KR101974301B1 - A symmetric bc-bch decoder for error correction of flash memory, an error correcting method and system using the sbc-bch decoder - Google Patents

Abstract

The present invention relates to a symmetric concatenated BCH decoder for error correction of a flash memory and an error correction method and system using the same. According to an embodiment of the present invention, the symmetric concatenated BCH (SBC-BCH) decoder for error correction of a flash memory comprises: a data input/output unit (code word FIFO) which receives data for error correction from a flash memory and generates a syndrome based on the received data for error correction at the same time; a syndrome buffer in which the data for error correction and the generated syndrome are stored; a key equation solver which generates a polynomial based on the syndrome for error correction; a Chien search unit which performs operation for finding the position of an error in the data for error correction based on the polynomial; and a syndrome tracker which performs operation for rearranging codes for operations performed by the Chien search unit.

Description

FIELD OF THE INVENTION [0001] The present invention relates to a symmetric concatenated BC decoder for error correction of a flash memory and an error correction method and system using the same.

The present invention relates to a symmetric concatenated BC decoder for error correction of a flash memory and an error correction method and system using the same. More particularly, the present invention relates to a symmetric concatenated BC decoder, (SBC-BCH) codes using a decoding scheme, and a method and system for correcting errors using the same.

NAND flash memory is a non-volatile memory in which stored data is retained even when no power is supplied. The built-in memory and SSD (solid-statedrive), which are data storage devices based on the non-volatile memory, And is widely used in portable devices such as cameras and computers.

Recently, as a main technique for increasing the degree of integration of NAND flash memories, there has been used a multi-level method of increasing the amount of information stored per cell and fine processing that reduces the size of a cell in which data is stored. In order to maintain the reliability of the NAND flash memory based data storage device at a high level, it is necessary to use an error control code having excellent correction capability because the application of such a technique increases errors of the NAND flash memory itself It is essential.

The error correcting codes can be roughly classified into soft-decision ECC and hard-decision ECC. The soft-error correcting code has a high error correcting performance, And it is difficult to realize a high output speed in accordance with the currently used flash memory. Therefore, it is required to develop a next - generation hard - decision error correcting code which improves the performance of the error correcting code, and a joint error correcting code using the information dependency between the individual error correcting codes has been developed.

Conventionally developed concatenated error correcting codes have a problem in that the relative increase in correction performance is not high compared to the increase in complexity. Therefore, a symmetric concatenated BC code having a triangular geometry has been developed. However, Patent Publication No. 10-1267958), there is a problem that it is difficult to effectively implement correction performance due to information dependency between symmetric concatenated BCAQ codes.

Korean Registered Patent No. 10-1267958 (Feb.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems and it is an object of the present invention to provide a symmetric concatenated BC decoder that is optimized for correcting errors using a symmetric concatenated BC code and a method and system for correcting errors using the symmetric concatenated BC decoder. .

In order to minimize the energy consumed in the flash memory for error correction, a symmetric concatenated BC decoder is constructed by using a rearrangement process of the ChienSearch and configured to have a higher computation speed and higher energy efficiency than conventional decoders. And to provide a method and a system for correcting an error by using the method.

A symmetric concatenated BC (SBC-BCH) decoder for error correction of a flash memory according to an embodiment of the present invention receives data for error correction from a flash memory and simultaneously receives data for error correction A data input / output unit (FIFO) for generating syndromes, a syndrome buffer for storing error correction data and generated syndromes, and a key equation solving unit for generating a polynomial based on a syndrome for error correction Equation Solver), a Chien Search for performing an operation for searching for a location of an error in data for error correction based on a polynomial, and an operation for reordering codes for operations performed in the Chien search portion And a syndrome tracker, wherein the plurality of CHAN search parts are formed, and each of the plurality of CHAN search parts comprises: It is connected in parallel to the equation solving unit, syndrome track portion may be formed so as to correspond to each of the plurality of Chien search section.

The data for error correction according to an embodiment of the present invention may include a symmetric concatenated BC code.

The syndrome tracking unit according to an embodiment of the present invention includes a main syndrome calculation unit for collecting all error patterns of respective constituent codes through a feedback path to estimate a difference between all syndromes, (Sub Syndrome Calculation) that estimates a sub-syndrome.

A symmetric concatenated BC (SBC-BCH) decoding system for error correction of a flash memory according to an embodiment of the present invention is characterized in that the error of data detected by the symmetric concatenated BC decoder and the symmetric concatenated BC decoder, An error manager for receiving the position and correcting the error, and a memory unit (SRAM) for storing data for decode and decoded data.

A method of correcting an error using a symmetric concatenated BC (SBC-BCH) code for error correction of a flash memory according to an embodiment of the present invention includes error correction from a flash memory through a data input / output unit (Codeword FIFO) A first step of receiving data for error correction and generating a syndrome on the basis of data for error correction inputted, a second step of storing data for error correction and the generated syndrome in a syndrome buffer, A third step of generating a polynomial in the Key Equation Solver based on the syndrome generated for the first time, and a third step of finding the position of the error in the data for error correction in the Chien Search based on the polynomial equation A fourth step of performing an operation for performing a computation for an operation performed by the Syntrome Tracker, And a fifth step of performing an operation on a plurality of Tien search parts, wherein each of the plurality of Tien search parts is connected in parallel to the key equation solution part, and the syndrome tracking part is formed to correspond to each of the plurality of Tien search parts .

According to an embodiment of the present invention, a method for correcting an error using a symmetric concatenated BC (SBC-BCH) code for error correction of a flash memory includes the steps of And the step of outputting the data to the flash memory via the data input / output unit.

The data for error correction according to an embodiment of the present invention may include a symmetric concatenated BC code.

The syndrome tracking unit according to an embodiment of the present invention includes a main syndrome calculation unit for collecting all error patterns of respective constituent codes through a feedback path to estimate a difference between all syndromes, (Sub Syndrome Calculation) that estimates a sub-syndrome.

According to another aspect of the present invention, there is provided a computer-readable recording medium storing a program for causing a computer to execute the above-described method.

According to the decoder and the error correction method and system using the decoder provided as one embodiment of the present invention, it is possible to improve the correction performance over the existing concatenated code using the symmetric concatenated BC code, and to use the symmetric concatenated BC code By implementing an optimized hardware structure, efficiency and speed of decoding operation can be improved as compared with the conventional decoder.

In addition, as a method for minimizing the energy consumed in the flash memory for error correction, the reordering process of the chip search can be used and implemented, and the improved error correction capability can be secured as compared with the prior art.

1 is a block diagram illustrating an example of a structure of a decoder supporting conventional BCAST for error correction.
FIG. 2 is a block diagram illustrating a configuration of a symmetric concatenated BC decoder according to an embodiment of the present invention. Referring to FIG.
3 illustrates a structure of a symmetric concatenated DBS code according to an embodiment of the present invention.
4 is a graph illustrating the performance of an error correcting code including a symmetric concatenated DBS code according to an embodiment of the present invention.
FIG. 5 is a diagram illustrating a decoding scheme using a conventional linear decoder and a decoding scheme of a symmetric concatenated DBase code according to an embodiment of the present invention.
FIG. 6 is a diagram illustrating an example of a rearrangement process of a Chiens search according to an embodiment of the present invention.
FIG. 7 is a block diagram illustrating a symmetric concatenated BC decoder and a memory according to an embodiment of the present invention. Referring to FIG.
FIG. 8 is a block diagram illustrating a syndrome tracking unit of a symmetric concatenated BC decoder according to an exemplary embodiment of the present invention. Referring to FIG.
FIG. 9 is a block diagram illustrating a structure of a symmetric concatenated BCAU decoding system according to an embodiment of the present invention. Referring to FIG.
10 is a block diagram illustrating a structure of a symmetric concatenated BCAST system according to an embodiment of the present invention.
11 is a flowchart illustrating a method of correcting errors using a symmetric concatenated DBase code according to an embodiment of the present invention.

The terms used in this specification will be briefly described and the present invention will be described in detail.

While the present invention has been described in connection with what is presently considered to be the most practical and preferred embodiment, it is to be understood that the invention is not limited to the disclosed embodiments. Also, in certain cases, there may be a term selected arbitrarily by the applicant, in which case the meaning thereof will be described in detail in the description of the corresponding invention. Therefore, the term used in the present invention should be defined based on the meaning of the term, not on the name of a simple term, but on the entire contents of the present invention.

When an element is referred to as " including " an element throughout the specification, it is to be understood that the element may include other elements as well, without departing from the spirit or scope of the present invention. Also, the terms " part, " " module, " and the like described in the specification mean units for processing at least one function or operation, which may be implemented in hardware or software or a combination of hardware and software .

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings, which will be readily apparent to those skilled in the art. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. In order to clearly illustrate the present invention, parts not related to the description are omitted, and similar parts are denoted by like reference characters throughout the specification.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram illustrating an example of a structure of a decoder supporting conventional BCAST for error correction.

Referring to FIG. 1, a conventional BC decoder for error correction includes a syndrome calculator (SC), a key-equation solver (KES), an error-position searcher EPS). In the decoding process using the conventional decoder, when a block corresponding to a syndrome operation unit generates a coefficient of an equation for finding an error through the data received from the flash memory, the error of the data in the block corresponding to the key- And a block corresponding to the error-position search unit inputs an arbitrary answer into the equation and calculates the position of the error. The operation of each block is performed in units of information blocks. When one operation is completely performed, the output proceeds in the order of corrected information unit blocks.

Conventional BC decoders are designed in a pipelined structure in which each decoding block is designed to continuously perform an operation in order to increase the processing speed significantly. Generally, a pipeline structure can be created due to the dependency of the sign when the concatenated code is used There is no problem. Therefore, it is not only impossible to perform the operations redundantly, but also the inefficient operation of increasing the memory access is performed continuously by the necessity of the full-row precedence of the operation of the previous constituent code due to the interdependence of the information blocks, In order to improve the structure, it is impossible to increase the operation speed through the configuration for parallelizing the blocks.

2 is a block diagram illustrating a configuration of a symmetric type DBase decoder 100 according to an embodiment of the present invention.

Referring to FIG. 2, a symmetric concatenated BC (SBC-BCH) decoder 100 for error correction of a flash memory according to an embodiment of the present invention receives data for error correction from a flash memory A data input / output unit 110 (Codeword FIFO) for generating a syndrome on the basis of data for error correction received, a syndrome buffer 120 for storing data for error correction and a generated syndrome, (Key Equation Solver) 130 for generating a polynomial based on the syndrome for the error correction, a chien search unit 140 for performing an operation for finding the position of an error in data for error correction based on the polynomial And a syndrome tracker 150 for performing an operation for rearranging codes for operations performed by the Chien search unit 140. The Chien search unit 140 includes a syndrome tracking unit 150, Each of the plurality of CHN search units 140 is connected to the key equation solving unit 130 in parallel and the syndrome tracking unit 150 is formed to correspond to each of the plurality of CHN search units 140 .

Conventional BC decoders, as described above, are difficult to increase the computation speed due to the difficulty of pipelining or parallelization and the inefficient operation. Therefore, in order to solve this problem, it is necessary to reduce inefficient memory access . Applying the pre-operation method of the syndrome operation unit that accesses the memory first can increase the speed even partially. This can be implemented by applying the method of storing the initial syndrome operation in the buffer at the same time as receiving the data from the flash memory Which can reduce the consumption of computation cycles compared to existing structures. In addition, when such a buffer storage technique is used, it is possible to perform a Chiensearch immediately when a unit operation of a block having a dependency in the following operation is completed. Therefore, have.

That is, the symmetric concatenated DBase decoder 100 according to an embodiment of the present invention includes a data input / output unit 110 for receiving syndrome data and generating a syndrome by receiving data from a flash memory, And a syndrome buffer 120 for storing data, and the operation of the data input / output unit 110 and the operation of storing the operation result in the syndrome buffer 120 can be performed at the same time. In addition, according to an embodiment of the present invention, a plurality of CHN search units 140 are formed and a plurality of CHANNEL search units 140 are connected in parallel with the key equation solver unit 130, So that the waiting time for the decoding operation can be shortened.

However, even after the data input / output unit 110 and the syndrome buffer 120 are configured and the plurality of CHANNEL search units 140 are configured in parallel, according to the embodiment of the present invention, The use rate gradually decreases as the decoding process proceeds. To solve this problem, search can be used for realignment. The re-ordering refers to the way in which the code is rearranged when the Chiensearch is performed and processed so that the Chiensearch can operate immediately after the key equation is solved. The method of rearrangement of the specific CHN search will be described later. In order to support rearrangement of the CHN search, the symmetric concatenated BC decoder 100 according to an embodiment of the present invention may include a syndrome tracking unit 150. That is, since the syndrome for the succeeding constituent code can be updated through the buffer 120 by reflecting the data block corresponding to the position of the error found by the current value search through the syndrome tracking unit 150 in real time, It is possible to realize an optimum calculation speed and correction performance.

3 illustrates a structure of a symmetric concatenated DBS code according to an embodiment of the present invention.

Conventional concatenated codes can improve the correction performance by combining codes having short code lengths in a geometric structure and performing repetitive operations by repairing data blocks that can not be repaired through full decoding. However, Which is not as high as the increase in complexity.

In order to overcome this problem, the triangular geometric structure of the symmetric concatenated code according to an embodiment of the present invention uses a starting point of a code in the form of a right triangle as shown in FIG. 3, and each constituent code uses a BC code having a short code length . The direction of the code advances to the right or the lower right, and finally, the parity information block ends, and each code shares some information unit blocks, thereby improving the correction performance.

4 is a graph illustrating the performance of an error correcting code including a symmetric concatenated DBS code according to an embodiment of the present invention.

That is, the graph of FIG. 4 shows the result of verifying and evaluating the correction capability of the code through software simulation, and the raw bit-error rate (RBER) of the horizontal axis indicates the error occurrence probability of the data itself read from the flash memory , Which is the same concept as the uncoded bit-error rate used mainly in communication systems. The uncorrectable bit-error rate (UBER) on the vertical axis means the ratio of the error that is not corrected even through the correcting code (the required reliability measure of the system).

Referring to FIG. 4, when comparing the latest correction codes for supporting the existing flash memory, it can be determined that the code that can sustain a higher RBER on the same UBER line is a better correction code. Therefore, the symmetric concatenated BCN (SBC-BCH) has a higher performance than the conventional hard decision codes, and has higher performance than the LDPC code of the low correction performance ([5]) used as the soft decision code Can be confirmed. In addition, although the high-performance LDPC code ([4], [6]) shows relatively higher performance than other hard decision codes including symmetric concatenated BC code, it has a fatal disadvantage of high power consumption and low life of the flash memory Therefore, symmetric concatenated BC code is more accurate than other hard decision and soft decision codes in terms of correction performance and energy efficiency.

FIG. 5 is a diagram illustrating a decoding scheme using a conventional linear decoder and a decoding scheme of a symmetric concatenated DBase code according to an embodiment of the present invention.

Referring to FIG. 5 (a), a decoding method using a conventional linear BC decoder performs a syndrome operation, a key equation solving, and a solving process for each constituent code sequentially, Therefore, it can be confirmed that there is a problem that 3600 cycles are required for calculation.

Referring to FIG. 5B, a data input / output (I / O) unit for reading data from a flash memory and calculating a syndrome and storing the syndrome in a buffer 120 is provided to a symmetric type DBase decoder 100 according to an embodiment of the present invention. When a syndrome generator 140 configured in parallel with the syndrome buffer 110 and the syndrome buffer 120 is included, a syndrome operation is performed on each of the codewords, and there is no need to proceed to the next operation, It can be confirmed that the operation of the codes proceeds simultaneously. In particular, since the cycle required for the operation is reduced to 3360 cycles, it can be seen that the operation speed is increased compared to the conventional decoder, which can be confirmed through FIG. 5 (a). However, as described above with reference to FIG. 2, as the computation proceeds, a wasteful cycle of waiting for the start of decoding of the correction code gradually increases, thereby causing a problem that hardware utilization is reduced.

5 (c), in order to solve the problem occurring in FIGS. 5 (a) and 5 (b), in the symmetric concatenated DBase decoder 100 according to the embodiment of the present invention, the syndrome tracking unit 150 ), It is possible to greatly reduce the cycle time required for the computation to 1760 cycles, thereby realizing stabilization and optimized correction performance and computation speed.

FIG. 6 is a diagram illustrating an example of a rearrangement process of a Chiens search according to an embodiment of the present invention.

As described above, the rearrangement of the Tien search is a method in which codes are rearranged so that the key equation search can be performed after the calculation of the key equation solution, and the process of wasting for decoding can be greatly reduced through this process. In the case of the BCCH code, there is no problem in correcting the error based on the position of the finally found error even if the order of operation of the data block in the code is not mathematically maintained. Therefore, The code can be rearranged by treating all shared data blocks in a direction to be subordinate to data blocks that do not have a dependency after the zero block, and the decoded output result can be the same as before the reordering.

FIG. 7 is a block diagram illustrating a symmetric concatenated BC decoder 100 and a memory unit 300 according to an embodiment of the present invention. FIG. 8 is a block diagram of a symmetric concatenated BC decoder < RTI ID = 0.0 > 100 of the syndrome tracking unit 150 shown in FIG.

7 and 8, a syndrome tracking unit 150 according to an exemplary embodiment of the present invention includes a main syndrome calculation unit 151 for collecting a total error pattern of each constituent code through a feedback path and estimating a difference between all syndromes, (Main Syndrome Calculation) and a sub syndrome calculation unit 152 (Sub Syndrome Calculation) for estimating the difference between the partial syndromes of the respective constituent codes.

The syndrome tracking unit 150 estimates a syndrome difference of a constituent code whenever an error is found through the channel searching unit 140 in the decoding process and stores the syndrome difference in the buffer 120 to support reordering of codes for improving the correction performance The main syndrome calculation unit 151 included in the syndrome tracking unit 150 collects the entire error pattern of the corresponding configuration code when a predetermined configuration code is operated in the predetermined chip search unit 140 The syndrome can be updated by accessing the syndrome buffer 120 at once by accumulating the differences of the cumulative total syndromes of the respective constituent codes. The sub syndrome calculation unit 152 included in the syndrome tracking unit 150 performs a predetermined syndrome calculation when a predetermined configuration code is calculated in the predetermined value search unit 140, The syndrome can be updated by accessing the syndrome buffer 120 immediately after estimating the difference of the partial syndrome included in the code. Therefore, when the TNS search unit 140 is in operation, only the sub syndrome operation unit 152 can access the syndrome differences in the syndrome buffer 120. [

Referring to FIG. 8, the syndrome tracking unit 150 can confirm how an operation is performed in accordance with each cycle operation sequence. The operation formula for the configuration code performed by each configuration of the syndrome tracking unit 150 can be specifically examined in the following [Table 1].

[Table 1]

In this case, C (x) is a codeword of a constituent code, D (x) is each data block constituting a constituent code, S (x) is a syndrome for a constituent code, and Z _pd (X) .

If the alpha value (a predetermined value input in the syndrome generation process) is substituted into C (x) for the syndrome calculation, the multiplier becomes D (x) multiplied by a different value. If the plurality of arithmetic operations on the same D (x) as in the main syndrome arithmetic operation unit 151 and the sub syndrome arithmetic operation unit 152 shown in FIG. 5 are constructed so that they can be simply multiplied by different values of the multiplier, As a result, the number of operation cycles can be significantly reduced.

Referring to FIG. 8, since the output through the cube search unit 140 is C (x) whose error has been corrected or needs to be corrected, the multiplier value of? Is not sequentially output in order to use the code reordering technique , The multiplier value of? May be designed to be adjusted according to a predetermined rule in order to perform a syndrome operation so as to match the multiplier value of? Defined in the previous operation. The structure design of the symmetric concatenated BC decoder 100 according to an embodiment of the present invention can solve the speed reduction problem due to the dependency problem between the conventional data blocks, Speed can be increased 8 times or more.

FIG. 9 is a block diagram illustrating a structure of a symmetric concatenated BCAST system according to an embodiment of the present invention. FIG. 10 is a block diagram illustrating a structure of a symmetric concatenated BCAST system according to an embodiment of the present invention. Another example.

9 and 10, a symmetric type SBC-BCH decoding system for error correction of a flash memory according to an embodiment of the present invention includes a symmetric concatenated BC decoder 110, An error manager 200 for receiving an error location of data detected by the BC decoder 100 and correcting the error and a memory unit 300 for storing data for decoding error and decoded data ) ≪ / RTI > (SRAM).

That is, when the symmetric concatenated BC decoder 100 according to an embodiment of the present invention detects an error position of data received from the flash memory, the error is corrected based on the error position detected by the error management unit 200 The system can be operated in such a manner that not only the data received from the flash memory and the decoded data but also the related data necessary for decoding are stored in the memory unit 300 for error correction.

11 is a flowchart illustrating a method of correcting errors using a symmetric concatenated DBase code according to an embodiment of the present invention.

11, a method of correcting an error using a symmetric concatenated BC (SBC-BCH) code for error correction of a flash memory according to an embodiment of the present invention includes a data input / output unit 110 (Codeword FIFO A first step S100 for generating a syndrome on the basis of data for error correction received from the flash memory, a data for error correction, and a syndrome generated in the syndrome buffer A third step S300 of generating a polynomial in the key equations solver 130 based on the syndrome generated for error correction, a second step S200 of storing the syndrome in the syndrome buffer 120, A fourth step S400 and a syndrome tracker 150 for performing an operation for searching for an error position of data for error correction in a Chien search unit 140 based on a polynomial, Tooth And a fifth step S500 of performing an operation for rearranging codes for an operation to be performed in the search unit 140. The plurality of chien search units 140 are formed in a plurality of chien search units 140, And the syndrome tracking unit 150 may be formed to correspond to each of the plurality of CHN search units 140. In this case,

Referring to FIG. 11, according to an embodiment of the present invention, the second through fifth steps described above are repeatedly performed in a method of correcting errors using a symmetric concatenated DBS code for error correction of a flash memory And outputting the decoded data to the flash memory via the data input / output unit 110 (S600).

According to an embodiment of the present invention, when a symmetric concatenated BC code is used, an operation process must be repeatedly performed to find and correct an error position with respect to constituent codes including a plurality of data blocks. Therefore, And the fifth step is repeatedly performed, the error location detection and error correction are repeated, and the finally decoded data can be output to the flash memory. In other words, in addition to the syndrome generated through the error detection process by the decoder 100, the error correction process through the error management unit 200, and the initial calculation, as well as the syndrome tracking unit 150 according to an embodiment of the present invention The process of storing all the contents of the estimated syndromes and the error-corrected data blocks and the like through the syndrome buffer 120 of the decoder 100 and the memory unit 300 on the system is repeated, The corrected clean data can be output to the flash memory.

The contents of the above-described apparatus can be applied in connection with the method according to an embodiment of the present invention. Therefore, the description of the same contents as those of the above-described apparatus with respect to the method is omitted.

According to another aspect of the present invention, there is provided a computer-readable recording medium storing a program for causing a computer to execute the above-described method. In other words, the above-described method can be implemented in a general-purpose digital computer that can be created as a program that can be executed in a computer and operates the program using a computer-readable medium. Further, the structure of the data used in the above-described method can be recorded on a computer-readable medium through various means. Recording media that record executable computer programs or code for carrying out the various methods of the present invention should not be understood to include transient objects such as carrier waves or signals. The computer-readable medium may comprise a storage medium such as a magnetic storage medium (e.g., ROM, floppy disk, hard disk, etc.), optical readable medium (e.g., CD ROM, DVD, etc.).

It will be understood by those skilled in the art that the foregoing description of the present invention is for illustrative purposes only and that those of ordinary skill in the art can readily understand that various changes and modifications may be made without departing from the spirit or essential characteristics of the present invention. will be. It is therefore to be understood that the above-described embodiments are illustrative in all aspects and not restrictive. For example, each component described as a single entity may be distributed and implemented, and components described as being distributed may also be implemented in a combined form.

It is intended that the present invention covers the modifications and variations of this invention provided they come within the scope of the appended claims and their equivalents. .

100: symmetric concatenated BC decoder
110: Data input / output unit 120: Syndrome buffer
121: Buffer Management Unit 130: Key Equation Solving Unit
140: Chien search section 150: Syndrome tracking section
151: main syndrome operation unit 152: sub syndrome operation unit
200: error management unit 300: memory unit

Claims (9)

A symmetric concatenated BC (SBC-BCH) decoder for error correction of a flash memory,
A data input / output unit (FIFO) for receiving error correction data from the flash memory and generating a syndrome based on the error correction data;
A syndrome buffer in which the error correction data and the generated syndrome are stored;
A key equation solver for generating a polynomial based on the syndrome for error correction;
A Chien Search unit for performing an operation for searching for a position of an error of the data for error correction based on the polynomial; And
And a syndrome tracker for performing an operation for rearranging the configuration codes of the data for error correction for the operation performed by the CHN search unit,
Wherein each of the plurality of CHN search units is connected to the key equation solving unit in parallel,
And a plurality of syndrome tracking units are formed to correspond to each of the plurality of CHN search units.
The method according to claim 1,
Wherein the data for error correction includes a symmetric concatenated BC code. ≪ RTI ID = 0.0 > 18. < / RTI >
The method according to claim 1,
A main syndrome calculator for collecting a total error pattern of each of the constituent codes through a feedback path and estimating a difference of the entire syndromes; And a Sub Syndrome Calculation unit for estimating a difference between partial syndromes of the respective constituent codes.
A symmetric concatenated BC (SBC-BCH) decoding system for error correction of a flash memory,
A symmetric concatenated BC decoder according to claim 1;
An error manager for receiving a position of an error of data detected by the symmetric concatenated BC decoder and correcting the error; And
And a memory unit (SRAM) for storing the data for error correction and the decoded data.
A method for correcting an error using a symmetric concatenated BC (SBC-BCH) code for error correction of a flash memory,
A first step of receiving data for error correction from the flash memory through a data input / output unit (Codeword FIFO) and generating a syndrome based on the input error correction data;
A second step of storing the error correction data and the generated syndrome in a syndrome buffer;
A third step of generating a polynomial in a Key Equation Solver based on a syndrome generated for the error correction;
A fourth step of performing an operation for searching for a position of an error of the data for error correction in a Chien search section based on the polynomial; And
And a fifth step of performing an operation for rearranging the configuration codes of the data for error correction in order to perform an operation in the syndrome section at a syndrome tracker,
Wherein each of the plurality of CHN search units is connected to the key equation solving unit in parallel,
Wherein a plurality of syndrome tracking units are formed to correspond to each of the plurality of CHN search units.
6. The method of claim 5,
And outputting the decoded data to the flash memory through the data input / output unit. The method of claim 1, further comprising: .
6. The method of claim 5,
Wherein the data for error correction includes a symmetric concatenated BCN code. ≪ RTI ID = 0.0 > 11. < / RTI >
6. The method of claim 5,
A main syndrome calculator for collecting a total error pattern of each of the constituent codes through a feedback path and estimating a difference of the entire syndromes; And a sub-syndrome calculator for estimating a difference between the partial syndromes of each of the constituent codes.
9. A computer-readable recording medium on which a program for implementing the method of any one of claims 5 to 8 is recorded.

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