KR101969766B1 - Apparatus and method for recognizing iris - Google Patents

Abstract

An iris recognition apparatus and method are disclosed. An iris recognition apparatus according to an embodiment of the present invention includes an image sensor unit for acquiring an iris image of a user using an image sensor; And an iris recognition unit for recognizing the iris of the user by using an iris image acquired from the image sensor set by the register.

Description

[0001] APPARATUS AND METHOD FOR RECOGNIZING IRIS [0002]

The present invention relates to an iris recognition technique, and more particularly, to a register setting technique of an image sensor for acquiring an iris image.

The iris recognition technology uses infrared illumination to increase the iris recognition rate. If natural light is used for the iris recognition technique, there is a disadvantage that the pupil of the pupil is reflected, the iris and pupil edges are unclear, and the iris band is not clear.

Therefore, the iris recognition apparatus can extract the iris image using the infrared illumination. At this time, since the iris recognition device derives the iris image from the reflected infrared image, the iris recognition rate can be increased. However, when the iris recognition apparatus utilizes infrared illumination, there is a disadvantage that it is sensitive to external illumination.

In order to overcome the disadvantage that the iris recognition apparatus is sensitive to external illumination, there is a solution for adaptively adjusting the infrared illumination so as to be insensitive to external illumination. To this end, the conventional iris recognition apparatus uses an average value of an image to adjust the gain value and exposure time of the image sensor and adjust the light intensity of the IR-LED. However, rather than calculating the average value in the FPGA module, it is easy to calculate floating point fractions in a convenient outsourced computing device (PC, etc.). However, when the average value of the image is obtained from the PC, the communication between the PC and the device (USB or other interface device) and the I2C method are performed in order to access the register and the gain register related to the integration time of the image sensor. It must go through an image sensor and a microcomputer or other control device. In this case, the time for setting the register of the image sensor does not match with the adjustment time of the light intensity of the IR-LED, which increases the error, and may cause a problem of being more sensitive to external illumination.

Korean Patent No. 10-1511326 entitled " Iris and Face Image Capture Device " is a device for capturing an iris image and a face image effectively by guiding a user to a distance suitable for iris image capture from the iris recognition device .

However, Korean Patent No. 10-1511326 is sensitive to external illumination because it uses infrared rays.

The present invention aims to overcome the sensitivity of an image sensor for acquiring a user's iris image to external illumination changes.

It is another object of the present invention to provide an internal register setting for an image sensor, thereby improving an error occurring in an iris image acquisition process.

It is also an object of the present invention to provide an FPGA module for calculating an average value of an image for providing a register setting.

According to an aspect of the present invention, there is provided an iris recognition apparatus including an image sensor unit for acquiring an iris image of a user using an image sensor; And an iris recognition unit for recognizing the iris of the user by using an iris image acquired from the image sensor set by the register.

In this case, the image sensor setting unit may include an FPGA calculation unit for calculating an average value of an image per frame of the iris image; A register setting unit for setting a register of the image sensor based on the image average value, and an image transmitting unit for transmitting the iris image to the iris recognition unit.

In this case, the FPGA calculation unit may calculate the image average value in units of pixels of the iris image using an FPGA (Field-Programmable Gate Array) module.

At this time, the FPGA calculation unit may calculate the image average value by receiving the cumulative average value, the current pixel value, and the number of pixels of the previous pixels, which are previously stored in the FPGA module.

At this time, the FPGA calculation unit can calculate the image average value by performing a floating point operation of the FPGA module.

In this case, the FPGA calculation unit can perform the floating point operation using the divider module included in the FPGA module.

In this case, the FPGA calculation unit calculates the difference between the cumulative average value of the previously stored previous pixels and the current pixel value, and inputs the difference value and the number of pixels to the divider module, Can be calculated.

At this time, the FPGA calculation unit may calculate the intermediate value in addition to the quotient by rounding the residual value, and calculate the image average value by subtracting the intermediate value from the cumulative average value of the previously stored previous pixels.

According to another aspect of the present invention, there is provided an iris recognition method including acquiring an iris image of a user using an image sensor, Calculating an image mean value of the iris image; Setting a register of the image sensor based on the image average value; And recognizing the iris of the user using the iris image obtained from the image sensor to which the register is set.

In this case, the step of calculating the image average value may calculate the image average value in units of pixels of the iris image using an FPGA (Field-Programmable Gate Array) module.

In this case, the step of calculating the image average value may calculate the image average value using the cumulative average value, the current pixel value, and the number of pixels of the previous pixels previously stored in the FPGA module.

At this time, in the step of calculating the average value of the image, the FPGA module may perform a floating point operation to calculate the image average value.

At this time, the floating-point operation can be performed using the divider module included in the FPGA module.

In this case, the calculating of the image average may include calculating the difference between the cumulative average value of the previously stored previous pixels and the current pixel value, and inputting the difference value and the number of the pixels to the divider module Quotient and remainder values can be calculated.

In this case, the step of calculating the image average value may calculate the image average value by rounding the residual value to calculate the intermediate value in addition to the quotient, and subtracting the intermediate value from the cumulative average value of the previously stored previous pixels.

The present invention aims to overcome the sensitivity of an image sensor for acquiring a user's iris image to external illumination changes.

It is another object of the present invention to provide an internal register setting for an image sensor, thereby improving an error occurring in an iris image acquisition process.

It is also an object of the present invention to provide an FPGA module for calculating an average value of an image for providing a register setting.

FIG. 1 and FIG. 2 are views illustrating a vertical blanking interval for an exposure time of an image sensor according to an exemplary embodiment of the present invention. Referring to FIG.
3 and 4 are views showing an example of a register setting process of the image sensor.
5 is a diagram illustrating a register setting process according to an embodiment of the present invention.
6 is a block diagram illustrating an iris recognition apparatus according to an embodiment of the present invention.
FIG. 7 is a detailed block diagram illustrating an example of the image sensor setting unit shown in FIG.
FIG. 8 is a detailed diagram illustrating an FPGA module included in the FPGA calculation unit shown in FIG.
9 is a flowchart illustrating an iris recognition method according to an embodiment of the present invention.

The present invention will now be described in detail with reference to the accompanying drawings. Hereinafter, a repeated description, a known function that may obscure the gist of the present invention, and a detailed description of the configuration will be omitted. Embodiments of the present invention are provided to more fully describe the present invention to those skilled in the art. Accordingly, the shapes and sizes of the elements in the drawings and the like can be exaggerated for clarity.

Throughout the specification, when an element is referred to as " comprising ", it means that it can include other elements as well, without excluding other elements unless specifically stated otherwise.

Hereinafter, preferred embodiments according to the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 and FIG. 2 are views illustrating a vertical blanking interval for an exposure time of an image sensor according to an exemplary embodiment of the present invention. Referring to FIG.

Referring to FIGS. 1 and 2, a vertical blanking interval for an exposure time of an image sensor according to an exemplary embodiment of the present invention is shown.

As shown in FIG. 1, when the acquisition time (Readout Time) is larger than the exposure time (10), the vertical blanking interval 20 is shortened.

Also, as shown in FIG. 2, when the exposure time 30 is greater than the acquisition time (Readout Time), the vertical blanking interval 40 becomes longer.

3 and 4 are views showing an example of a register setting process of the image sensor.

Referring to FIG. 3, when an average value of the image of the previous frame (n-1 frame) is obtained in the register setting process and is set to the current frame (n frame) in the integration time 50, (N + 2) instead of the second frame (n + 1).

That is, a delay of one frame may occur in the process of transmitting an iris image to an external computer device (PC or the like) and calculating an average value of the image and receiving the image.

If an image sensor transmits an iris image to an external computer device via a USB interface, if the loss of frame data occurs, a large deviation in the gray value of the instantaneous raw data may occur.

Referring to FIG. 4, FIG. 3 is shown in more detail.

If an image average value calculation is started at the start of N frames, the average value 60-1 of the image in the (N + 1) th frame after N frames can be calculated.

At this time, the register value 60-2 of the image sensor may be calculated based on the image average value in the (N + 1) -th frame

Further, the register value may be set at the start time of the N + 2 frame in the image sensor, and the average value of the iris image acquired at the set exposure time of the register value may be reflected in the N + 3 frame.

Accordingly, in the present invention, an iris recognition apparatus and method for quickly responding to an external illumination change by advancing an image average value one frame ahead are proposed.

5 is a diagram illustrating a register setting process according to an embodiment of the present invention.

Referring to FIG. 5, it can be seen that an image average value 70-1 is calculated at the time of N-frame type in the register setting process according to an embodiment of the present invention.

At this time, the register value 70-2 calculated immediately from the image average value 70-1 is immediately reflected and set in the immediately following N + 1 frame, and the average value of the image obtained in the exposure time is reflected in the (N + 2) Able to know.

6 is a block diagram illustrating an iris recognition apparatus according to an embodiment of the present invention. FIG. 7 is a detailed block diagram illustrating an example of the image sensor setting unit shown in FIG. FIG. 8 is a detailed diagram illustrating an FPGA module included in the FPGA calculation unit shown in FIG.

Referring to FIG. 6, an iris recognition apparatus according to an embodiment of the present invention includes an image sensor unit 110, an image sensor setting unit 120, and an iris recognition unit 130.

The image sensor unit 110 can acquire a user's iris image using the image sensor.

At this time, the image sensor unit 110 can acquire an iris image by irradiating the iris of the user with infrared light.

At this time, the image sensor unit 110 can control the exposure time of the image sensor and the irradiation of the infrared light based on the set register.

The image sensor setting unit 120 may set the register of the image sensor by calculating the average value of the image using the iris image.

Referring to FIG. 7, the image sensor setting unit 120 may include an FPGA calculation unit 121, a register setting unit 122, and an image transmission unit 123.

The FPGA calculation unit 121 can calculate an image average value of each iris image.

In this case, the FPGA calculation unit 121 may calculate an image average value in units of pixels of the iris image using an FPGA (Field-Programmable Gate Array) module.

At this time, the FPGA calculation unit 121 may receive the cumulative average value, the current pixel value, and the number of pixels of the previous pixels, which are previously stored in the FPGA module, and calculate the image average value.

At this time, the FPGA calculation unit 121 can calculate an image average value using Equation (1).

At this time, the FPGA calculation unit 121 can perform a floating point operation to implement Equation (1) as an FPGA module.

That is, the FPGA calculation unit 121 can calculate an average value of an image by performing a floating point operation on the FPGA module.

Referring to FIG. 8, an FPGA module included in the FPGA calculation unit 121 and calculating an average value of the image is shown in detail.

In this case, the FPGA module may include the divider module 140 which can be constructed according to Equation (1) and can perform floating point operation to reduce errors.

At this time, the FPGA module can declare all variables as unsigned values.

At this time, the FPGA calculation unit 121 can perform floating point operation using the divider module 140 included in the FPGA module.

In this case, as an example of the FPGA module, the FPGA module may correspond to the Spartan-6 product of Zilinx, and the divider module 140 may correspond to the Divider IP Core provided by Zilinx.

At this time, the FPGA calculation unit 121 can output the cumulative average value of the previous pixels according to the predetermined clock (CLK) using the D flip / flop (D F / F) module included in the FPGA module.

At this time, the FPGA calculation unit 121 may input an initial value of 0 to the D flip / flop module when there is no cumulative average value of previous pixels.

At this time, the FPGA calculation unit 121 can calculate the difference value between the cumulative average value of the previous pixels and the current pixel value (Pixel Value) of the FPGA module.

At this time, the FPGA calculation unit 121 inputs the difference value and the number of pixels (Count) to the divider module 140, and the divider module can output the quotient and the remaining value Remainder.

At this time, the FPGA calculation unit 121 can round the remaining value through the ROUND module, and calculate the intermediate value by adding the remaining rounded value to the quotient using the OR gate module.

At this time, the FPGA calculation unit 121 calculates an average value of the image by subtracting the intermediate value from the cumulative average value of the previously stored previous pixels, and outputs the average value.

The register setting unit 122 can set a register of the image sensor based on the image average value.

At this time, the register setting unit 122 may calculate the exposure time of the image sensor and the register value for controlling the infrared illumination based on the image average value.

At this time, the register setting unit 122 may transmit the calculated register value to the image sensor unit 110 to set a register of the image sensor.

At this time, the register setting unit 122 may set an integration time related register and a gain register based on the image average value.

The image transmitting unit 123 may transmit the iris image to which the average value of the images has been calculated, to the iris recognition unit 130.

The iris recognition unit 130 can recognize the iris of the user using the iris image acquired from the image sensor in which the register is set.

At this time, the iris recognition unit 130 receives the iris image according to a predetermined vertical sync, and recognizes the user from the iris image.

9 is a flowchart illustrating an iris recognition method according to an embodiment of the present invention.

Referring to FIG. 9, the iris recognition method according to an embodiment of the present invention may first acquire an image (S210).

That is, in step S210, the iris image of the user can be acquired using the image sensor.

At this time, the step S210 can acquire the iris image by irradiating the iris of the user with infrared light.

At this time, step S210 may control the exposure time of the image sensor and the irradiation of infrared light based on the set register.

In addition, the iris recognition method according to an embodiment of the present invention may calculate an image average value (S220).

That is, in step S220, the average value of the image per frame of the iris image can be calculated.

At this time, in step S220, an image average value can be calculated in units of pixels of the iris image using an FPGA (Field-Programmable Gate Array) module.

At this time, the FPGA module may calculate the average value of the image by receiving the accumulated average value of the previous pixels, the current pixel value, and the number of pixels.

In this case, in step S220, the average value of the image can be calculated using Equation (1).

In this case, step S220 may perform a floating point operation to implement Equation (1) as an FPGA module.

That is, in step S220, the FPGA module may perform a floating point operation to calculate an image average value.

In this case, the FPGA module may include the divider module 140 which can be constructed according to Equation (1) and can perform floating point operation to reduce errors.

At this time, the FPGA module can declare all variables as unsigned values.

In this case, the floating-point operation may be performed using the divider module 140 included in the FPGA module in step S220.

In this case, as an example of the FPGA module, the FPGA module may correspond to the Spartan-6 product of Zililinx, and the divider module 140 may correspond to the Divider IP Core provided by Zilinx.

At this time, the step S220 may output a cumulative average value of the previous pixels according to a predetermined clock (CLK) using the D flip / flop (D F / F) module included in the FPGA module.

In this case, in step S220, if the cumulative average value of the previous pixels does not exist, the initial value may be input to the D flip / flip module as 0.

At this time, the step S220 may calculate the difference value between the accumulated average value of the previous pixels and the current pixel value (Pixel Value) of the FPGA module.

At this time, in step S220, the difference value and the number of pixels (Count) are input to the divider module 140, and the divider module outputs the quotient and the remaining value Remainder.

In this case, in step S220, the remaining value may be rounded off through the ROUND module, and the remaining value rounded up using the OR gate module may be added to the quotient to calculate the intermediate value.

In this case, in step S220, the intermediate value is subtracted from the accumulated average value of the previously stored previous pixels, and the average value of the image is calculated and output.

In addition, the iris recognition method according to an embodiment of the present invention may perform register setting (S230).

That is, step S230 may set the register of the image sensor based on the image average value.

At this time, the step S230 may calculate the exposure time of the image sensor and the register value for controlling the infrared illumination based on the image average value.

At this time, the step S230 may transmit the calculated register value to the image sensor unit 110 to set the register of the image sensor.

At this time, step S230 may transmit the iris image in which the image average value is calculated.

At this time, the step S230 may set an integration time related register and a gain register based on the image average value.

In addition, the iris recognition method according to an embodiment of the present invention may perform iris recognition (S240).

That is, in step S240, the iris of the user can be recognized using the iris image acquired from the image sensor in which the register is set.

At this time, the step S240 receives the iris image according to the preset vertical sync, and recognizes the user from the iris image.

As described above, the iris recognition apparatus and method according to an embodiment of the present invention are not limited to the configuration and method of the embodiments described above. All or some of the embodiments may be selectively combined.

10, 30: Exposure Time (Exposure Time)
20, 40: Vertical Blanking Interval
50: frame start section 60-1: image average value
60-2: register setting value 70-1: image average value
70-2: Register setting value 110: Image sensor section
120: image sensor setting unit 121: FPGA calculation unit
122: register setting unit 123: image transmission unit
130: iris recognition unit

Claims (15)

An image sensor unit for acquiring a user's iris image using an image sensor;
An image sensor setting unit for calculating an average value of the image using the iris image and setting a register of the image sensor; And
An iris recognition unit for recognizing the iris of the user using the iris image acquired from the image sensor to which the register is set;
Lt; / RTI >
The image sensor setting unit
Setting a register for controlling the exposure time and the infrared illumination of the image sensor based on the average value of the image calculated in the current frame of the iris image and setting a register for controlling the infrared illumination based on the register, Lt; RTI ID = 0.0 > infrared < / RTI >
The image sensor setting unit
Calculating an average value of an image from a predetermined previous frame of the current frame to an end time of the current frame, calculating a register value from the average value of the image, and comparing the end time of the current frame with a preset next frame Setting the register value to the image sensor between a start time,
Wherein the image sensor sets the exposure start time of the image sensor between the start time of the next frame and the end time of the predetermined next frame based on the register value. The method according to claim 1,
The image sensor setting unit
An FPGA calculating unit for calculating an average value of an image per frame of the iris image;
A register setting unit for setting a register of the image sensor based on the image average value; And
An image transmitting unit for transmitting the iris image, on which the image average value is calculated, to the iris recognition unit;
And an iris recognition device for recognizing the iris. The method of claim 2,
The FPGA calculation unit
And calculates the image average value in units of pixels of the iris image using an FPGA (Field-Programmable Gate Array) module. The method of claim 3,
The FPGA calculation unit
Wherein the FPGA module receives the cumulative average value, the current pixel value, and the number of pixels of the previous pixels previously stored, and calculates the image average value. The method of claim 4,
The FPGA calculation unit
Wherein the FPGA module performs a floating point operation to calculate the image average value. The method of claim 5,
The FPGA calculation unit
Wherein the floating point operation is performed using a divider module included in the FPGA module. The method of claim 6,
The FPGA calculation unit
Wherein the FPGA module calculates a difference value between the cumulative average value of the previously stored pixels and the current pixel value and inputs the difference value and the number of pixels to the divider module to output a quotient and a remaining value Iris recognition device. The method of claim 7,
The FPGA calculation unit
Rounding off the remaining value to calculate the intermediate value in addition to the quotient,
And calculates the image average value by subtracting the intermediate value from the cumulative average value of the previously stored previous pixels. A method of using an iris recognition apparatus,
Acquiring a user's iris image using an image sensor;
Calculating an image mean value of the iris image;
Setting a register of the image sensor based on the image average value;
Recognizing the iris of the user using the iris image obtained from the image sensor in which the register is set;
Lt; / RTI >
The step of setting the register
Setting a register for controlling the exposure time and the infrared illumination of the image sensor based on the average value of the image calculated in the current frame of the iris image and setting a register for controlling the infrared illumination based on the register, Lt; RTI ID = 0.0 > infrared < / RTI >
The step of setting the register
Calculating an average value of an image from a predetermined previous frame of the current frame to an end time of the current frame, calculating a register value from the average value of the image, and comparing the end time of the current frame with a preset next frame Setting the register value to the image sensor between a start time,
Wherein the image sensor sets an exposure start time of the image sensor between a start time of the next frame and an end time of the predetermined next frame based on a register value. The method of claim 9,
The step of calculating the image mean value
Wherein the image average value is calculated in units of pixels of the iris image using an FPGA (Field-Programmable Gate Array) module. The method of claim 10,
The step of calculating the image mean value
Wherein the image module calculates the average value of the image using the cumulative average value, the current pixel value, and the number of pixels of the previous pixels previously stored in the FPGA module. The method of claim 11,
The step of calculating the image mean value
Wherein the FPGA module performs a floating point operation to calculate the image average value. The method of claim 12,
The step of calculating the image mean value
Wherein the floating point operation is performed using a divider module included in the FPGA module. 14. The method of claim 13,
The step of calculating the image mean value
Wherein the FPGA module calculates a difference between a cumulative average value of the previously stored pixels and the current pixel value and inputs the difference value and the number of pixels to the divider module to calculate a quotient and a remaining value, Iris recognition method. 15. The method of claim 14,
The step of calculating the image mean value
Rounding off the remaining value to calculate the intermediate value in addition to the quotient,
And calculating the image average value by subtracting the intermediate value from the cumulative average value of the previously stored previous pixels.

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