KR101954412B1 - A method of manufacturing a semiconductor device with separated merged source/drain structure - Google Patents

Abstract

In a method of forming a semiconductor device including a fin field effect transistor (FinFET), a sacrificial layer is formed over a source / drain structure and an isolation insulating layer of a FinFET structure. A mask pattern is formed on the sacrificial layer. The sacrificial layer and the source / drain structure are patterned by using a mask pattern as an etch mask, thereby forming an opening adjacent the patterned sacrificial layer and the source / drain structure. A dielectric layer is formed in the opening. After the dielectric layer is formed, the patterned sacrificial layer is removed to form a contact opening over the patterned source / drain structure. A conductive layer is formed in the contact opening.

Description

TECHNICAL FIELD [0001] The present invention relates to a method of manufacturing a semiconductor device having a separately coupled source / drain structure,

This application claims priority to U.S. Provisional Patent Application No. 62 / 427,432, filed November 29, 2016, the entire disclosure of which is incorporated herein by reference.

The present disclosure relates to a method of manufacturing a semiconductor integrated circuit, and more particularly to a method of manufacturing a semiconductor device including a fin field effect transistor (FinFET) and a semiconductor device.

As the semiconductor industry evolves into nanometer technology processes seeking higher device density, higher performance and lower cost, it is possible to use a fin field effect transistor (FinFET) and a high-k (dielectric constant) There has been a challenge from both manufacturing and design issues in the development of a three-dimensional design, such as the use of metal gate structures that have been fabricated.

The aspects of the disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. According to standard practice in industry, it is noted that various features are not drawn to scale. In fact, the dimensions of the various features may optionally increase or decrease for clarity of discussion.
1A-1C illustrate one of various stages of a semiconductor device fabrication process according to some embodiments of the present disclosure.
Figures 2A-2C illustrate one of various stages of a semiconductor device manufacturing process according to some embodiments of the present disclosure.
Figures 3A-3C illustrate one of various stages of a semiconductor device manufacturing process according to some embodiments of the present disclosure.
4A-4C illustrate one of various stages of a semiconductor device fabrication process according to some embodiments of the present disclosure.
Figures 5A-5C illustrate one of various stages of a semiconductor device manufacturing process in accordance with some embodiments of the present disclosure.
6A-6C illustrate one of various stages of a semiconductor device fabrication process according to some embodiments of the present disclosure.
Figures 7A-7C illustrate one of various stages of a semiconductor device manufacturing process in accordance with some embodiments of the present disclosure.
8A-8C illustrate one of various stages of a semiconductor device manufacturing process according to some embodiments of the present disclosure.
Figures 9A-9C illustrate one of various stages of a semiconductor device manufacturing process in accordance with some embodiments of the present disclosure.
Figures 10A-10E illustrate one of various stages of a semiconductor device manufacturing process in accordance with one or more embodiments of the present disclosure.
11A and 11B illustrate one of various stages of a semiconductor device fabrication process according to one or more embodiments of the present disclosure.
12A and 12B illustrate one of various stages of a semiconductor device manufacturing process according to one or more embodiments of the present disclosure.
Figure 13 illustrates one of various stages of a semiconductor device manufacturing process in accordance with one or more embodiments of the present disclosure.
Figure 14 illustrates one of various stages of a semiconductor device manufacturing process in accordance with one or more embodiments of the present disclosure.
15A and 15B illustrate one of various stages of a semiconductor device fabrication process according to one or more embodiments of the present disclosure.
16A and 16B illustrate one of various stages of a semiconductor device fabrication process according to one or more embodiments of the present disclosure.
17A and 17B illustrate one of various stages of a semiconductor device manufacturing process according to one or more embodiments of the present disclosure.
Figure 18 illustrates one of various stages of a semiconductor device manufacturing process in accordance with one or more embodiments of the present disclosure.
19 illustrates one of various stages of a semiconductor device manufacturing process in accordance with one or more embodiments of the present disclosure.
Figure 20 illustrates one of various stages of a semiconductor device manufacturing process in accordance with one or more embodiments of the present disclosure.
Figures 21A-21D illustrate one of various stages of a semiconductor device manufacturing process in accordance with one or more embodiments of the present disclosure.
Figures 22A and 22B illustrate exemplary cross-sectional views of a semiconductor device according to some embodiments of the present disclosure.
Figure 23 illustrates one of various stages of a semiconductor device manufacturing process in accordance with one or more embodiments of the present disclosure.
24 illustrates one of various stages of a semiconductor device fabrication process in accordance with one or more embodiments of the present disclosure.
Figure 25 illustrates one of various stages of a semiconductor device manufacturing process in accordance with one or more embodiments of the present disclosure.
Figure 26 illustrates one of various stages of a semiconductor device fabrication process in accordance with one or more embodiments of the present disclosure.
Figure 27 illustrates one of various stages of a semiconductor device fabrication process in accordance with one or more embodiments of the present disclosure.
Figure 28 illustrates one of various stages of a semiconductor device fabrication process in accordance with one or more embodiments of the present disclosure.

It will be understood that the following disclosure provides many different embodiments or examples for implementing different features of the present invention. Specific embodiments or examples of components and devices are described below to simplify the present disclosure. This is, of course, merely illustrative and not limiting. For example, the dimensions of an element are not limited to the ranges or values disclosed, but may depend on the process conditions and / or desired attributes of the device. Moreover, formation of the first feature on the second feature in the following description or formation of the first feature on the second feature may include embodiments in which the first and second features are formed in direct contact, and the first and second features And may include embodiments in which additional features may be formed to insert the first and second features so as not to be in direct contact. The various features may be optionally selectively drawn at different scales for simplicity and clarity. In the accompanying drawings, some layers / features may be omitted for simplicity.

Also, spatially related terms such as "beneath", "below", "lower", "above", "upper" May be used herein for convenience of explanation to illustrate the relationship of an element or feature to an element or feature. Spatially related terms are intended to encompass different orientations of the device in use or operation in addition to the orientation shown in the figures. The devices may be otherwise oriented (rotated 90 degrees or in other orientations) and the spatially related descriptors used herein may be similarly interpreted accordingly. In addition, the term "made of" may mean "comprising" or "consisting of". Also, in the following manufacturing process, there may be one or more additional operations between the described / described operations, and the order of the operations may be changed.

The disclosed embodiments relate to a method of forming a source / drain (S / D) structure for a FinFET, which includes isolating or isolating the S / D structure. Embodiments such as those described herein are generally applicable not only to FinFETs but also to other devices such as double-gate, surround-gate, omega-gate, or gate- gate-all-around transistor, a two-dimensional FET and / or a nanowire transistor or a source / drain epitaxial growth process.

1A-9C illustrate various processes in a semiconductor device fabrication process according to some embodiments of the present disclosure. In various views and exemplary embodiments, like reference numerals are used to indicate like elements. In Figures 1A-9C, a " a " drawing (e.g., Figures 1A, 2a, etc.) shows a perspective view, and a "b" (For example, Figs. 1C, 2C, and the like) shows a cross-sectional view along the Y direction corresponding to the line Y1-Y1 along the X direction corresponding to the line X1- Fig. It is understood that additional operations may be provided before, during and after the process illustrated by Figures 1A-9C, and some of the operations described below may be replaced or eliminated for further embodiments of the method . The order of operations / processes may be interchangeable.

Referring first to Figs. 1A-1C, Figs. 1A-1C illustrate structures after various fabrication operations have been performed to form a FinFET structure. 1A-1C, a source / drain structure 120 and a metal gate 130 are formed on the substrate 101 together with a gate dielectric layer 131. The source / This structure can be formed by the following manufacturing operation.

1A-1C, a substrate 101 having one or more pin structures is shown, and one pin structure 102 is shown. Although one pin structure is shown for illustrative purposes, it is understood that other embodiments may include any number of pin structures. In some embodiments, at least one dummy fin structure is formed adjacent to the fin structure of the active FinFET. The pin structure 102 extends in the X direction and protrudes from the substrate in the Z direction, while the gate 130 extends in the Y direction.

The substrate 101 may include various doping zones depending on design requirements (e.g., p-type substrate or n-type substrate). In some embodiments, the doping region may be doped with a p-type or n-type dopant. For example, the doping zone may be a p-type dopant such as boron or BF ₂ ; N-type dopants such as phosphorus or arsenic; And / or combinations thereof. The doping region may be configured for an n-type FinFET or alternatively it may be configured for a p-type FinFET.

In some embodiments, the substrate 101 may comprise suitable element semiconductors such as silicon, diamond or germanium; III-V compound semiconductors (for example, gallium arsenide (GaAs), silicon carbide (SiC), silicon germanium carbide (SiGeC), GeSn, SiSn, SiGeSn) A suitable alloy or compound semiconductor such as indium gallium arsenide (InGaAs), indium arsenide (InAs), indium phosphide (InP), indium antimonide (InSb), gallium arsenide phosphide (GaAsP) or gallium indium phosphide (GaInP) . The substrate 101 may also include an epitaxial layer (epi-layer) that may be strained for enhanced performance and / or a silicon-on-insulator RTI ID = 0.0 > SOI) < / RTI >

The pin structure 102 may be formed using a patterning process to form a trench such that, for example, the pin structure 102 is formed between adjacent pin structures. As will be discussed in more detail below, the fin structure 102 will be used to form a FinFET.

An isolation region, such as a shallow trench isolation (STI) 105, is disposed in the trench above the substrate 101. One or more liner layers are formed on the sidewalls of the bottom portion 103 of the substrate 101 and the fin structure 102 in some embodiments prior to forming the isolation layer 105. [ In some embodiments, the liner layer comprises a first pin liner layer 106 formed on the sidewalls of the substrate 101 and the bottom portion 103 of the fin structure 102, and a second pin liner layer 106 formed on the first pin liner layer 106 And a second fin liner layer 108 formed thereon. Each of the liner layers has a thickness between about 1 nm and about 20 nm in some embodiments.

In some embodiments, the first fin liner layer 106 comprises silicon oxide and has a thickness between about 0.5 nm and about 5 nm, the second fin liner layer 108 comprises silicon nitride, And has a thickness of about 5 nm. Although any acceptable process may be utilized, the liner layer may be formed of one or more materials such as physical vapor deposition (PVD), chemical vapor deposition (CVD), or atomic layer deposition (ALD) ≪ / RTI > process.

The isolation layer 105 may be formed of a low-k dielectric such as silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), carbon doped oxide, For example, extreme low-k dielectrics, such as porous carbon doped silicon dioxide, polymers such as polyimide, combinations thereof, and the like. In some embodiments, an isolation insulating layer (not shown) may be formed through a process such as CVD, flowable CVD (FCVD), or spin-on-glass process, 105 are formed. Subsequently, a portion of the isolating insulating layer 105 that extends over the top surface of the fin structure 102 and a portion of the liner layer on top of the fin structure 102 are removed by, for example, an etching process, a chemical mechanical polishing : CMP).

In some embodiments, the isolation dielectric layer 105 and the liner layer are recessed to expose the top portion 104 of the fin structure 102 as shown in Figs. 1A-1C. In some embodiments, the isolation dielectric layer 105 and the liner layer are recessed using a single etch process or multiple etch processes. In some embodiments in which the isolated insulating layer 105 is made of silicon oxide, the etching process may be, for example, dry etch, chemical etch, or wet cleaning process. For example, chemical etching may use fluorine-containing chemicals such as dilute hydrofluoric acid (dHF). After the fin forming process, in some embodiments, the fin height (H _fin ) is about 30 nm or more, such as about 50 nm or more. In one embodiment, the pin height is between about 40 nm and about 80 nm. It is understood that the pin height can be modified by subsequent processing. Other materials, processes and dimensions may be used.

After the fin structure 102 is formed, a dummy gate structure including a dummy gate dielectric layer and a dummy gate electrode is formed on the exposed pin structure 102 . A dummy gate dielectric layer and a dummy gate electrode will subsequently be used to define and form the source / drain regions. In some embodiments, a dummy gate dielectric layer and a dummy gate electrode are formed by depositing and patterning a dummy dielectric layer formed over the exposed pin structure 102 and a dummy electrode layer over the dummy gate dielectric layer. The dummy dielectric layer may be formed by thermal oxidation, CVD, sputtering, or any other method known and used in the art to form the dummy dielectric layer. In some embodiments, the dummy dielectric layer comprises at least one suitable dielectric material such as silicon oxide, silicon nitride, SiCN, SiON, and SiN, a low-k dielectric such as a carbon doped oxide, an extreme low-k dielectric such as porous carbon doped silicon dioxide A dielectric, a polymer such as polyimide, or the like, or a combination thereof. In one embodiment, the SiO ₂ is used.

Subsequently, a dummy electrode layer is formed on the dummy dielectric layer. In some embodiments, the dummy electrode layer is a conductive material and is made of a material selected from the group consisting of amorphous silicon, poly silicon, amorphous germanium, poly germanium, amorphous silicon-germanium, Polysilicon-germanium, metal nitride, metal silicide, metal oxide, and metal. The dummy electrode layer may be deposited by PVD, CVD, sputter deposition, or other techniques known and used in the art for depositing conductive materials. Other conductive and non-conductive materials may be used. In one embodiment, poly-Si is used.

A mask pattern may be formed on the dummy electrode layer to assist in patterning. The mask pattern is made of at least one layer of SiO ₂ , SiCN, SiON, Al ₂ O ₃ , SiN or other suitable material. By using the mask pattern as an etching mask, the dummy electrode layer is patterned into the dummy gate electrode. In some embodiments, a dummy dielectric layer is also patterned to define a dummy gate dielectric layer.

Subsequently, a sidewall spacer 132 is formed along the sidewalls of the dummy gate structure. The sidewall spacers 132 may be formed by depositing and anisotropically etching an insulating layer deposited over the dummy gate structure, the pin structure 102, and the isolation dielectric layer 105. In some embodiments, the sidewall spacers 132 are formed of silicon nitride and may have a single-layer structure. In an alternate embodiment, the sidewall spacers 132 may have a composite structure comprising a plurality of layers. For example, the sidewall spacers 132 may comprise a silicon oxide layer and a silicon nitride layer over the silicon oxide layer. The other material, other low-k material, or a combination thereof, such as _{SiO 2, SiCN, SiON, SiN} , SiOCN , may also be used. The thickness of the sidewall spacers 132 ranges from about 5 nm to about 40 nm in some embodiments.

After the dummy gate structure and sidewall spacers are formed, a source / drain (S / D) structure 120 is formed on the exposed portion 104 of the fin structure 120 along the opposite side of the dummy gate structure. The S / D structure 120 may be formed epitaxially on the side and top surface of the exposed pin structure 104. In some embodiments, the pin structure 104 may be recessed and the S / D structure is formed epitaxially on the exposed portion of the recessed pin. The use of epitaxially grown material in the source / drain regions allows the source / drain regions to exert pressure on the channel of the FinFET.

The material used for the S / D structure 120 is that one type of material is used to impose tensile stress in the channel region of the n-type FinFET and a compressive stress is applied to the p- Type < / RTI > and p-type FinFETs so that other types of materials can be used for the < RTI ID = For example, SiP or SiC may be used to form an n-type FinFET, and SiGe or Ge may be used to form a p-type FinFET. Other materials may be used. In some embodiments, the S / D structure 120 includes two or more epitaxial layers having different compositions and / or different dopant concentrations.

In some embodiments where different materials are utilized for the n-type device and the p-type device, the epitaxial material is formed for another structure (e.g., p-type pin structure) and the process for the other is repeated While one structure (e.g., an n-type pin structure) is masked. The S / D structure 120 can be doped through an implanting process to implant a suitable dopant, or by in-situ doping as the material grows. For example, the channel is Si or Si _1-for the p- channel FET, which may be _x Ge _x, a doped epitaxial film is a boron-doped Si _1-y Ge _y can be a, where y is enhanced hole mobility ( is greater than or equal to x to induce longitudinal compressive strain in the channel for hole mobility enhancement. For an n-channel FET in which the channel may be Si, the doped epitaxial film may be formed of, for example, phosphorus-doped silicon (Si: P) or silicon-carbon (Si _{1 - z} C _z : Lt; / RTI > In the case where the channel is a compound semiconductor such as In _m Ga _{1 - m} As, the doping epitaxial film may be, for example, In _n Ga _{1 - n} As, where n is equal to or less than m.

As shown in FIGS. 1A and 1B, the S / D structure 120 extends in the Y direction, which has a wider width than the pin structure 104. In some embodiments, the cross section of the S / D structure 120 in the Y direction has a substantially hexagonal shape, and in another embodiment, the cross section of the S / D structure 120 is diamond shaped, (pillar shape) or a bar shape (bar shape). In some embodiments, the width (W _SD ) of the S / D structure in the Y direction is in the range of about 25 nm to about 100 nm.

After the S / D structure 120 is formed, a first insulating layer 122 is deposited as a liner layer to cover the S / D structure 120 and the sidewall spacers 132 of the dummy gate structure. The first insulating layer 122 acts as an etch stop during patterning of the subsequently formed dielectric material. In some embodiments, the first insulating layer 122 includes SiO _2, SiCN, SiON, SiN, and other suitable dielectric material. In one embodiment, SiN is used. The first insulating layer 122 may be made of a plurality of layers comprising a combination of the above-mentioned materials. Although any acceptable process may be utilized, the first insulating layer 122 may be deposited via one or more processes such as PVD, CVD, or ALD. Other materials and / or processes may be used. In some embodiments, the first insulating layer 122 has a thickness between about 0.5 nm and about 5 nm. Other thicknesses may be used in other embodiments.

After the first insulating layer 122 is formed, a first sacrificial layer 115 is formed on the first insulating layer 122. In some embodiments, the first sacrificial layer comprises a dielectric material, or at least one layer of another suitable dielectric material such as _{SiO 2, SiCN, SiON, SiOC} , SiOH, SiN. In some embodiments, although any acceptable process may be utilized, it is formed through a film-forming process such as CVD, PVD, ALD, FCVD or a spin-on-glass process. Subsequently, a portion of the first insulating layer 122 is removed, for example, using an etch process, CMP, etc., on the exposed upper surface of the dummy gate electrode.

Subsequently, the dummy gate electrode and the dummy gate dielectric layer are removed. The removal process may include one or more etch processes. For example, in some embodiments, the removal process includes selectively etching using dry or wet etching. When dry etching is used, the process gas may include CF ₄ , CHF ₃ , NF ₃ , SF ₆ , Br ₂ , HBr, Cl _2, or combinations thereof. A diluting gas such as N ₂ , O ₂ or Ar may optionally be used. When wet etching is used, an etching solution (etchant) can be applied to the surface of the substrate, such as NH ₄ OH: H ₂ O ₂ : H ₂ O (APM), NH ₂ OH, KOH, HNO ₃ : NH ₄ F: H ₂ O and / or the like. The dummy gate dielectric layer may be removed using a wet etch process, such as dilute HF acid, and used. Other processes and materials may be used.

After the dummy gate structure is removed, a gate dielectric layer 131 is formed over the channel region of the fin structure 104. In some embodiments, the gate dielectric layer 131 includes one or more high-k dielectric layers (e.g., having a dielectric constant greater than 3.9). For example, the one or more gate dielectric layers may comprise at least one layer of Hf, Al, Zr, a combination of the metal oxides or silicides thereof, and a multi-layer thereof. Other suitable materials include La, Mg, Ba, Ti, Pb, Zr in the form of metal oxides, metal alloy oxides and combinations thereof. Exemplary materials include MgO _x , BaTi _x O _y , BaSr _x Ti _y O _z , PbTi _x O _y , PbZr _x Ti _y O _z , SiCN, SiON, SiN, Al ₂ O ₃ , La ₂ O ₃ , Ta ₂ O ₃ , Y ₂ O ₃ , HfO ₂ , ZrO ₂ , HfSiON, YGe _x O _y , YSi _x O _y, and LaAlO ₃ . Methods of forming the gate dielectric layer 131 include molecular-beam deposition (MBD), ALD, PVD, and the like. In some embodiments, the gate dielectric layer 131 has a thickness of about 0.5 nm to about 5 nm. In some embodiments, a gate dielectric layer 131 is also formed on the side of the sidewall spacers 132.

In some embodiments, an interfacial layer (not shown) may be formed over the channel region 104 prior to forming the gate dielectric layer 131, and a gate dielectric layer 131 is formed over the interface layer . The interfacial layer aids in buffering the subsequently formed high-k dielectric layer from the underlying semiconductor material. In some embodiments, the interface layer is a chemical silicon oxide that can be formed by a chemical reaction. For example, chemical silicon oxides can be formed using deionized water + ozone (DIO ₃ ), NH ₄ OH + H ₂ O ₂ + H ₂ O (APM), or other methods. Other embodiments may utilize different materials or processes for the interfacial layer. In one embodiment, the interface layer has a thickness from about 0.2 nm to about 1 nm.

After the gate dielectric layer 131 is formed, a gate electrode 130 is formed over the gate dielectric layer 131. The gate electrode 130 may be a metal selected from the group of W, Cu, Ti, Ag, Al, TiAl, TiAlN, TaC, TaCN, TaSiN, Mn, Co, Pd, Ni, Re, Ir, Ru, have. In some embodiments, the gate electrode 130 comprises a metal selected from the group of TiN, WN, TaN, and Ru. Metal alloys such as Ti-Al, Ru-Ta, Ru-Zr, Pt-Ti, Co-Ni and Ni-Ta may be used and / or WN _x , TiN _x , MoN _x , TaN _x and TaSi _x N _y May be used. In some embodiments, the gate electrode 130 has a thickness in the range of about 5 nm to about 100 nm. The gate electrode 130 may be formed using a suitable process such as ALD, CVD, PVD, plating, or a combination thereof. A planarization process such as CMP may be performed to remove the excess material.

In certain embodiments of the disclosure, the gate electrode 130 includes one or more work function adjustment layers (not shown) disposed on the gate dielectric layer 131. The work function adjustment layer is made of a single layer of TiN, TaN, TaAlC, TiC, TaC, Co, Al, TiAl, HfTi, TiSi, TaSi or TiAlC or a conductive material such as multiple layers of two or more of these materials. At least one of TaN, TaAlC, TiN, TiC, Co, TiAl, HfTi, TiSi and TaSi is used as the work function adjustment layer for the n-channel FinFET and TiAlC, Al, TiAl, TaN, At least one of TaAlC, TiN, TiC and Co is used as a work function adjusting layer.

Thereafter, the gate electrode 130, the gate dielectric layer 131, and the work function adjustment layer are recessed, and a gate cap layer 134 is formed on the recessed gate electrode 130. [ In some embodiments, when the gate electrode 130 is mainly made of W, the gate electrode may be formed, for example, in a temperature range of 24 占 폚 to 150 占 폚, and at a pressure of less than 1 Torr, Cl ₂ / O ₂ / BCl ₃ May be recessed using a dry etch process.

After recessing the gate electrode 130, a gate cap layer 134 is formed in the recess to protect the gate electrode 130 during a subsequent process. In some embodiments, the gate cap layer 134 includes _{SiO 2, SiCN, SiON, SiN} , Al 2 O 3, La 2 O 3, SiN, combinations thereof, etc., but may be another suitable dielectric film. The gate cap layer 134 may be formed using, for example, CVD, PVD, spin-on, or the like. Other suitable process steps may be used. A planarization process such as CMP may be performed to remove the excess material.

Figures 2A-2C illustrate an exemplary view of one of the various stages for fabricating a FinFET device according to some embodiments of the present disclosure.

As shown in Figs. 2A-2C, the first sacrificial layer 115 is at least partially removed from both side regions of the S / D structure 120 to form the opening 116. In some embodiments, all of the first sacrificial layer 115 is removed. The first sacrificial layer 115 may be removed by a suitable etching operation such as dry etching and / or wet etching. The etching operation substantially stops at the first insulating layer 122. [ In some embodiments, the first insulating layer 122 has a thickness between about 0.5 nm and about 10 nm.

Figures 3A-3C illustrate an exemplary view of one of the various stages for fabricating a FinFET device in accordance with some embodiments of the present disclosure.

After the opening 116 is formed, a second sacrificial layer 140 is formed in the opening 116. The second sacrificial layer 140 is made of a material having a higher (e.g., 5 or more) etch selectivity with respect to the material of the first insulating layer 122 and / or the isolation insulating layer 105. In some embodiments, the second sacrificial layer 140 may be a crystalline, polycrystalline, or amorphous material and may be Si, SiGe, SiC, Ge (which may be doped or un- , SiGeC, and GeSn. ≪ / RTI > In another embodiment, the second sacrificial layer 140 is made of SiOC, SiC, SiON, SiCN, SiOCN, SiN and / or at least one silicon-based dielectric layer of SiO _2. Aluminum-based dielectric materials such as aluminum oxide, aluminum oxy-carbide and aluminum oxynitride may be used. SOC (spin-on-carbon) can also be used. In a particular embodiment, the second sacrificial layer 140 may comprise one or more of III-V compound semiconductors, including but not limited to GaAs, GaN, InGaAs, InAs, InP, InSb, InAsSb, AlN and / Layer. Although any acceptable process may be utilized, the second sacrificial layer 140 may be deposited via one or more processes such as PVD, CVD, or ALD. Other materials and / or processes may be used. In one embodiment, Si is used as the second sacrificial layer.

A planarization operation, such as an etch-back process or CMP, may be performed to planarize the top surface of the second sacrificial layer 140. By the planarization operation, the upper surface of the gate cap layer 134 is exposed. The height H _sacr of the second sacrificial layer measured from the surface of the first insulating layer 122 on the isolated insulating layer 105 is in a range of about 100 nm to about 350 nm in some embodiments.

Figures 4A-4C illustrate an exemplary view of one of the various stages for fabricating a FinFET device in accordance with some embodiments of the present disclosure.

After the second sacrificial layer 140 is formed, the mask pattern 142 is formed on the second sacrificial layer 140. The mask pattern 142 may be formed by patterning a layer of suitable mask material using a photo-etching operation. The mask pattern 142 extends in the X direction and has a width (W _hm ) in the Y direction in the range of about 5 nm to about 100 nm in some embodiments, and in a range of about 10 nm to about 40 nm in other embodiments, . The width W _hm may be a different value depending on the design rules and / or the type of semiconductor device.

A mask pattern 142 is made of one or more layers of dielectric material such as SiO _2, SiN and / or SiON and / or TiN. Although any acceptable process may be utilized, the material for the mask pattern 142 may be deposited through one or more processes such as PVD, CVD, or ALD. Other materials and / or processes may be used.

The second sacrificial layer 140, the first insulating layer 122 and the S / D structure 120 are anisotropically etched by using the mask pattern 142 as an etching mask to form the patterned second sacrificial layer 140, And an opening 144 adjacent to the S / D structure 120. The etching operation may include a plurality of etching processes using different plasma gases.

When a Si-based material (e.g., poly-Si or amorphous Si) is used as the second sacrificial layer 140, the etching may be performed by, for example, a gas containing HBr or a gas containing Cl ₂ and SF ₆ For example, by plasma dry etching. When SOC (spin-on-carbon) is used as the second sacrificial layer 140, for example, a gas containing N ₂ and H ₂ or a gas containing SO ₂ and O ₂ is used for plasma dry etching Etching can be performed. When a Si oxide based material formed by FCVD is used as the second sacrificial layer 140, it can be performed by plasma dry etching using a gas including, for example, fluorocarbon and / or fluorine have. When a Ge based material (e. G., Ge or SiGe) is used as the second sacrificial layer 140, it can be etched by plasma dry etching using, for example, a gas comprising fluorocarbon or a gas containing halogen Can be performed. During the etching, the substrate may be heated at a temperature between about 20 [deg.] C and about 200 [deg.] C.

This etching operation removes at least a lateral portion of the S / D structure 120 such that the etched side of the S / D structure 120 is substantially parallel to the side of the upper fin structure 104. The amount of etching of one side portion of the S / D structure 120 (which is substantially equal to half the difference between W _{SD shown} in FIG. 1B and W _hm shown in FIG. 3B) is about 5 nm to about 5 nm in some embodiments 40 nm. After patterning (etching) of the S / D structure 120, when the both side portions are etched, the width of the S / D structure 120 patterned in the Y direction is in the range of about 10 nm to about 40 nm.

4A and 4B, only one side portion of the S / D structure 120 is etched by using mask patterns 142 having different shapes in both side portions of the S / D structure 120, Is etched.

The gate cap layer 134 is not substantially etched during the patterning of the second sacrificial layer 140 and the source / drain structure 120, as shown in FIG. 4A. In other words, the material for the mask pattern 142 has a high etch selectivity (e.g., 5 or more) with respect to the gate cap layer 134.

Figures 5A-5C illustrate an exemplary view of one of the various stages for fabricating FinFET devices in accordance with some embodiments of the present disclosure.

The mask pattern 142 is removed by using a suitable etch and / or planarization operation such as CMP. In some embodiments, the height ( _Etch ) of the second sacrificial layer 140 from the surface of the isolation dielectric layer 105 ranges from about 80 nm to about 250 nm after the mask pattern 142 is removed.

Figures 6A-6C illustrate an exemplary view of one of the various stages for fabricating a FinFET device in accordance with some embodiments of the present disclosure.

After the mask pattern 142 is removed, a second insulating layer 146 is formed over the patterned second sacrificial layer 140 and the patterned S / D structure 120. 6A, a second insulating layer 146 is also formed on the sidewall spacers 132 and the gate cap layer 134. As shown in FIG.

In some embodiments, the second insulating layer 146 may include _{SiO 2, SiCN, SiON, SiCN} , SiOCN and SiN, however, other suitable dielectric materials can be used. In one embodiment, a silicon nitride based material such as SiN is used. The second insulating layer 146 may be made of a plurality of layers including a combination of the above-mentioned materials. Although any acceptable process may be utilized, the second insulating layer 146 may be deposited through one or more processes such as PVD, CVD, or ALD. Other materials and / or processes may be used. In some embodiments, the second insulating layer 146 has a thickness between about 1 nm and about 10 nm. Other thicknesses are used in other embodiments.

In some embodiments, as illustrated in Figures 6a and 6b, the patterned before the formation of the S / D structure and then to reduce the R _c between the formed contact metal (contact metal), the second insulating layer 146 A silicide layer 126 is formed on the S / D structure 120. The metal suicide formation process may form a metal suicide on the side portion of the S / D structure. The metal suicide formation process includes depositing a metal film on the S / D structure 120, thermal treatment to form a metal suicide at the interface or surface of the S / D structure 120, and excess unreacted metal ). ≪ / RTI > The metal silicide includes TiSi _x , NiSi _x , CoSi _x , NiCoSi _x and TaSi _x , but other suitable silicide materials may be used. In some embodiments, the silicide layer 126 has a thickness between about 0.5 nm and about 10 nm. In another embodiment, the silicide layer is not formed in the stage of such a manufacturing operation, but can be formed in a later manufacturing stage.

Figures 7A-7C illustrate an exemplary view of one of the various stages for fabricating a FinFET device in accordance with some embodiments of the present disclosure.

After the second insulating layer 146 is formed, a first interlayer dielectric (ILD) 145 is formed on the second sacrificial layer 140 and the S / D structure 120, filling the openings 144 .

The ILD layer 145 may comprise a single layer or multiple layers. In some embodiments, ILD layer 145 includes _{SiO 2, SiCN, SiOC, SiON} , SiOCN, SiN or low -k material, but the film can be used other suitable dielectric. The ILD layer 145 may be formed by CVD, PECVD or ALD, FCVD, or spin-on-glass processes. A planarization process such as a CMP process can be performed to remove excess material. By the planarization process, the upper surface of the second sacrificial layer 140 (and the cap insulating layer 134) is exposed in some embodiments.

When FCVD is used, in some embodiments a curing process is performed on a flowable dielectric dielectric precursor. The curing process includes UV curing, ozone (O ₃ ) plasma curing, or low temperature O ₃ plasma + UV curing (LTB + UV curing) to transfer the flowable dielectric dielectric precursor into a dielectric layer such as a silicon oxide layer can do. The processing temperature range of the UV curing process is in some embodiments between about 0 캜 and about 10 캜. The processing temperature range of the O ₃ plasma curing process is between about 100 ° C and about 250 ° C in some embodiments. The processing temperature range of the LTB + UV curing process is between about 30 [deg.] C and about 50 [deg.] C in some embodiments. In some embodiments, the curing process may be performed only once after the deposition process to save (but not limit) the process time. The deposition process and the curing process can be performed alternately. In another embodiment, the flowable isolating dielectric precursor may also be directly transferred into the dielectric layer through an oxidation process by direct introduction of nitrogen, oxygen, ozone, or steam.

To further increase the structural density of the ILD layer, after the curing process, a thermal treatment process may be performed on the isolation dielectric layer. The heat treatment process includes a steam containing thermal treatment process (wet annealing) and a nitrogen-containing thermal treatment process (dry annealing) . The processing temperature range of the steam-containing heat treatment is in some embodiments between about 400 ° C and about 1000 ° C, and the processing temperature of the nitrogen-containing heat treatment process is between about 1000 ° C and about 1200 ° C. In another embodiment, the temperature of the heat treatment may be reduced to about 400 占 폚 by exposing the film to ultra-violet radiation, for example, an ultra violet thermal processing (UVTP) process.

After curing or processing, the ILD layer may have a relative permittivity of less than 6 in some embodiments.

In another embodiment, a spin on dielectric (SOD) process is performed to form the ILD layer 145. In this embodiment, a nitride-containing liner layer is formed in a pre-process to provide an inter layer suitable for the deposited isolated dielectric layer in the contact isolation region by the SOD process. Thus, the ILD layer can be formed by an SOD process using suitable precursors.

In an SOD process for ILD layer 145, the precursor may be selected from the group consisting of siloxane, methylsiloxane, polysilazane and hydrogensilsesquioxane, perhydro polysilazane, PHPS), and other suitable materials. ≪ RTI ID = 0.0 > [0031] < / RTI > SOD precursors are soluble in compatible organic solvents commonly used in coating solutions of spin-on chemicals. Suitable organic solvents include, for example, dibutyl ether (DBE), toluene, xylene, propyleneglycol monomethyletheracetate (PGMEA), ethyl lactate, Isopropyl alcohol (IPA), and the like, and preferably xylene is used as a solvent for PHPS. The concentration of the SOD precursor in the solution may be varied to adjust the concentration of the solution (i.e., viscosity) and the thickness of the coating. In some embodiments, a solution containing from about 4% to about 30% of the SOD precursor weight may be used. In another embodiment, a solution containing from about 8% to about 20% of the SOD precursor weight is used. Additional minor amounts of additives such as surfactants and binders may be included in the solution.

The wafer is spinned to uniformly diffuse the SOD precursor from the center of the wafer to the edge during the precursor spin-on process. In some embodiments, the spin rate of the cast rotation for coating the SOD precursor on the substrate for a 12 inch wafer is from 100 rpm to 3000 rpm. In some embodiments, the dynamic dispense rate of the SOD precursor is near 1 ml / sec and the dispense puddle will fully diffuse to the edge of the wafer before the main speed. The SOD precursor can thus cover the bottom of the contact isolation hole collectively and fill the opening 144.

Subsequently, a prebaking process is performed after SOD deposition to stabilize the SOD layer. In some embodiments, the pre-baking process is performed at ambient temperatures in the range of about 100 ° C to about 200 ° C. A heat treatment process is performed after the prebaking process to densify the SOD layer. In some embodiments, the heat treatment process is an annealing process performed at a high temperature ranging from about 400 [deg.] C to about 1100 [deg.] C. The annealing process may be a wet annealing process using a vapor containing gas, O ₂ and H ₂ gas, or a dry annealing process using a gas comprising N ₂ and O ₂ gas. In another embodiment, the heat treatment process uses a plasma at a lower temperature in the range of about 150 캜 to about 400 캜. The partial pressure ratio of water vapor (H ₂ O) to hydrogen (H ₂ ) is preferably controlled to a value in the range of about 1 × 10 ^-11 to about 1.55.

8A-8C illustrate an exemplary view of one of the various stages for fabricating a FinFET device according to some embodiments of the present disclosure.

Subsequently, the contact opening 148 is formed by removing the first insulating layer 122 remaining on top of the S / D structure 120, after the second sacrificial layer 140 is removed. 8A-8C, the contact openings 148 are defined by the second insulating layer 146 and the sidewall spacers 132. As shown in FIG. The etching operation for removing the second sacrificial layer 140 may be isotropic or anisotropic.

When a Si-based material (e.g., poly-Si or amorphous Si) is used as the second sacrificial layer 140, a plasma dry etch using a gas comprising Cl ₂ and NF ₃ or a gas comprising F ₂ plasma dry etching or wet etching using NH ₄ OH and / or tetramethylammonium (TMAH). When SOC (spin-on-carbon) is used as the second sacrificial layer 140, for example, a gas containing N ₂ and H ₂ or a gas containing SO ₂ and O ₂ is used for plasma dry etching ≪ / RTI > When a Si oxide based material formed by FCVD is used as the second sacrificial layer 140, etching may be performed by wet etching using, for example, HF or BHF. When a Ge based material (e.g., Ge or SiGe) is used as the second sacrificial layer 140, for example, a plasma dry etching using ozone or a solution containing NH ₄ OH and H ₂ O ₂ , or a solution containing HCl And H ₂ O _{2. The} etching may be carried out by wet etching using a solution containing H ₂ O ₂ . The remaining first insulating layer 122 may be removed by using a suitable etching operation.

9A-9C illustrate an exemplary view of one of the various stages for fabricating a FinFET device according to some embodiments of the present disclosure.

After the second sacrificial layer 140 and the remaining first insulating layer 122 are removed an additional suicide layer 127 is formed on the exposed top of the S / D structure 120. When the silicide layer 126 is not formed, only the uppermost portion of the S / D structure 120 (at the bottom of the contact opening 148 defined by the second insulating layer 146 and the sidewall spacers 132) . The silicide layer 127 may be formed by a metal silicide formation process similar to the formation of the silicide layer 126. [ In some embodiments, silicide layer 127 has a thickness between about 0.5 nm and about 10 nm.

Subsequently, the contact portion 150 is formed in the contact opening 148 to contact the silicide layer 127 formed on top of the S / D structure 120.

Contact 150 may comprise a single layer or multi-layer structure. For example, in some embodiments, the contacts 150 may include a contact liner layer, such as a diffusion barrier layer, an adhesion layer, and the like, and a contact liner layer, . The contact liner layer may include Ti, TiN, Ta, TaN, etc. formed by ALD, CVD or the like. The contact body may be formed by depositing a conductive material such as one or more layers of Ni, Ta, TaN, W, Co, Ti, TiN, Al, Cu, Au, . A planarization process such as CMP may be performed to remove excess material from the surface of the ILD layer 145.

The height H _g of the gate structure including the gate cap layer 134 measured from the top of the fin structure 104 is in the range of about 20 nm to 100 nm after the contact portion 150 is formed, ) height (H _mg) of the metal gate (130) measured from the top of the is in the range of from about 10 nm to about 60 nm in some embodiments.

After the contacts 150 are formed, additional CMOS processes are performed to form various features, such as additional inter-level dielectric layers, contact / via, interconnect metal and passivation layers, .

Figures 10A-21D illustrate various processes in a semiconductor device manufacturing process according to another embodiment of the present disclosure. Additional operations may be provided before, during and after the process illustrated by Figures 10A-21D, and some of the operations described below may be replaced or removed for further embodiments of the method. The order of operations / processes may be interchangeable. Materials, configurations, dimensions, and / or processes that are the same as or similar to the above-described embodiments described with reference to Figs. 1A-9C may be used in the following embodiments, and the detailed description thereof may be omitted.

Figures 10A-21D illustrate various processes in a semiconductor device fabrication process for static random access memory (SRAM) cells formed by FinFETs. The source / drain structures 220 and 221 and the metal gate 230 are formed on the substrate 201 together with the gate dielectric layer 231, as shown in Figures 10A-10E. This structure can be formed by the manufacturing operation as described above.

10A shows a top view of an SRAM cell. 10B is a perspective view corresponding to the area AR of FIG. 10A. The cell boundary of one SRAM unit cell is shown by SC. Within one SRAM unit cell, there are two gates 230 and four pin structures 202. A first conductive type S / D structure 220 and a second conductive type S / D structure 221 are formed on the fin structure between the gates. In one embodiment, the first conductivity type is p-type and the second conductivity type is n-type. In another embodiment, the first conductivity type is n-type and the second conductivity type is p-type.

Similar to FIGS. 1A-1C, a fin structure 202 including a bottom portion 203 and an upper portion 204 is disposed on a substrate 201. The bottom portion 203 is embedded in the isolated insulating layer 205 and the top portion 204 protrudes from the isolated insulating layer 205. A gate cap layer 234 is formed on each gate 230 and a gate cap layer 234 and a gate 230 are disposed between the sidewall spacers 232. The first insulating layer 222 covers the S / D structure and the first sacrificial layer 215 is formed on the S / D structure that is covered by the first insulating layer 222 between the gate structures.

Figs. 10C-10E are cross-sectional views corresponding to the lines Y21-Y21, Y22-Y22, and Y23-Y23 in Fig. 10A, respectively. In this stage of manufacturing operation, a portion of the S / D structure is undesirably merged with one or two adjacent S / D structures due to the narrow separation between adjacent pin structures. For example, when the space (S _fin ) between two adjacent pin structures is less than about 100 nm, the layer formed with the epitaxial layer of the adjacent S / D structure tends to be merged.

In the cross section corresponding to the lines Y21-Y21 shown in Fig. 10C, the adjacent second conductive type S / D structure 221, more specifically the epitaxially formed layer, is merged. In the cross section corresponding to the line Y22-Y22 shown in Fig. 10D, the adjacent second conductive type S / D structure 221, more specifically, the epitaxially formed layer is merged and the adjacent first conductive type S / The first conductive type S / D structure 220 and the second conductive type S / D structure are merged. In the cross section corresponding to the line Y23-Y23 shown in FIG. 10E, the adjacent second conductive type S / D structures 221 are merged, the adjacent first conductive type S / D structures 220 are merged, The conductive S / D structure and the second conductive type S / D structure are merged, respectively. Some of the merged S / D structures will be separated by the following operation. In some embodiments, a void 269 is formed below the merging portion of the S / D structure. In other embodiments, one S / D structure is not merged, but is very close to an adjacent S / D structure (e.g., less than about 3 nm) that can cause current leakage due to electrical breakdown . Embodiments of the present disclosure are applicable to S / D structures that are positioned as such.

11A and 11B illustrate an exemplary view of one of the various stages for fabricating a FinFET device according to some embodiments of the present disclosure. Fig. 11A is a perspective view, and Fig. 11B is a cross-sectional view corresponding to the line Y23-Y23 in Figs. 10A and 10B.

Similar to FIGS. 2A-2C, the first sacrificial layer 215 is formed from both side regions of the S / D structures 220 and 221 to form the opening 216 and to expose the first insulating layer 222 At least partially. In some embodiments, all of the first sacrificial layer 215 is removed.

12A and 12B illustrate an exemplary view of one of the various stages for fabricating a FinFET device according to some embodiments of the present disclosure. Fig. 12A is a perspective view, and Fig. 12B is a cross-sectional view corresponding to the line Y23-Y23 in Figs. 10A and 10B.

Similar to FIGS. 3A-3C, after opening 216 is formed, a second sacrificial layer 240 is formed in opening 216.

Figure 13 illustrates an exemplary view of one of the various stages for fabricating a FinFET device in accordance with some embodiments of the present disclosure.

4A-4C, after the second sacrificial layer 240 is formed, a mask pattern 242 is formed on the second sacrificial layer 240 and the gate structure. A portion of the mask pattern 142 over the S / D structure has a width (W _hm ) in the range of about 10 nm to about 40 nm in some embodiments.

By using the mask pattern 242 as an etching mask, the second sacrificial layer 240, the first insulating layer 222, and the S / D structures 220 and 221 are anisotropically etched to form a patterned second sacrificial layer 240 and S / D structures 220 and 221, respectively.

This etching operation removes at least one of the side portions of the S / D structure 220 such that the etched side surfaces of the S / D structures 220 and 221 are substantially parallel to the side surfaces of the upper fin structure 204.

Figure 14 illustrates an exemplary view of one of the various stages for fabricating a FinFET device in accordance with some embodiments of the present disclosure.

Similar to Figs. 5A-5C, the mask pattern 242 is removed by using a suitable etch and / or planarization operation such as CMP.

15A and 15B illustrate an exemplary view of one of the various stages for fabricating a FinFET device according to some embodiments of the present disclosure. Fig. 15A is a perspective view, and Fig. 15B is a cross-sectional view corresponding to the line Y23-Y23 in Figs. 10A and 10B.

6A-6C, after the mask pattern 242 is removed, a second insulating layer 246 is formed over the patterned second sacrificial layer 240 and the patterned S / D structures 220 and 221 . 15A and 15B, a second insulating layer 246 is also formed on the sidewall spacers 232 and the gate cap layer 234. In some embodiments, a silicide layer is not formed on the patterned S / D structure in the stage of such fabrication operations. In another embodiment, a silicide layer is formed on the patterned S / D structure before forming the second insulating layer.

16A and 16B illustrate an exemplary view of one of the various stages for fabricating a FinFET device according to some embodiments of the present disclosure. Fig. 16A is a perspective view, and Fig. 16B is a cross-sectional view corresponding to the line Y23-Y23 in Figs. 10A and 10B.

7A-7C, after the second insulating layer 246 is formed, a first interlayer insulator (ILD) 244 is formed to fill the opening 244 and to cover the second sacrificial layer 240 and the S / D structure. ) Layer 245 is formed. A planarization process, such as a CMP process, is performed to remove the excess material for the ILD layer 245 and a portion of the second insulating layer 246. By the planarization process, the top surface (and the cap insulating layer 234) of the second sacrificial layer 240 is exposed in some embodiments.

Figures 17A and 17B illustrate an exemplary view of one of the various stages for fabricating a FinFET device according to some embodiments of the present disclosure. Fig. 17A is a perspective view, and Fig. 17B is a cross-sectional view corresponding to the line Y23-Y23 in Figs. 10A and 10B.

Similar to Figs. 8A-8C, the second sacrificial layer 240 is removed.

Figure 18 illustrates an exemplary view of one of the various stages for fabricating a FinFET device in accordance with some embodiments of the present disclosure.

Similar to FIGS. 8A-8C, after the second sacrificial layer 240 is removed, the first insulating layer 222 remaining on the top or side of the S / D structure is removed to form contact openings 248 . 18, each of the contact openings 248 is defined by a second insulating layer 246 and a sidewall spacer 232.

19 illustrates an exemplary view of one of the various stages for fabricating a FinFET device according to an embodiment of the present disclosure.

9A-9C, a silicide layer 227 is formed on the exposed top and sides of the S / D structures 220 and 221 after the contact openings 248 are formed.

Figure 20 illustrates an exemplary view of one of the various stages for fabricating a FinFET device in accordance with some embodiments of the present disclosure.

Similar to FIGS. 9A-9C, the contact openings 248 are formed to contact the silicide layer 227 formed on top and sides of the S / D structure.

After forming the contacts 250, additional CMOS processes are performed to form various features such as additional inter-level dielectric layers, contact / via, interconnect metal layers and passive layers.

21A shows a top view of an SRAM cell after the contacts are formed. Figs. 21B to 21D are cross-sectional views corresponding to lines Y21 to Y21, Y22 to Y22, and Y23 to Y23 in Figs. 20 and 21A, respectively. It is noted that FIG. 21A shows only the fin structure 202, the gate 230, and the S / D structures 220 and 221. FIG.

In Figure 21B, only one of the side portions of the epitaxial layer of the first conductive type S / D structure 220 has an etched surface, while both sides of the epitaxial layer of the second conductive type S / Etched surface. Thus, the first conductive type S / D structure 220 has an asymmetrical cross section about the pin structure 204 along the Y direction. In some embodiments, the distance D ₁ between the etched surface and the fin structure 204 on _one side is greater than the distance (D ₂ ) between the non-etched surface (the farthest point from the fin structure) ) To about 70%. In another embodiment, the distance D ₁ is from about 20% to about 50% of the distance D ₂ .

The second conductive type S / D structure 221 has a substantially symmetrical cross section with respect to the pin structure 204 along the Y direction. However, due to process variations such as an overlay error in a photo lithography operation, the second conductive type S / D structure 221 may have a slightly asymmetric cross-section. In such a case, in some embodiments, the distance D ₃ between the etched surface and the fin structure 204 on one side is greater than the distance D ₄ between the etched surface and the fin structure 204 on the other side, % To about 140%. In another embodiment, the distance D ₃ is from about 90% to about 110% of the distance D ₄ .

21C, only one of the side portions of the epitaxial layer of the first conductive type S / D structure 220 has an etched surface, similar to FIG. 21B. The epitaxial layer of the second conductivity type S / D structure 221 is merged on one side while the other side has an etching surface.

21D, this cross section includes a first conductive S / D structure 220 in which only one of the side portions of the epitaxial layer has an etched surface, and the first conductive S / D structure 220 comprises an adjacent second conductive S / / D structure 220 and each of the first conductive S / D structure 220 and the second conductive S / D structure 220 has an etched surface.

It is noted that, as shown in FIGS. 21B-21D, voids 270, 271, and 272 may be formed below the S / D structure.

As described above, the S / D structure shown by Figs. 21B-21D can exist in one semiconductor device, for example, SRAM. The structure shown by Figs. 9A-9C may be included in the same semiconductor device. Furthermore, the same semiconductor device may also include a S / D structure that does not have an etched surface, similar to the structure shown in Figures 10C-10E.

Figures 22A-22B illustrate exemplary cross-sectional views of a semiconductor device according to another embodiment of the present disclosure.

In the above-described embodiment, one or more epitaxial layers are formed on the upper portion of the fin structure 104 or 204 as the S / D structure 120, 220 or 221. 22A, the upper portion of the fin structure 104 or 204 is recessed below or below the top surface of the ILD 205, and then one or more epitaxial layers 320 or 321 At least one epitaxial layer is formed to be formed on the sined pin structure.

22B, the fin structure 104 or 204 is replaced with a stacked layer of a first semiconductor layer 301 and a second semiconductor layer 302 for a gate-all-around FET, Wherein the channel of the FET is a nano-wire of a first semiconductor layer or a second semiconductor layer, each of which is wrapped with a gate dielectric layer and a gate electrode.

23-28 illustrate various stages of a semiconductor device fabrication process according to one or more embodiments of the present disclosure. It is understood that additional operations may be provided before, during and after the process illustrated by Figures 23-28, and that some of the operations described below may be replaced or eliminated with respect to additional embodiments of the method . The order of operations / processes may be interchangeable. Materials, configurations, dimensions, and / or processes that are the same as or similar to the above-described embodiments described with reference to Figs. 1A-22B may be used in the following embodiments, and the detailed description thereof may be omitted.

After the structure shown in Figs. 10A to 10E is formed, a mask pattern 342 is formed on the first sacrificial layer 215, as shown in Fig. A mask pattern 342 is the first sacrificial layer 215 and is made of a different _{material, SiO 2, SiCN, SiON,} Al 2 O 3, SiN, TiN, TaN, TiO 2, Si, Ge, SiGe, SiC , or other Includes one or more layers of suitable material. In some embodiments, a plurality of patterning operations using two or more mask layers are used to form the mask pattern.

By using the mask pattern 342 as an etching mask, the first sacrificial layer 215, the first insulating layer 222 and the S / D structures 220 and 221 are anisotropically etched to form the opening 344 , This opening separates the adjacent S / D structures as shown in Fig. In some embodiments, a plurality of etching operations are performed. For example, an initial etch operation etches the first sacrificial layer 215 and stops on the first insulating layer 222. Subsequent etching operations etch the first sacrificial layer 215 and the epitaxial layer of the S / D structure. The etch masks for the initial etch and subsequent etch may be the same (using the same layer of the mask pattern) or different (using different layers of the mask pattern).

At least one of the side portions of the S / D structures 220 and 221 is removed by an etching operation so that the etched side surfaces of the S / D structures 220 and 221 are substantially parallel to the side surfaces of the upper fin structure 204. [ do. Mask pattern 342 is removed by using suitable etching and / or planarization operations such as CMP.

After the mask pattern 342 is removed, a second insulating layer 346 is formed over the patterned first sacrificial layer 215 and the patterned S / D structures 220 and 221, as shown in FIG. 25 .

After the second insulating layer 346 is formed, a first interlayer dielectric (ILD) layer 345 is formed to fill the opening 344 and cover the first sacrificial layer 215 and the S / D structure. A planarization process, such as a CMP process, is performed to remove the excess material for the ILD layer 345 and a portion of the second insulation layer 346. By the planarization process, the upper surface of the first sacrificial layer 215 is exposed in some embodiments, as shown in Fig.

Subsequently, as shown in FIG. 27, the first sacrificial layer 215 is removed by forming the opening 348 by using an appropriate etching operation. In some embodiments, a wet etch operation is used.

After the first sacrificial layer 215 is removed, the first insulating layer 222 remaining on the top or side of the S / D structure is removed to expose the S / D structure, and the S / D structure 220 and / A silicide layer 227 is formed on the exposed uppermost and side surfaces of the silicon carbide layer 221. [ Subsequently, a contact portion 250 is formed to contact the silicide layer 227 formed on the top and sides of the S / D structure.

After forming the contacts 250, additional CMOS processes are performed to form various features such as additional inter-level dielectric layers, contact / via, interconnect metal layers and passive layers.

It will be appreciated that not all advantages are necessarily discussed herein, that specific advantages are not required for all embodiments or examples, and that other embodiments or examples may provide different advantages.

For example, in the present disclosure, once a merged epitaxial layer of a source / drain structure is separated by a subsequent patterning operation due to the narrow separation of an adjacent fin structure, and thus a short-circuit problem between adjacent FinFETs It is possible to reduce the device area without causing a problem. In addition, the size of the post-etched S / D structure can be more precisely controlled since a material having a higher etch selectivity (e.g., Si) is used as the second sacrificial layer in the separate patterning.

According to one aspect of the disclosure, in a method of forming a semiconductor device including a fin field effect transistor (FinFET), a sacrificial layer is formed over a FinFET structure and a source / drain structure of an isolation dielectric layer. A mask pattern is formed on the sacrificial layer. By using the mask pattern as an etching mask, the sacrificial layer and the source / drain structure are patterned, thereby forming an opening adjacent to the patterned sacrificial layer and the source / drain structure. A dielectric layer is formed in the opening. After the dielectric layer is formed, the patterned sacrificial layer is removed to form a contact opening over the patterned source / drain structure. A conductive layer is formed in the contact opening.

According to another aspect of the present disclosure, there is provided a method of forming a semiconductor device including a FinFET, comprising: forming a first source / drain structure of a first FinFET structure, a second source / drain structure of a second FinFET structure, A sacrificial layer is formed on the isolated insulating layer. The first source / drain structure and the second source / drain structure are merged. A mask pattern is formed on the sacrificial layer. The sacrificial layer and the first and second source / drain structures are patterned by using the mask pattern as an etching mask, thereby separating the first and second source / drain structures and forming the patterned sacrificial layer and the patterned first and second Forming an opening adjacent the source / drain structure. A dielectric layer is formed in the opening. After the dielectric layer is formed, the patterned sacrificial layer is removed to form contact openings on the patterned first and second source / drain structures, respectively. A conductive layer is formed in the contact opening.

According to another aspect of the present disclosure, a semiconductor device including a FinFET includes a first fin structure including a first fin structure extending in a first direction and a first source / drain structure, a first FinFET adjacent to the first FinFET, And a second fin structure including a second fin structure and a second source / drain structure disposed in the first direction and extending in a first direction, and a dielectric layer separating the first source / drain structure and the second source / drain structure. The first source / drain structure is asymmetric with respect to the first fin structure in a cross-section along the second direction crossing the first direction.

1) A method of forming a semiconductor device including a fin field effect transistor (FinFET) according to some embodiments of the present disclosure, comprising: forming a sacrificial layer and an insulative isolation layer over a source / drain structure of a FinFET structure; Forming a mask pattern on the sacrificial layer; Patterning the sacrificial layer and the source / drain structure by using the mask pattern as an etch mask to form openings adjacent the patterned sacrificial layer and the source / drain structure; Forming a dielectric layer in the openings; Removing the patterned sacrificial layer to form a contact opening over the patterned source / drain structure after the dielectric layer is formed; And forming a conductive layer in the contact opening.

2) A method of forming a semiconductor device comprising a fin field effect transistor (FinFET) according to some embodiments of the present disclosure, wherein before the sacrificial layer is formed, a first insulating layer is formed between the source / May be formed over the insulating layer.

3) A method of forming a semiconductor device comprising a fin field effect transistor (FinFET) according to some embodiments of the present disclosure, the sacrificial layer comprising at least one of a Group IV elemental or compound materials .

4) A method of forming a semiconductor device comprising a fin field effect transistor (FinFET) according to some embodiments of the present disclosure, wherein the sacrificial layer may be made of one or more of silicon based or aluminum based dielectric materials.

5) A method of forming a semiconductor device comprising a fin field effect transistor (FinFET) according to some embodiments of the present disclosure, wherein after the sacrificial layer and the source / drain structure are patterned and before the dielectric layer is formed, And forming a second insulating layer on the patterned sacrificial layer and the source / drain structure.

6) A method of forming a semiconductor device comprising a fin field effect transistor (FinFET) in accordance with some embodiments of the present disclosure, wherein after the sacrificial layer and the source / drain structure are patterned and the second insulating layer is formed The method may further include forming a silicide layer on the patterned source / drain structure.

7) A method of forming a semiconductor device comprising a fin field effect transistor (FinFET) in accordance with some embodiments of the present disclosure, the sacrificial layer comprising: a first insulating layer, But may be made of other materials.

8) A method of forming a semiconductor device comprising a fin field effect transistor (FinFET) according to some embodiments of the present disclosure, wherein the source / drain structure comprises a fin structure, and on the opposite sides, The source / drain structure may be patterned such that the at least one epitaxial layer formed on at least one of the sides is partially etched.

9) A method of forming a semiconductor device comprising a fin field effect transistor (FinFET) according to some embodiments of the present disclosure, wherein the source / drain structure comprises at least one epitaxial layer formed on both sides And may be patterned to be partially etched.

10) A method of forming a semiconductor device comprising a fin field effect transistor (FinFET) according to some embodiments of the present disclosure, the source / drain structure including a pin structure embedded in the isolation layer, One or more epitaxial layers formed on top of the structure and the source / drain structures may be patterned such that the at least one epitaxial layer is partially etched.

11) A method of forming a semiconductor device comprising a fin field effect transistor (FinFET) according to some embodiments of the present disclosure includes forming a first source / drain structure of a first FinFET structure, a second source / drain of a second FinFET structure, Wherein the first source / drain structure and the second source / drain structure are merged, and forming a sacrificial layer over the isolation dielectric layer; Forming a mask pattern on the sacrificial layer; Patterning the sacrificial layer and the first and second source / drain structures by using the mask pattern as an etch mask to separate the first and second source / drain structures and to pattern the patterned sacrificial layer and the patterned 1 and the second source / drain structure; Forming a dielectric layer in the openings; Removing the patterned sacrificial layer to form contact openings on each of the patterned first and second source / drain structures after the dielectric layer is formed; And forming a conductive layer in the contact openings.

12) A method of forming a semiconductor device comprising a fin field effect transistor (FinFET) according to some embodiments of the present disclosure, wherein the first source / drain structure has the same conductivity type as the second source / drain structure .

13) A method of forming a semiconductor device comprising a fin field effect transistor (FinFET) according to some embodiments of the present disclosure, the first source / drain structure having a conductivity type different from the second source / .

14) A method of forming a semiconductor device comprising a fin field effect transistor (FinFET) according to some embodiments of the present disclosure, wherein before forming the sacrificial layer, a first insulating layer is formed over the first and second A source / drain structure and the isolation insulating layer.

15) A method of forming a semiconductor device comprising a fin field effect transistor (FinFET) according to some embodiments of the present disclosure, wherein the sacrificial layer may be made of at least one of Si, SiGe, and Ge.

16) A method of forming a semiconductor device including a fin field effect transistor (FinFET) in accordance with some embodiments of the present disclosure, the sacrificial layer SiOC, SiC, SiON, SiCN, SiOCN, at least one of SiN and SiO ₂ .

17) A method of forming a semiconductor device comprising a fin field effect transistor (FinFET) in accordance with some embodiments of the present disclosure, comprising the steps of: after the sacrificial layer and the first and second source / drain structures are patterned, And forming a second insulating layer on the patterned sacrificial layer and the first and second source / drain structures prior to forming the patterned sacrificial layer.

18) A method of forming a semiconductor device comprising a fin field effect transistor (FinFET) in accordance with some embodiments of the present disclosure, the sacrificial layer comprising a first insulating layer, a first insulating layer, But may be made of other materials.

19) A method of forming a semiconductor device comprising a fin field effect transistor (FinFET) according to some embodiments of the present disclosure, wherein the first source / drain structure may comprise a first epitaxial layer And the second source / drain structure may include a second epitaxial layer, the first epitaxial layer may be merged with the second epitaxial layer, and the first and second source / / Drain structure may be patterned to separate the merged first and second epitaxial layers.

20) A semiconductor device comprising a fin field effect transistor (FinFET) according to some embodiments of the present disclosure includes: a first FinFET including a first fin structure extending in a first direction and a first source / drain structure; A second FinFET disposed adjacent to the first FinFET and including a second fin structure and a second source / drain structure extending in the first direction; And a dielectric layer separating the first source / drain structure and the second source / drain structure, wherein the first source / drain structure is a cross-section along a second direction crossing the first direction, But may be asymmetric with respect to the first pin structure.

The foregoing outlines features of the various embodiments or examples to enable those skilled in the art to better understand the aspects of the disclosure. Those skilled in the art should appreciate that the present disclosure can readily be used as a basis for designing or modifying other processes and structures to accomplish the same objectives and / or to achieve the same advantages of the embodiments or examples introduced herein. Those skilled in the art will also appreciate that such equivalents may be made without departing from the spirit and scope of this disclosure, and without departing from the spirit and scope of this disclosure, various changes, substitutions and alterations can be made herein.

Claims (10)

A method of forming a semiconductor device comprising a fin field effect transistor (FinFET), the method comprising:
Forming a sacrificial layer over the source / drain structure and isolated isolation layer of the FinFET structure;
Forming a mask pattern on the sacrificial layer;
Patterning the sacrificial layer and the source / drain structure by using the mask pattern as an etch mask to form openings adjacent the patterned sacrificial layer and the source / drain structure;
Forming a dielectric layer in the openings;
Removing the patterned sacrificial layer to form a contact opening over the patterned source / drain structure after the dielectric layer is formed; And
Forming a conductive layer in the contact opening
Gt; (FinFET), < / RTI > The method according to claim 1,
Wherein the first insulating layer is formed on the source / drain structure and the isolation insulating layer before the sacrificial layer is formed. 3. The method of claim 2,
Further comprising forming a second insulating layer on the patterned sacrificial layer and the source / drain structure after the sacrificial layer and the source / drain structure are patterned and before the dielectric layer is formed. (FinFET). ≪ / RTI > The method of claim 3,
Further comprising forming a silicide layer on the patterned source / drain structure after the sacrificial layer and the source / drain structure are patterned and before the second insulating layer is formed. ≪ / RTI > The method of claim 3,
Wherein the sacrificial layer is made of a material different from the isolation insulating layer, the first insulating layer, and the second insulating layer. The method according to claim 1,
Wherein the source / drain structure comprises a fin structure, and at least one epitaxial layer formed on opposite sides and on top of the fin structure,
Wherein the source / drain structure is patterned such that the at least one epitaxial layer formed on at least one of the sides is partially etched. ≪ Desc / Clms Page number 19 > The method according to claim 6,
Wherein the source / drain structure is patterned such that the at least one epitaxial layer formed on both sides of the sides is partially etched. The method according to claim 1,
Wherein the source / drain structure comprises a pin structure embedded in the isolation dielectric layer, and at least one epitaxial layer formed on top of the pin structure,
Wherein the source / drain structure is patterned such that the at least one epitaxial layer is partially etched. ≪ Desc / Clms Page number 20 > A method of forming a semiconductor device comprising a fin field effect transistor (FinFET), the method comprising:
The first source / drain structure of the first FinFET structure, the second source / drain structure of the second FinFET structure, the first source / drain structure and the second source / drain structure are merged, Forming a sacrificial layer over the layer;
Forming a mask pattern on the sacrificial layer;
Patterning the sacrificial layer and the first and second source / drain structures by using the mask pattern as an etch mask to separate the first and second source / drain structures and to pattern the patterned sacrificial layer and the patterned 1 and the second source / drain structure;
Forming a dielectric layer in the openings;
Removing the patterned sacrificial layer to form contact openings on each of the patterned first and second source / drain structures after the dielectric layer is formed; And
Forming a conductive layer in the contact openings
Gt; (FinFET), < / RTI > A method of forming a semiconductor device,
Forming an epitaxial layer on the source / drain regions of the fin structure;
Forming a sacrificial layer over the epitaxial layer;
Patterning the sacrificial layer and the epitaxial layer;
Forming an insulating layer on the patterned sacrificial layer and the patterned epitaxial layer;
Forming a dielectric layer over the insulating layer;
Removing the patterned sacrificial layer after the dielectric layer is formed; And
Forming a conductive contact over the patterned epitaxial layer;
/ RTI > A method of forming a semiconductor device,

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