KR101950829B1 - Circuit for generating driving voltage of light emitting display device and method for driving the same - Google Patents

Abstract

The present invention relates to a driving voltage generating circuit for a light emitting diode display capable of increasing power efficiency. When a magnitude of a current consumed in a driving voltage supply line is smaller than or equal to a preset reference value, And supplies the stabilized voltage to the driving voltage supply line. When the magnitude of the current consumed in the driving voltage supply line exceeds the reference value, the boosted voltage is supplied to the driving voltage supply line by boosting the input voltage from the outside .

Description

TECHNICAL FIELD [0001] The present invention relates to a driving voltage generating circuit for a light emitting diode display, and a driving voltage generating circuit for driving the same.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power supply circuit of a light emitting diode display, and more particularly to a driving voltage generating circuit for a light emitting diode display capable of increasing power efficiency and a driving method thereof.

The pixels of the light emitting diode display include light emitting diodes, which emit light in accordance with the driving current generated by the driving voltage.

In order to stabilize the driving current supplied to the pixels, it is necessary to stabilize the driving voltage which is the source of the driving current, and the driving voltage after the stabilization step becomes smaller than the original driving voltage. However, if the driving voltage is reduced, there is a problem that the power efficiency is decreased and the consumption current is increased.

SUMMARY OF THE INVENTION The present invention has been conceived to solve the problems as described above, and it is an object of the present invention to provide a driving voltage supplying apparatus and a driving method thereof, which can stabilize a boosted driving voltage when a low- A drive voltage generating circuit for a light emitting diode display device and a driving method thereof that can improve power efficiency by providing a boosted drive voltage directly to a drive voltage supply line without stabilizing the boosted drive voltage when an image of a high gradation strong against noise is displayed It has its purpose.

According to an aspect of the present invention, there is provided a driving voltage generating circuit for a light emitting diode display, comprising: a driving voltage generating circuit for boosting an input voltage from the outside when a magnitude of a current consumed in a driving voltage supply line is less than or equal to a preset reference value; And supplies the stabilized voltage to the driving voltage supply line. When the magnitude of the current consumed in the driving voltage supply line exceeds the reference value, the boosted voltage is supplied to the driving voltage supply line by boosting the input voltage from the outside. do.

Wherein the driving voltage generating circuit comprises: a boosting unit for raising an input voltage from the outside to generate a boosting voltage and outputting the boosting voltage through a boosting output terminal; A stabilization unit for stabilizing the boosting voltage input to the stabilization input terminal to generate a stabilization voltage, outputting the stabilization voltage through the stabilization output terminal, and receiving the stabilization voltage from the stabilization output terminal through the stabilization feedback terminal; A first switch performing one of a first switching operation for controlling the boosting output terminal and the stabilizing input terminal in accordance with a switch control signal and a second switching operation for connecting the boosting output terminal and the stabilizing output terminal to each other; A first voltage divider for dividing a boosting voltage from the boosting output terminal to generate a first divided voltage; A first switching operation that is controlled according to the switch control signal to connect the boosting output terminal to the first voltage divider and a second switching operation that separates the boosting output terminal from the connection of the first voltage division period, A second switch for performing; A second voltage divider for dividing a boosting voltage from the stabilizing output terminal to generate a second divided voltage; A third switch for performing either a first switching operation for connecting the stabilization output terminal and the stabilization feedback terminal in accordance with the switch control signal and a second switching operation for connecting the stabilization output terminal and the second voltage divider; A first divided voltage from the first voltage divider and a second divided voltage from the second voltage divider, and compares the divided voltage with a preset reference voltage. Based on the comparison result, A pulse mode selection unit for continuously outputting drive pulses or discontinuously outputting drive pulses; And a controller for counting the number of drive pulses output from the pulse mode selector for a predetermined threshold period and, when the number of counted drive pulses is less than a predetermined threshold value, When the number of the driving pulses counted during the threshold period is equal to or greater than the threshold value, the driving voltage supply line is controlled so that the first to third switches perform the first switching operation, And a switch controller for controlling the first to third switches to perform the second switching operation when it is determined that the magnitude of the current consumed exceeds the reference value.

The switch control unit controls the first to third switches to perform the first switching operation.

Wherein the boosting unit comprises: an inductor connected between an input line for supplying an external input voltage and a boosting input terminal of the boosting unit; A boosting switching element connected between the boosting input terminal and the ground terminal, the boosting switching element being controlled by a drive pulse applied to the boosting feedback terminal of the boosting unit, And a diode connected between the boosting input terminal and the boosting output terminal.

And the inductor is located outside the boosting unit.

The stabilizing unit includes: a stabilizing voltage divider that divides a stabilizing voltage applied to the stabilization feedback terminal to generate a stabilizing divided voltage; A stabilizing comparator which compares a preset first reference voltage with a stabilizing divided voltage from the stabilizing voltage divider and generates an output based on the comparison result; And a stabilization switching element controlled in accordance with an output from the stabilization comparator and connected between the stabilization input terminal and the stabilization output terminal.

Wherein the pulse mode selector comprises: a first comparator that compares a second reference voltage, which is set in advance, with a first divided voltage from the first voltage divider, and generates an output in accordance with the comparison result; A second comparator for comparing a third reference voltage, which is preset, with a second divided voltage from the second voltage divider, and generating an output in accordance with the comparison result; A first switching operation for selecting and outputting an output from the first comparator in response to a switch control signal from the switch control unit and a second switching operation for selecting and outputting an output from the second comparator, 4 switches; An inverter for inverting an output from said fourth switch; A clock generator for generating a clock pulse; A third comparator that compares a clock pulse from the clock generator with an output from the inverter and generates an output based on the comparison result; And a drive pulse generator for receiving the clock pulses from the clock generator and generating the drive pulses by outputting the clock pulses continuously or discontinuously according to the output from the third comparator. do.

Wherein the switch control unit counts the number of drive pulses output from the pulse mode selection unit for a predetermined threshold period so that when the number of the counted drive pulses is less than a preset threshold value, Wherein the control circuit controls the fourth switch to perform a first switching operation when the number of the driving pulses counted during the threshold period is equal to or greater than the threshold value, The control unit determines that the magnitude of the current exceeds the reference value and controls the first to third switches to perform the second switching operation.

A timer for setting a plurality of critical periods; A counter for counting the driving pulses inputted to itself from the starting point of each threshold period set by the timer and terminating counting at the end of each threshold period; And a switch control signal output unit for comparing the number counted from the counter at the end of each threshold period with a threshold value and for outputting a first switch control signal or a second switch control signal based on the comparison result, do.

The first reference voltage, the second reference voltage, and the third reference voltage are all set to the same value.

According to another aspect of the present invention, there is provided a driving method of a driving voltage generating circuit for a light emitting diode display, comprising: comparing a magnitude of a current consumed in a driving voltage supply line with a preset reference value; Boosting and stabilizing an input voltage from the outside when the magnitude of the current consumed in the driving voltage supply line is less than or equal to the reference value and supplying the boosted voltage to the driving voltage supply line; And boosting the input voltage from the outside and supplying the boosted voltage to the driving voltage supply line when the magnitude of the current consumed in the driving voltage supply line exceeds the reference value.

The driving voltage generating circuit and the driving method thereof for a light emitting diode display according to the present invention have the following effects.

According to the present invention, when a low-gradation image which is vulnerable to noise is displayed, the boosted driving voltage is stabilized and supplied to the driving voltage supply line to prevent distortion of the driving current. In addition, when a high- It is possible to increase the power efficiency by directly supplying the driving voltage to the driving voltage supply line without stabilizing the driving voltage.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a view illustrating a light emitting diode display device according to an embodiment of the present invention. FIG.
FIG. 2 is a circuit diagram of a pixel included in one of the pixels of FIG. 1;
3 is a detailed configuration diagram of a drive voltage generating circuit according to an embodiment of the present invention;
4 is a diagram showing waveforms of clock pulses output from the clock generator and waveforms of peak pulses and drive pulses output from the drive pulse generator;
5 is a diagram showing a detailed configuration of a switch control unit;
6A is a diagram for explaining the operation of a drive voltage generation circuit operating in the PSM system;
6B is a diagram for explaining the operation of the driving voltage generating circuit operating in the CCM system;

1 is a view illustrating a light emitting diode display device according to an embodiment of the present invention.

1, a light emitting diode display device according to an embodiment of the present invention includes a display unit DSP, a system SYS, a scan driver SD, a data driver DD, a timing controller TC, And a supply unit PS.

The display unit DSP includes a plurality of pixels PXL and a plurality of scan lines SL1 to SLm for transmitting various signals necessary for displaying the images of the pixels PXL, DLn and a plurality of power supply lines. Only the driving voltage supply line VDL among these power supply lines is shown in Fig.

These pixels PXL are arranged in a matrix on the display unit DSP. The pixels PXL are divided into a red pixel PXL for displaying red, a green pixel PXL for displaying green, and a blue pixel PXL for displaying blue.

The system SYS outputs a vertical synchronizing signal, a horizontal synchronizing signal, a clock signal, and image data through an interface circuit through a Low Voltage Differential Signaling (LVDS) transmitter of a graphic controller. The vertical / horizontal synchronizing signal and the clock signal output from the system SYS are supplied to the timing controller TC. In addition, the image data sequentially output from the system SYS is supplied to the timing controller TC.

The timing controller TC generates a data control signal, a scan control signal, and a light emission control signal by using a horizontal synchronizing signal, a vertical synchronizing signal, and a clock signal input to the timing controller TC, Supply. The data control signal includes a dot clock, a source shift clock, a source enable signal, a polarity reversal signal, and the like. The scan control signal includes scan start pulse, scan shift clock, scan output enable, and the like.

The data driver DD samples the image data according to the data control signal from the timing controller TC and then outputs the sampling image corresponding to one horizontal line per horizontal period (1H, 2H, ...) Latches the data and supplies the latched image data to the data lines DL1 to DLn. That is, the data driver DD converts the video data from the timing controller TC into an analog pixel signal (data signal) by using the gamma voltage input from the power supply unit PS and outputs the analog pixel signal (data signal) to the data lines DL1 to DLn Supply.

The scan driver SD includes a shift register for sequentially generating scan signals in response to a scan start pulse from the timing controller TC and a level shifter for shifting the scan signals to a voltage level suitable for driving the pixel PXL. . The scan driver SD sequentially supplies scan pulses to the scan lines SL1 to SLm in response to a scan control signal from the timing controller TC.

The power supply unit PS generates a gamma voltage, a driving voltage, a base voltage and a reference voltage required for driving the pixel PXL. To this end, the power supply unit includes a gamma voltage generation circuit for generating a gamma voltage, a drive voltage generation circuit for generating a drive voltage, a base voltage generation circuit for generating a base voltage, and a reference voltage generation circuit for generating a reference voltage. The driving voltage VDD generated from the driving voltage generating circuit is supplied to the pixels through the driving voltage supply line VDL.

The pixels PXL have the same configuration, which will be described in detail with reference to FIG.

FIG. 2 is a circuit diagram of a pixel included in one of the pixels of FIG. 1. Referring to FIG.

As shown in FIG. 2, one pixel PXL includes a data switching element Tr_DS, a driving switching element Tr_DR, a storage capacitor Cst, and a light emitting diode OLED.

The data switching element Tr_DS switches the data voltage from the data line DL in accordance with the scan signal from the scan line SL. To this end, the gate electrode of the data switching element Tr_DS is connected to the scan line SL, the source electrode thereof is connected to the data line DL, and the drain electrode is connected to the gate electrode of the drive switching element Tr_DR .

The driving switching element Tr_DR adjusts the magnitude of the driving current according to the driving voltage VDD and the data voltage switched from the data switching element Tr_DS. To this end, the gate electrode of the driving switching element Tr_DR is connected to the drain electrode of the data switching element Tr_DS, the source electrode thereof is connected to the driving voltage supply line VDL, and the drain electrode is connected to the light emitting diode OLED. As shown in FIG.

The storage capacitor Cst is connected between the gate electrode and the source electrode of the drive switching element Tr_DR.

The light emitting diode OLED is connected between the source electrode of the drive switching element Tr_DR and the base low voltage supply line. That is, the anode electrode of the light emitting diode (OLED) is connected to the source electrode of the drive switching element (Tr_DR), and the cathode electrode is connected to the base low voltage supply line. The light emitting diode OLED emits light in accordance with the driving current from the driving switching element Tr_DR.

In particular, the driving voltage generator according to the present invention compares the magnitude of the current consumed in the driving voltage supply line VDL with a preset reference value, and when the magnitude of the consumption current is smaller than or equal to the reference value, Boosting and stabilizing. And supplies the stabilized driving voltage VDD to the driving voltage supply line VDL together with the boosted voltage. On the other hand, if the comparison result indicates that the magnitude of the current consumption exceeds the reference value, the input voltage from the outside is boosted and supplied to the driving voltage supply line VDL.

That is, as the number of pixels for displaying an image of a high gradation is increased, the driving current required by the display portion DSP is increased, which causes the current load of the driving voltage supply line VDL to increase, The consumption current is increased. Conversely, the larger the number of pixels for displaying an image of low gradation, the smaller the driving current required by the display portion DSP, which reduces the current load on the driving voltage supply line VDL and reduces the consumption current from this line . For example, when black of the darkest 0 gradation is displayed on the entire screen of the display unit (DSP) of the light emitting diode display device capable of displaying 256 gradations, the drive current required from the display unit DSP is about 1 [mA ]to be. On the other hand, when displaying the brightest 255 gradations of white on the entire screen of the display (DSP) of such a light emitting diode display, the drive current required from the display DSP is about 150 [mA]. Therefore, the current load of the driving voltage supply line VDL relatively decreases as the number of pixels displaying dark low gradations is relatively large, while the current load of the driving voltage supply line VDL becomes relatively large as the number of pixels displaying bright high gradations .

In order to stabilize the driving current supplied to the pixels, it is necessary to stabilize the driving voltage (VDD; boosted driving voltage) which is the source of the driving current. The driving voltage (VDD) VDD). However, if the driving voltage VDD becomes smaller, there is a problem that the power efficiency is decreased and the consumption current is increased. On the other hand, when the boosted driving voltage is directly used without the stabilization step, it is possible to prevent a decrease in power efficiency. However, in this case, a ripple is generated in the boosted driving voltage due to external noise, It can be distorted. This distortion of the driving current is particularly problematic when displaying a screen with a lower tone than when displaying a screen with a higher tone.

Accordingly, the present invention provides a driving voltage supply line (VDL) that stabilizes a boosted driving voltage (VDD) when an image with a low gray level is susceptible to noise, thereby preventing distortion of the driving current, When the gradation image is displayed, the boosted driving voltage VDD can be directly supplied to the driving voltage supply line VDL without stabilization, thereby enhancing the power efficiency.

To this end, according to the present invention, the magnitude of the current load is monitored by monitoring the voltage change of the driving voltage supply line (VDL), and the magnitude of the detected current load is compared with the reference value to determine the current load Or a current load corresponding to a low gray level, and determines whether the boosted driving voltage is stabilized or not based on the determination result.

To this end, the driving voltage generating circuit according to the present invention may have the following configuration.

3 is a detailed configuration diagram of a driving voltage generating circuit according to an embodiment of the present invention.

3, the driving voltage generating circuit according to the embodiment of the present invention includes a boosting unit BST, a stabilization unit RGT, a first switch SW1, a first voltage divider VD1, A switch SW2, a second voltage divider VD2, a third switch SW3, a pulse mode selector PMS, and a switch controller SCT.

The boosting unit BST increases the input voltage Vin from the outside to generate a boosting voltage, and outputs the boosting voltage. The boosting unit BST includes a boosting input terminal bit, a boosting output terminal bot and a boosting feedback terminal bft. The input voltage Vin from the outside is boosted through a boosting input terminal (bit) (BST), and the boosting voltage is output through the boosting output terminal (bot).

For this boosting operation, the boosting unit BST includes an inductor L, a boosting switching element Tr_bs, and a diode D.

The inductor L is connected between an input line (not shown) for supplying an input voltage Vin from outside and a boosting input terminal (bit). The inductor L is large in size and installed outside the boosting unit BST.

The boosting switching element Tr_bs is controlled according to the drive pulse DPS output from the pulse mode selector PMS and is connected between the boosting input terminal bit and the ground terminal. Here, the drive pulse DPS output from the pulse mode selector PMS is supplied to the gate electrode of the boosting switching element Tr_bs through the boosting feedback terminal bft.

The diode D is connected between the boosting input terminal (bit) and the boosting output terminal (bot). This diode (D) prevents reverse current flowing from the boosting output terminal (bot) to the boosting input terminal (bit).

The operation of the boosting unit BST having such a configuration will now be described.

The boosting switching element Tr_bs is periodically turned on and off according to the driving pulse DPS provided from the pulse mode selector PMS. When the boosting switching element Tr_bs is turned on, a current generated by the input voltage Vin passes through the inductor L and flows to the ground terminal, and energy is accumulated in the inductor L. Thus, the voltage of the boosting input terminal (bit) rises by this energy. The voltage applied to the boosting input terminal (bit) is the boosting voltage, which has a higher value than the input voltage Vin. Thereafter, when the boosting switching element Tr_bs is turned off, the boosting voltage of the boosting input terminal (bit) is supplied to the boosting output terminal bot via the diode D.

The stabilization unit RGT stabilizes the boosting voltage inputted to the stabilization input terminal rit to generate a stabilization voltage, and outputs the stabilization voltage. The stabilization unit RGT may be a regulator and may be an LDO (Low Dropout) regulator. The stabilization unit RGT includes a stabilization input terminal rit, a stabilization output terminal rot and a stabilization feedback terminal rft. The boosting voltage provided from the boosting unit BST is supplied to the stabilization input terminal rit Is inputted to the stabilization part (RGT), and the stabilization voltage is outputted through the stabilization output terminal (rot).

VDD in Fig. 3 means either a stabilized boosting voltage or an unstable boosting voltage.

For this stabilization operation, the stabilization part RGT includes a stabilization voltage divider VDr, a stabilization comparator RCMP, and a stabilization switching element Tr_rg.

The stabilizing voltage divider VDr divides the stabilizing voltage applied to the stabilizing feedback terminal rft to generate a stabilizing divided voltage. To this end, the stabilization voltage divider (VDr) comprises a first resistor (R1) and a second resistor (R2) connected in series between the stabilization feedback terminal (rft) and the ground terminal. The stabilized divided voltage is output from the node to which the first resistor R1 and the second resistor R2 are connected.

The stabilization comparator RCMP compares the preset first reference voltage Vref1 with the stabilizing voltage divided from the stabilizing voltage divider VDr and generates an output based on the comparison result. That is, the stabilizing comparator RCMP includes a non-inverting terminal (+), an inverting terminal (-) and an output terminal. The first reference voltage Vref1 is input to the non-inverting terminal (+ -), and an output is generated from the output terminal. The stabilizing comparator RCMP generates an output when the stabilizing divided voltage is less than the first reference voltage Vref1, but does not generate an output when the stabilizing divided voltage is equal to or greater than the first reference voltage Vref1. Here, the fact that an output is generated from the stabilizing comparator (RCMP) means that the voltage of the high logic from the stabilizing comparator (RCMP) is output, and that no output from the stabilizing comparator (RCMP) The voltage of the low logic is outputted from the output terminal.

The stabilization switching element Tr_rg is controlled in accordance with the output from the stabilization comparator RCMP and is connected between the stabilization input terminal rit and the stabilization output terminal rot. This stabilization switching element Tr_rg is turned on only when there is an output from the stabilization comparator RCMP. When the stabilizing switching element Tr_rg is turned on, the boosting voltage applied to the stabilizing input terminal rit is attenuated by the voltage corresponding to the internal resistance of the turned-on stabilizing switching element Tr_rg, and the attenuated boosting voltage Voltage) is supplied to the stabilizing output terminal rot. As this boosting voltage passes through the stabilizing switching element Tr_rg, its noise component is removed and stabilized. At this time, the stabilization voltage has a smaller value than the boosting voltage. For example, if the boosting voltage applied to the stabilization input terminal rit is 10.5 [V], the stabilization voltage applied to the stabilization output terminal rot through the stabilization switching element Tr_rg may be 10 [V] .

The first switch SW1 is controlled according to the switch control signal SCS to perform any one of the first switching operation and the second switching operation. That is, the first switch SW1 includes a first switching operation for connecting the boosting output terminal bot and the stabilizing input terminal rit, and a second switching operation for connecting the boosting output terminal bot and the stabilizing output terminal rot to each other And performs any one of the second switching operations.

The first voltage divider VD1 divides the boosting voltage from the boosting output terminal bot to generate a first divided voltage. To this end, the first voltage divider VD1 includes a third resistor R3 and a fourth resistor R3 connected in series between the input terminal thereof (the input terminal of the first voltage divider VD1 to which the boosting voltage is input) and the ground terminal, (R4). The first divided voltage is output from a node to which the third resistor R3 and the fourth resistor R4 are connected.

The second switch SW2 is controlled according to the switch control signal SCS to perform any one of the first switching operation and the second switching operation. That is, the second switch SW2 has a first switching operation for connecting the boosting output terminal bot and the first voltage divider VD1, and a second switching operation for disconnecting the connection between the boosting output terminal bot and the first voltage divider VD1 And performs any one of the second switching operations.

The second voltage divider VD2 divides the boosting voltage from the stabilizing output terminal rot to generate the second divided voltage. To this end, the second voltage divider VD2 includes a fifth resistor and a sixth resistor serially connected between the input terminal thereof (the input terminal of the second voltage divider VD2 to which the boosting voltage is input) and the ground terminal . And a second divided voltage is output from a node to which the fifth resistor and the sixth resistor are connected.

The third switch SW3 is controlled according to the switch control signal SCS to perform any one of the first switching operation and the second switching operation. That is, the third switch SW3 has a first switching operation for connecting the stabilization output terminal rot and the stabilization feedback terminal rft, and a second switching operation for connecting the stabilization output terminal roto and the second voltage divider VD2, And performs a switching operation.

The pulse mode selection unit PMS receives the divided voltage of either the first divided voltage from the first voltage divider VD1 and the second divided voltage from the second voltage divider VD2, And compares preset reference voltages. Then, based on the comparison result, the drive pulse DPS is continuously output or discontinuously output.

For this operation, the pulse mode selection unit PMS includes a first comparator CMP1, a second comparator CMP2, a fourth switch SW4, an inverter INV, a clock generator CLG, a third comparator CMP3 and a drive pulse generator DFG.

The first comparator CMP1 compares the preset second reference voltage Vref2 with the first divided voltage from the first voltage divider VD1 and generates an output in accordance with the comparison result. That is, the first comparator CMP1 includes a non-inverting terminal (+), an inverting terminal (-) and an output terminal, and the second reference voltage Vref2 is input to the non-inverting terminal (+ (-), and an output is generated from the output terminal. The first comparator CMP1 generates an output when the first divided voltage is lower than the second reference voltage Vref2, whereas when the first divided voltage is equal to or greater than the second reference voltage Vref2, I never do that. Here, the fact that an output is generated from the first comparator CMP1 means that the voltage of the high logic from the first comparator CMP1 is outputted, and that no output from the first comparator CMP1 is generated, 1 < / RTI > voltage from the comparator CMP1.

The second comparator CMP2 compares the third reference voltage Vref3 set in advance with the second divided voltage from the second voltage divider VD2, and generates an output in accordance with the comparison result. That is, the second comparator CMP2 includes a non-inverting terminal (+), an inverting terminal (-) and an output terminal. The third reference voltage Vref3 is input to the non-inverting terminal (+ (-) to the second divided voltage, and an output is generated from the output terminal. The second comparator CMP2 generates an output when the second divided voltage is lower than the third reference voltage Vref3, whereas when the second divided voltage is equal to or greater than the third reference voltage Vref3, I never do that. Here, the fact that an output is generated from the second comparator CMP2 means that the voltage of the high logic from the second comparator CMP2 is output, and that no output is generated from the second comparator CMP2, 2 < / RTI > voltage from the comparator CMP2.

The fourth switch SW4 is controlled according to the switch control signal SCS from the switch control unit SCT to perform any one of the first switching operation and the second switching operation. That is, the fourth switch SW4 selects either one of the first switching operation for selecting and outputting the output from the first comparator CMP1 and the second switching operation for selecting and outputting the output from the second comparator CMP2 .

The inverter INV inverts the output from the fourth switch SW4. For example, the inverter INV inverts the voltage of the high logic to the voltage of the low logic when the voltage of the high logic is input, and inverts the voltage of the low logic to the voltage of the high logic when the voltage of the low logic is input.

A clock generator (CLG) generates a clock pulse (CLK). The clock pulse CLK includes a plurality of impulses having a constant period and a duty ratio.

The third comparator CMP3 compares the clock pulse CLK from the clock generator CLG with the output from the inverter INV and generates an output based on the comparison result. That is, the third comparator CMP3 includes a non-inverting terminal (+), an inverting terminal (-) and an output terminal. The clock pulse CLK is input to the non-inverting terminal (+ The output from the inverter (INV) is input, and the output is generated from the output terminal. The third comparator CMP3 generates an output when the output from the inverter INV is smaller than the clock pulse CLK while the output from the inverter INV is equal to the third reference voltage Vref3 If it is larger than this, no output is generated. Here, the fact that an output is generated from the third comparator CMP3 means that the voltage of the high logic from the third comparator CMP3 is outputted, and that no output from the third comparator CMP3 is generated, 3 < / RTI > voltage of the low logic is outputted from the comparator CMP3.

When the clock pulse CLK has a high logic voltage and a low logic voltage and the output of the third comparator CMP3 is a low logic voltage, the third comparator CMP3 outputs the clock pulse CLK and And outputs a voltage having the same phase. That is, the voltage of the low logic and the voltage of the high logic are alternately outputted from the third comparator (CMP3). On the other hand, when the output inputted to the third comparator CMP3 is the voltage of the high logic, the third comparator CMP3 outputs the voltage of low logic.

The drive pulse generator DFG receives the clock pulse CLK from the clock generator CLG and successively outputs the clock pulse CLK in accordance with the output from the third comparator CMP3, Thereby generating the drive pulse DPS. This will be described in detail with reference to FIG.

4 is a diagram showing the waveform of the clock pulse CLK output from the clock generator CLG and the waveforms of the peak pulse PPS and the drive pulse DPS output from the drive pulse generation unit DFG.

The drive pulse generating unit DFG generates a peak pulse PPS having a high logic voltage at each time point corresponding to a falling edge of the clock pulse CLK as shown in Fig. When the peak pulse PPS is a low logic voltage, the drive pulse DPS having a high logic voltage at the rising edge of the clock pulse CLK is output, The drive pulse DPS is dropped to the low voltage at the time when the voltage of the high logic is changed. However, if the peak pulse PPS (dotted line circle portion in FIG. 4) has a high logic value at the time point (or just before the rising edge) corresponding to the rising edge other than the falling edge of the clock pulse CLK, The clock pulse CLK (the clock pulse CLK having the voltage of the high logic) is ignored. Therefore, as shown in Fig. 4, one cycle of the drive pulse DPS having the voltage of the high logic corresponding to the point in time is omitted. That is, the drive pulse generator DFG compares the clock pulse CLK from the clock generator CLG with the output from the third comparator CMP3 and, at the rising edge of the clock pulse CLK, The above described peak pulse PPS is changed to a voltage of high logic at this point when the output from the capacitor CMP3 is a high logic voltage, and the peak pulse PPS is at the high logic value The clock pulse CLK at the rising edge time is ignored. 3, the driving pulse DPS is normally output in the first period T1, the second period T2 and the fourth period T4, while the driving pulse DPS of the third period T3 is omitted . Accordingly, the driving pulses DPS are continuously output during the first and second periods T1 and T2, and the driving pulses are omitted during the third period T3, thereby generating the discontinuous driving pulse DPS.

If the driving pulse DPS is omitted at least once, the driving voltage generating circuit is driven by the PSM (pulse skipped mode) method. On the other hand, if the driving pulse DPS is continuously output continuously, the driving voltage generating circuit is driven by the CCM (Continuous Conduction Mode) method.

That is, the driving voltage generating circuit of the present invention detects the magnitude of the current consumed in the driving voltage supply line (VDL) by sensing the magnitude of the current consumed from the stabilizing output terminal (rot) The driving pulse DPS of one period is omitted. On the other hand, when the magnitude of the current consumption is larger than the reference value, the driving method is driven by the CCM method in which the driving pulse DPS is omitted continuously.

The driving pulse generating unit DFG may set the duty ratio of the driving pulse DPS to be different from the duty ratio of the driving pulse DPS when the driving pulse DPS is the CCM method. For example, the duty ratio of the drive pulse DPS when the PSM method is set to be larger or smaller than the duty ratio of the drive pulse DPS when the CCM method is used.

The switch control unit SCT counts the number of the drive pulses DPS output from the pulse mode selection unit PMS for a predetermined threshold period and compares the counted number of drive pulses DPS with a predetermined threshold value. That is, the switch control unit SCT sets a plurality of threshold periods and counts the number of the driving pulses DPS generated from the start point to the end point of each critical period. When the number of driving pulses DPS counted in the corresponding critical period is smaller than the threshold value, it is determined that the magnitude of the current consumed in the driving voltage supply line VDL is smaller than or equal to the reference value. Based on this determination, the first to fourth switches SW1 to SW4 are all controlled to perform the first switching operation. On the other hand, when the number of the driving pulses DPS counted during the corresponding threshold period is equal to or greater than the threshold value, it is determined that the magnitude of the current consumed in the driving voltage supply line VDL exceeds the reference value. Based on this determination, the first to fourth switches SW1 to SW4 are all controlled to perform the second switching operation. If the driving pulses DPS are continuously output continuously during the critical period, the number of the driving pulses DPS may be equal to or greater than the threshold value. On the other hand, if the driving pulse DPS is discontinuously output at least once during the critical period, the number of the driving pulses DPS may be smaller than the threshold value.

For example, if the number of the driving pulses DPS output during any one of the threshold periods (hereinafter referred to as the first threshold period) is smaller than the threshold value, the switch control unit SCT, at the end of the first threshold period, And outputs a control signal. Subsequently, if the number of the drive pulses DPS output during the next threshold period (hereinafter referred to as the second threshold period) is equal to the threshold value, the switch control unit SCT determines the end point of the second threshold period And outputs the second switch control signal.

5 shows a detailed configuration of the switch control unit SCT. The switch control unit SCT includes a timer TM, a counter CT and a switch control signal output unit SWC .

The timer TM sets a plurality of threshold periods as described above. The time lengths of this critical period can all be set equal.

The counter CT counts driving pulses DPS inputted thereto from the starting point of each threshold period set from the timer TM, and terminates counting at the end of each threshold period and is reset again. After the reset, the count is immediately counted from the beginning of the next critical period. This counter CT counts the number of drive pulses DPS at a time point corresponding to the rising edge of the drive pulse DPS.

The switch control signal output unit SWC compares the count counted from the counter CT with the threshold value at the end of each critical period and outputs a first switch control signal or a second switch control signal based on the comparison result . For example, the switch signal output section outputs a first switch control signal when the number provided from the counter CT (the number of the drive pulses DPS) is smaller than the threshold value, while the number provided from the counter CT (DPS)) is equal to or greater than the threshold value, the second switch control signal is output.

The switch control unit SCT controls the first to fourth switches SW1 to SW4 to perform the first switching operation before the initial circuit operates. That is, the switch control unit SCT supplies the first switch control signal to the first to fourth switches SW1 to SW4 before the initial circuit operates.

On the other hand, the first to third reference voltages Vref1 to Vref3 can all be set to the same value. For example, it can be set to 1.2 [V]. The first internal reference voltage Vref3 may be a reference value for distinguishing the consumption current at the time of high gradation and the consumption current at the time of low gradation.

The operation of the driving voltage generating circuit constructed as above will be described below.

First, referring to FIG. 6A, an example in which the driving voltage generating circuit is driven in a pulse skipped mode (PSM) will be described.

6A is a diagram for explaining the operation of the driving voltage generating circuit operating in the PSM system.

As shown in FIG. 6A, the first to fourth switches SW1 to SW4 perform the first switching operation. The first switch SW1 connects the boosting output terminal bot and the stabilizing input terminal rit and the second switch SW2 connects the boosting output terminal bot and the first voltage divider VD1 to each other. And the third switch SW3 connects the stabilizing output terminal rot and the stabilizing voltage divider to each other and the fourth switch SW4 connects the output terminal of the first comparator CMP1 and the inverter INV to each other Connect. For convenience of explanation, components not connected by operation of these switches have been deleted. However, in actual circuits, these components actually exist only in connection with the components of Fig. 6A.

First, the boosting unit BST boosts the input voltage Vin to generate a boosting voltage, and supplies the boosting voltage to the boosting output terminal bot. Then, the boosting voltage of the boosting output terminal bot is input to the stabilization unit RGT via the first switch SW1. The stabilizing unit RGT generates a stabilizing voltage by reducing the boosting voltage to a voltage smaller than the boosting voltage. This stabilization voltage is supplied to the drive voltage supply line VDL via the stabilization output terminal rot.

On the other hand, the first voltage divider VD1 divides the boosting voltage of the boosting output terminal bot to generate a first divided voltage. This first divided voltage is supplied to the inverting terminal (-) of the first comparator (CMP1). Then, the first comparator CMP1 compares the magnitude of the first divided voltage with the first reference voltage Vref1. If the first divided voltage is greater than the first reference voltage Vref1, the first comparator CMP1 outputs a low logic voltage. The voltage of this low logic is inverted to the voltage of high logic through the inverter (INV). The voltage of the high logic level from the inverter INV is supplied to the non-inverting terminal (+) of the third comparator CMP3. Then, the third comparator CMP3 compares the voltage of this high logic with the clock pulse CLK. At this time, since the voltage of the high logic is equal to or greater than the clock pulse CLK, the third comparator CMP3 generates an output of low logic. Then, the drive pulse generating section DFG generates the drive pulse DPS discontinuously. The drive pulse DPS to the drive pulse generating section DFG is supplied to the gate electrode of the boosting switching element Tr_bs and the switch control section SCT. The boosting switching element Tr_bs is turned off in response to the driving pulse DPS. At this time, a boosting voltage of 10.5 [V] may be applied to the boosting output terminal bot by the drive pulse DPS.

On the other hand, the switch control section SCT counts the number of the driving pulses DPS. If the driving pulse DPS is omitted once by the discontinuous driving pulse DPS and the total number of the driving pulses DPS in the current critical period is smaller than the threshold value, If it is the end of the period, the switch control section SCT outputs the first switch control signal. Then, the first to fourth switches SW1 to SW4 still remain in the first switch SW1 operating state. At this time, the boosting voltage of the boosting output terminal bot is reduced to 10 [V] via the stabilization part RGT and supplied to the driving voltage supply line VDL.

However, even though the driving pulse DPS is omitted once by the discontinuous driving pulse DPS but the total number of the driving pulses DPS in the current critical period is larger than the threshold value, If it is the end of the period, the switch control section SCT outputs the second switch control signal. At this time, the first to fourth switches SW1 to SW4 perform the second switching operation. This will be described in detail with reference to FIG.

6B is a diagram for explaining the operation of the driving voltage generation circuit operating in the CCM system.

As shown in FIG. 6B, the first to fourth switches SW1 to SW4 perform a second switching operation. Therefore, the first switch SW1 connects the boosting output terminal bot and the stabilizing output terminal rot, and the second switch SW2 connects the boosting output terminal bot and the first voltage divider VD1 The third switch SW3 connects the stabilizing output terminal rot and the second voltage divider VD2 to each other and the fourth switch SW4 is connected to the output terminal of the second comparator CMP2, (INV) to each other. For convenience of explanation, components not connected by operation of these switches have been deleted. However, in actual circuits, these components do not actually connect to the components of FIG. 6B but actually exist.

First, the boosting unit BST boosts the input voltage Vin to generate a boosting voltage, and supplies the boosting voltage to the boosting output terminal bot. Then, the boosting voltage of the boosting output terminal (bot) is input to the stabilizing output terminal (rot) through the first switch SW1. That is, this boosting voltage is supplied directly to the stabilizing output terminal roto without passing through the stabilization part RGT. Therefore, this boosting voltage is supplied to the drive voltage supply line VDL via the stabilization output terminal rot. At this time, the boosting voltage applied to the boosting output terminal (bot) and the stabilizing output terminal (rot) may be 10 [V].

On the other hand, the second voltage divider VD2 divides the boosting voltage of the stabilizing output terminal rot to generate the second divided voltage. This second divided voltage is supplied to the inverting terminal (-) of the second comparator CMP2. Then, the second comparator CMP2 compares the magnitude of the second divided voltage with the third reference voltage Vref3. If the second divided voltage is smaller than the third reference voltage Vref3, the second comparator CMP2 outputs a voltage of high logic. The voltage of this high logic is inverted to the voltage of low logic through the inverter (INV). The voltage of the low logic from this inverter INV is supplied to the non-inverting terminal (+) of the third comparator CMP3. Then, the third comparator CMP3 compares the voltage of the low logic with the clock pulse CLK. At this time, since the voltage of the row logic is smaller than or equal to the clock pulse CLK, the third comparator CMP3 generates an output having the same phase as the clock pulse CLK. That is, the output from the third comparator CMP3 has a waveform that alternately has a high voltage and a low voltage such as a clock pulse CLK. Then, the drive pulse generating section DFG continuously generates the drive pulse DPS. The drive pulse DPS to the drive pulse generating section DFG is supplied to the gate electrode of the boosting switching element Tr_bs and the switch control section SCT. The boosting switching element Tr_bs is periodically turned on and off in response to the driving pulse DPS. At this time, a boosting voltage of 10 [V] may be applied to the boosting output terminal bot by the drive pulse DPS.

On the other hand, the switch control section SCT counts the number of the driving pulses DPS. If the current number of the total driving pulses DPS in the current critical period is greater than the threshold by the current continuous driving pulse DPS and the current time is the end time of the current critical period, ) Outputs a second switch control signal. Then, the first to fourth switches SW1 to SW4 still remain in the second switch SW2 operating state. Therefore, the voltage of 10 [V] of the boosting output terminal bot is applied to the driving power supply line as it is without passing through the stabilization part RGT.

However, as described above, when the output of the second comparator CMP2 becomes low logic and a discontinuous driving pulse DPS is output and the number of total driving pulses DPS in the current critical period is smaller than the threshold value State, and if this current time point is the end of the current critical period, this switch control section SCT outputs the first switch control signal.

As described above, according to the present invention, when the driving voltage generating circuit is driven by the PSM system in which the current consumption is relatively low (that is, when an image of a low gradation level vulnerable to noise is displayed), the driving voltage generating circuit stabilizes the boosted driving voltage To the driving voltage supply line VDL to prevent distortion of the driving current. On the other hand, when the driving voltage generating circuit is driven by the CCM system in which the current consumption is relatively high (that is, when an image of a high gradation strong against noise is displayed), the driving voltage generating circuit does not stabilize the boosted driving voltage It is possible to increase the power efficiency by providing it to the driving voltage supply line VDL.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents. Will be clear to those who have knowledge of.

BST: boosting part RGT: stabilizing part
PMS: Pulse mode selector VD #: 1st voltage divider
VDr: Stabilizing voltage divider SW #: No. switch
CMP #: # # Comparator RCMP: Stabilization Comparator
CLG: clock generator CLK: clock pulse
SCS: Switching signal SCT: Switch control part
DPS: drive pulse DFG: drive pulse generator
INV: Inverting Vref #: No. # Reference voltage
R #: Resistor # Resistor bit: Boosting input terminal
bot: boosting output terminal bft: boosting feedback terminal
rit: stabilization input terminal rot: stabilization output terminal
rft: stabilization feedback terminal VDD: drive voltage

Claims (11)

When the magnitude of the current consumed in the drive voltage supply line for displaying an image of low gradation is smaller than or equal to a predetermined reference value, the boosting voltage is generated by raising the input voltage from the outside, stabilizes the boosting voltage, And supplies the boosted voltage to the voltage supply line. When the magnitude of the current consumed in the drive voltage supply line for displaying an image of a high gradation exceeds the reference value, the boosting voltage is generated by raising the input voltage from the outside, Voltage supply line,
A boosting unit for boosting an input voltage from the outside to generate a boosting voltage and outputting the boosting voltage through a boosting output terminal;
A stabilization unit for stabilizing the boosting voltage input to the stabilization input terminal to generate a stabilization voltage, outputting the stabilization voltage through the stabilization output terminal, and receiving the stabilization voltage from the stabilization output terminal through the stabilization feedback terminal;
A first switch performing one of a first switching operation for controlling the boosting output terminal and the stabilizing input terminal in accordance with a switch control signal and a second switching operation for connecting the boosting output terminal and the stabilizing output terminal to each other;
A first voltage divider for dividing a boosting voltage from the boosting output terminal to generate a first divided voltage;
A first switching operation that is controlled according to the switch control signal to connect the boosting output terminal to the first voltage divider and a second switching operation that separates the boosting output terminal from the connection of the first voltage division period, A second switch for performing;
A second voltage divider for dividing a boosting voltage from the stabilizing output terminal to generate a second divided voltage;
A third switch for performing either a first switching operation for connecting the stabilization output terminal and the stabilization feedback terminal in accordance with the switch control signal and a second switching operation for connecting the stabilization output terminal and the second voltage divider;
A first divided voltage from the first voltage divider and a second divided voltage from the second voltage divider, and compares the divided voltage with a preset reference voltage. Based on the comparison result, A pulse mode selection unit for continuously outputting drive pulses or discontinuously outputting drive pulses; And
The number of drive pulses output from the pulse mode selection unit is counted for a predetermined threshold period, and when the counted number of drive pulses is less than a predetermined threshold value, the magnitude of the current consumed in the drive voltage supply line is smaller than the reference value When the number of drive pulses counted during the threshold period is equal to or greater than the threshold value, the control unit controls the first to third switches to perform the first switching operation, And a switch controller for determining that the magnitude of the current exceeds the reference value and controlling all of the first to third switches to perform the second switching operation. delete The method according to claim 1,
Wherein the switch control unit controls the first to third switches to perform the first switching operation. The method according to claim 1,
The boosting unit includes:
An inductor connected between an input line for supplying an external input voltage and a boosting input terminal of the boosting unit;
A boosting switching element connected between the boosting input terminal and the ground terminal, the boosting switching element being controlled by a drive pulse applied to the boosting feedback terminal of the boosting unit, And
And a diode connected between the boosting input terminal and the boosting output terminal. 5. The method of claim 4,
And the inductor is located outside the boosting unit. 5. The method of claim 4,
The stabilizer may include:
A stabilizing voltage divider for dividing a stabilizing voltage applied to the stabilization feedback terminal to generate a stabilizing divided voltage;
A stabilizing comparator which compares a preset first reference voltage with a stabilizing divided voltage from the stabilizing voltage divider and generates an output based on the comparison result; And
And a stabilization switching element which is controlled according to an output from the stabilization comparator and is connected between the stabilization input terminal and the stabilization output terminal. The method according to claim 6,
Wherein the pulse mode selector comprises:
A first comparator for comparing a second reference voltage, which is preset, with a first divided voltage from the first voltage divider, and generating an output in accordance with the comparison result;
A second comparator for comparing a third reference voltage, which is preset, with a second divided voltage from the second voltage divider, and generating an output in accordance with the comparison result;
A first switching operation for selecting and outputting an output from the first comparator in response to a switch control signal from the switch control unit and a second switching operation for selecting and outputting an output from the second comparator, 4 switches;
An inverter for inverting an output from said fourth switch;
A clock generator for generating a clock pulse;
A third comparator that compares a clock pulse from the clock generator with an output from the inverter and generates an output based on the comparison result; And
And a drive pulse generator for receiving the clock pulses from the clock generator and generating the drive pulses by continuously or continuously outputting the clock pulses in accordance with the output from the third comparator A drive voltage generation circuit for a diode display device. 8. The method of claim 7,
The switch control unit,
The number of drive pulses output from the pulse mode selection unit is counted for a predetermined threshold period, and when the counted number of drive pulses is less than a predetermined threshold value, the magnitude of the current consumed in the drive voltage supply line is smaller than the reference value And controls the fourth switch to perform the first switching operation. When the number of drive pulses counted during the threshold period is equal to or greater than the threshold value, the magnitude of the current consumed in the drive voltage supply line is And controls the first to third switches to perform a second switching operation based on the determination that the reference value is exceeded. 9. The method of claim 8,
A timer for setting a plurality of critical periods;
A counter for counting the driving pulses inputted to itself from the starting point of each threshold period set by the timer and terminating counting at the end of each threshold period; And
And a switch control signal output unit for outputting a first switch control signal or a second switch control signal based on the result of the comparison by comparing the number counted from the counter at the end of each threshold period with a threshold value A drive voltage generation circuit for a diode display device. 8. The method of claim 7,
Wherein the first reference voltage, the second reference voltage, and the third reference voltage are all set to the same value.

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