KR101947533B1 - Output power adjustment apparatus and method - Google Patents

Abstract

The present relates to an apparatus and a method for adjusting output power which can dynamically provide a power amplifier specified for each frequency channel within a broadband frequency range. To this end, the apparatus for adjusting output power comprises: a plurality of power amplifiers for amplifying each input signal with power according to each power enable signal; a plurality of capacitors connected in parallel to an output signal of the plurality of power amplifiers and connected to the ground according to each cap enable signal; and a controller for selecting one or more power amplifiers and capacitors according to frequency information of the input signal among the plurality of power amplifiers and the plurality of capacitors and outputting one or more power enable signals corresponding to the selected power amplifier and one or more cap enable signals corresponding to the selected capacitor.

Description

TECHNICAL FIELD [0001] The present invention relates to an output power correcting apparatus and method,

The present invention relates to an output power correcting apparatus and method, and more particularly, to an output power correcting apparatus and method for maintaining output power constant and outputting power efficiently regardless of the band of each output frequency even within a wide frequency range .

Power amplifiers are known. The conventional power amplifier amplifies the input signal and outputs the amplified signal to the impedance matching circuit connected to the antenna. The amplified signal is transmitted as a radio signal.

Conventional power amplifiers are designed specifically for specific frequencies. Accordingly, the power amplifier enables effective power amplification within the designed frequency. When the power amplifier deviates from a specific specific frequency band, there arises a problem that the amplification efficiency is inferior. Therefore, there is a need to design a separate power amplifier when the frequency range of the radio signal is different.

On the other hand, TVWS (TV White Space) is a frequency band allocated for transmitting / receiving a TV in the past, but is not used for broadcasting at present, so that it can be used by anyone without requiring any license. This frequency band is expected to be used in many fields because of its wide reach and excellent transparency for buildings and the like.

Such a TVWS band channel is known to have a wide frequency band. For example, the TVWS band can use a wide frequency band from 470 MHz to 698 MHz, but the design of the power amplifier is not suitable due to the design characteristics of the power amplifier's adaptive frequency.

Thus, there is a need for an apparatus and method for correcting output power that can be dynamically used in a wide frequency band and enable efficient power output for each frequency channel.

10-2014-0042569 (A), April 07, 2014

It is an object of the present invention to provide an apparatus and method for correcting an output power that can dynamically provide a power amplifier specialized for each frequency channel within a wide frequency range.

It is another object of the present invention to provide an output power correcting apparatus and method that can provide linearity of power amplification in a wide frequency range and dynamically adjust a power output so that an efficient power output is performed for each frequency channel.

It is another object of the present invention to provide an apparatus and method for correcting an output power by controlling a plurality of power amplifiers and a plurality of capacitors to enable efficient power output for each frequency channel within a wide frequency range.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are not restrictive of the invention, unless further departing from the spirit and scope of the invention as defined by the appended claims. It will be possible.

According to an aspect of the present invention, there is provided an output power correcting apparatus comprising: a plurality of power amplifiers each for power amplifying an input signal according to a respective power enable signal; a plurality of power amplifiers connected in parallel to output signals of the plurality of power amplifiers, A plurality of capacitors connected to the ground according to a signal, a plurality of power amplifiers and a plurality of capacitors, one or more power amplifiers and capacitors are selected according to frequency information of input signals, and one or more power enable signals corresponding to the selected power amplifiers And a controller for outputting one or more cap enable signals corresponding to the selected capacitors.

In the above-described output power correction apparatus, the controller determines a predetermined number of power amplifier parameters and a number of capacitor parameters corresponding to the frequency channel according to the frequency channel information of the input signal, and selects one or more power amplifiers according to the determined number of power amplifier parameters Outputs a power enable signal of the selected power amplifier, selects one or more capacitors according to the determined number of capacitors parameter, and outputs a cap enable signal of the selected capacitor.

The output power compensating apparatus may further include a peak voltage sensing circuit for sensing a peak voltage of an output signal and a comparator for comparing a peak voltage with a reference voltage, The number of amplifiers parameter and the number of capacitors parameter are determined in advance.

The output power compensating apparatus may further include a reference voltage generating circuit for generating a peak voltage sensing circuit reference voltage for sensing a peak voltage of an output signal and a comparator for comparing a peak voltage and a reference voltage, The number of power amplifier and the number of capacitors for each frequency channel are determined in advance according to the comparison signal.

In the above-described output power correction device, the controller may sequentially output a cap enable signal for connecting a sequentially increasing number of capacitors to ground while outputting a power enable signal to a series of power amplifiers corresponding to the number of reference power amplifiers And receives a comparison signal from the comparator during the output of the sequential cap enable signal, and sets the power amplifier number parameter and the capacitor number parameter in advance for each frequency channel according to each received comparison signal.

In the output power correction apparatus, the peak voltage sensing circuit includes a first variable resistor for adjusting the peak voltage, the reference voltage generating circuit includes a second variable resistor for adjusting the reference voltage, A power amplifier for outputting a power enable signal to a series of power amplifiers corresponding to the number of power amplifiers, sequentially outputs a cap enable signal for connecting a sequentially increasing number of capacitors to a ground and for outputting a sequential cap enable signal Receiving a comparison signal from the comparator and adjusting one or more variable resistances of the first variable resistor or the second variable resistor when all of the received comparison signals do not satisfy the specified condition, The number of amplifiers and the number of capacitors are divided by frequency channel Determined.

An output power correction method according to an aspect of the present invention includes: recognizing frequency channel information of an input signal; selecting one or more power amplifiers and one or more capacitors corresponding to frequency channel information among a plurality of power amplifiers and a plurality of capacitors And coupling the selected one or more capacitors to ground and activating the selected one or more power amplifiers to amplify the input signal.

In the output power correction method, the selection step may include determining a predetermined number of power amplifier parameters and capacitor number parameters corresponding to a frequency channel according to frequency channel information of an input signal, and determining one or more power amplifiers according to the determined number of power amplifier parameters And selects one or more capacitors according to the determined number of capacitors parameter.

(A) activating power amplifiers corresponding to the number of test power amplifiers determined from the number of reference power amplifiers, (b) comparing the number of reference power amplifiers from the number of reference capacitors, (C) comparing the peak voltage with a reference voltage, (d) comparing the peak voltage with a reference voltage, (c) comparing the peak voltage of the output signal coupled to the capacitor and the power amplifier, (F) incrementing the number of test capacitors and repeating steps (c) through (e) if the peak voltage meets the specified condition, do.

(G) incrementing the number of test power amplifiers and repeating steps (b) to (f); (h) calculating a number of successive capacitors corresponding to the plurality of test power amplifiers And (i) determining a number of power amplifiers and a number of capacitors parameter of the specified frequency channel from the number of test power amplifiers corresponding to the number of one or more common success capacitors.

(J) changing a value of a variable resistor for adjusting a reference voltage or a peak voltage, and (k) if the number of successive capacitors is not common in step (h) repeating the steps a) through h).

The apparatus and method for correcting output power according to the present invention can dynamically provide a power amplifier specialized for each frequency channel within a wide frequency range.

Also, the apparatus and method for correcting output power according to the present invention can provide linearity of power amplification in a wide frequency range and dynamically adjust power output so that efficient power output is performed for each frequency channel.

In addition, the apparatus and method for correcting output power according to the present invention have the effect of enabling efficient power output for each frequency channel within a wide frequency range by controlling a plurality of power amplifiers and a plurality of capacitors.

The effects obtained by the present invention are not limited to the above-mentioned effects, and other effects not mentioned can be clearly understood by those skilled in the art from the following description will be.

1 is a diagram illustrating an exemplary implementation of an output power correction apparatus.
2 is a diagram showing a concrete hardware configuration for correcting the output power.
3 is a diagram showing a schematic control flow for correcting the output power.
4 is a diagram showing an exemplary concrete control flow of a process of setting parameters for each frequency channel.
5 is a diagram showing an example of a simulation result of an output signal according to the number of power amplifier activations.
6 is a diagram showing an example of a simulation result of an output signal according to the number of grounded capacitors.

The above and other objects, features and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings, in which: It can be easily carried out. In the following description, well-known functions or constructions are not described in detail since they would obscure the invention in unnecessary detail. Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a diagram illustrating an exemplary implementation of an output power correction apparatus 100. FIG.

The output power correction apparatus 100 of FIG. 1 can transmit a radio signal whose output power is corrected according to the present invention, and can also receive a radio signal.

The output power correction apparatus 100 according to the present invention can be configured in various types. For example, the output power correction apparatus 100 may constitute a device for transmitting and receiving a radio signal, a portable terminal, and a dedicated radio signal transceiver.

The output power correction apparatus 100 includes at least a hardware block (see FIG. 2) for correcting the output power, and these blocks are composed of a chipset or an integrated circuit. Alternatively, the output power correction apparatus 100 may be embedded in a baseband chipset for encoding and transmitting a frequency (carrier) signal of a wireless signal.

As shown in FIG. 1, the baseband chipset encodes data to be transmitted as a radio signal to a frequency of a specific frequency channel to output an encoded signal TX-IN, The calibration chipset receives this signal.

In addition, the output power correction chipset receives control signals from the baseband chipset. The control signals are received according to UART, I2C or known data transmission and reception protocols within the board. The control signal includes, for example, frequency channel information. This frequency channel information includes data that can identify or identify the frequency channel of the output signal TX-IN of the wideband frequency band (e.g., the TVWS band). For example, the frequency channel information includes a frequency channel number or the like.

The output power correction chipset specifies the frequency channel according to the control signal, reconfigures the internal circuit to be connected to the output signal by using various parameters stored in correspondence with the specified frequency channel, amplifies the output signal and outputs the output (PA_OUT) do.

The amplified signal PA_OUT can be output to the antenna through the antenna impedance matching circuit.

2 is a diagram showing a concrete hardware configuration for correcting the output power.

2, the output power correction apparatus 100 includes a plurality of power amplifiers 101, a plurality of (capacitors) 103, a peak voltage sense circuit 105, a reference voltage generation circuit 107 ), A comparator 109 and a controller 111. [ The output power correction device 100 may be comprised of a single chipset or an integrated circuit for power amplification or may be embedded in another chipset (e.g., a baseband chipset). The blocks of some of the blocks of FIG. 2 may be omitted according to a design variant, and other blocks not shown in FIG. 2 may be further included in the output power correction apparatus 100.

2, a plurality of power amplifiers 101 amplify an input signal TX-IN. Each of the power amplifiers 101 amplifies the input signal according to a corresponding power Enable signal (power supply enable signal) (for example, a signal of logic '1' or '0' And outputs it. The number of the plurality of power amplifiers 101 may be, for example, 36 (N).

As such, each of the power amplifiers 101 may not amplify or amplify the input signal in accordance with the corresponding power enable signal.

A plurality of capacitors (103) are connected in parallel to output signals amplified by the plurality of power amplifiers (101). Each of the plurality of capacitors 103 may be connected to ground (Gnd) or open according to an enable signal corresponding to the cap. A switch or relay connected to each capacitor 103 connects the capacitor 103 to ground when a corresponding cap enable signal (e.g., a signal of logic '1' or '0') is applied and the cap enable signal The capacitor 103 can be opened from the ground if it is not applied (logic signal opposite to the cap enable signal). The number of the plurality of capacitors 103 may be, for example, 20 (M). The cap enable signal is a control signal for connecting the corresponding capacitor 103 to ground.

The peak voltage sensing circuit 105 senses the peak voltage of the output signal PA_OUT output from the plurality of power amplifiers 101 and connected to the plurality of capacitors 103. The peak voltage sensing circuit 105 is comprised of a circuit for detecting a known peak voltage to sense the maximum voltage of the output signal. The peak voltage sensing circuit includes at least two resistors so that the voltage between the two resistors is output as the peak voltage for comparison. One resistor is a fixed resistor (resistor connected to ground) and the other resistor is a variable resistor. The variable resistor 105-1 for the peak voltage can increase its resistance value in a predetermined unit starting from the reference resistance value and thereby adjust the magnitude of the peak voltage output from the peak voltage sensing circuit 105. [

The reference voltage generating circuit 107 generates a reference voltage to be used for comparison with the peak voltage output from the peak voltage detecting circuit 105. [ The reference voltage generating circuit 107 generates a reference voltage between the resistors, which is generated from the input power supply VDD and includes at least two resistors. One resistor is a fixed resistor (resistor connected to ground) and the other resistor is a variable resistor. The variable resistor for reference voltage 107-1 is configured to increase its resistance value in a predetermined unit starting from a reference resistance value, and accordingly, the magnitude of the reference voltage can be adjusted.

Here, the reference resistance value is set so that the variable resistor 105-1 for peak voltage is larger than the fixed resistor 105-3 for the connected peak voltage. For example, the peak voltage variable resistor 105-1 is set to a value three times larger than the peak voltage fixed resistor 105-3 (the resistance of the peak voltage fixed resistor 105-3) Value) * 0.04 times the magnitude of the resistance value can be increased. Also, the reference resistance value is set so that the variable resistor for reference voltage 107-1 is larger than the connected fixed resistor. For example, the reference resistance for the reference voltage 107-1 is set to a value 3.2 times larger than the fixed resistance for the reference voltage (resistance value of the reference voltage fixing resistor 107-3) * 0.04 times The resistance value can be increased.

The peak voltage variable resistor 105-1 and the reference voltage variable resistor 107-1 are used to reflect various environmental factors inside the output power correction device 100. [ For example, in order to adjust an output signal that is unstable depending on the temperature or humidity of the outside or the inside, variations in components, etc., the peak voltage variable resistor 105-1 and the reference voltage variable resistor 107-1 are used The resistance values of the peak voltage variable resistor 105-1 and the reference voltage variable resistor 107-1 are adjusted so as to output a power amplified signal of a constant magnitude.

The peak voltage signal output from the peak voltage sensing circuit 105 is proportional to at least the magnitude of the peak voltage and the reference voltage signal output from the reference voltage generating circuit 107 may be a signal proportional to the reference voltage. The reference voltage may be at least the magnitude of the (desired) voltage intended to be amplified output to the impedance matching circuit of the antenna.

The comparator 109 compares the peak voltage with the reference voltage. The comparator 109 has a known comparison circuit, compares the magnitudes of the two voltages, and outputs a comparison signal Vcomp that indicates the result of the comparison. The comparison signal may represent a logic '1' or '0', for example, a comparison signal of logic '1' is output from the comparator 109 when the peak voltage is greater than the reference voltage and a comparison signal of logic ' Is outputted from the comparator 109.

The controller 111 dynamically amplifies an input signal according to a designated frequency by using a plurality of power amplifiers 101 and a plurality of capacitors 103. The controller 111 may include one or more execution units for executing a programmable gate array (e.g., an FPGA) or instruction code to perform a predetermined algorithm (e.g., programing a gate array or a program stored in a memory) And may be configured to dynamically amplify the input signal corresponding to a particular frequency channel.

For example, the controller 111 is provided with a memory (volatile or non-volatile memory) internally or externally, and is capable of storing the frequency (frequency) of each frequency channel in the frequency band (for example, 470 MHz to 698 MHz) Frequency band in the band, for example, 470 MHz to 475 MHz, 475 MHz to 480 MHz, and so on).

The controller 111 receives the frequency information of the input signal through the control signal. The control signal may be received, for example, via a UART, I2C, or dedicated signal line, and the controller 111 may extract the frequency information of the input signal in the control signal. The frequency information may be frequency channel information and may include a frequency channel number or the like.

The controller 111 identifies a frequency channel corresponding to the input signal and determines a predetermined number of power amplifier parameters and a number of capacitor parameters through a memory or the like corresponding to the identified frequency channel.

The controller 111 selects at least one of the plurality of power amplifiers 101 according to the determined number of power amplifiers 101 according to the determined number of power amplifiers 101 and activates the selected one or more of the power amplifiers 101 And outputs a power enable signal of each selected power amplifier 101 for outputting the amplified signal. For example, a series of power amplifiers 101 as many as the number parameter (for example, 15) among the total number of power amplifiers M is selected to output power enable signals for activating each of the selected power amplifiers 101 do.

The controller 111 also selects one or more capacitors 103 according to the number parameter of the plurality of capacitors 103 according to the determined capacitor number parameter and selects one or more capacitors 103 selected for connecting the selected capacitor 103 to the ground And outputs one or more cap enable signals corresponding to the capacitor (103). For example, a series of capacitors 103 as many as the number parameter (for example, 11) among the total capacitors 103 (N) are selected to output cap enable signals for connecting the selected capacitors 103 to the ground do.

The controller 111 stores individual (different) power amplifier number parameters and capacitor number parameters for each frequency channel in a memory or the like. The controller 111 can further store parameters other than the two parameters for each frequency channel. For example, the controller 111 maximizes the output efficiency of the input signal for each frequency channel by further utilizing the set values of the reference voltage variable resistor 107-1 and the peak voltage variable resistor 105-1 Power amplification is possible.

The controller 111 sets parameters for each frequency channel before power amplification of an input signal to be transmitted as a radio signal. The frequency-dependent parameters are set in advance to set the resistance values of the plurality of power amplifiers 101, the plurality of capacitors 103, the reference voltage variable resistor 107-1 and / or the peak voltage variable resistor 105-1 .

The controller 111 recognizes frequency channel information through a control signal for parameter setting prior to transmission of a radio signal, selects an input signal provided through a baseband chipset or the like as many as a test number among a plurality of power amplifiers 101, The number of capacitors 103 is selected and connected to the ground in accordance with the comparison signal from the comparator 109, and the number of power amplifiers, the number of capacitors, and the variable resistor parameter for reference voltage (b) The variable resistance parameter for the peak voltage is determined in advance.

For example, the controller 111 outputs a power enable signal to a series of power amplifiers 101 corresponding to the number of reference power amplifiers (for example, 10, etc.) for each frequency channel in accordance with a control signal, And outputs a cap enable signal for connecting the sequentially increasing number of capacitors 103 to the ground during the output of the enable signal. The comparator 109 compares the peak voltage with the reference voltage to output a comparison signal with respect to the number of capacitors while sequentially outputting the cap enable signal and the controller 111 compares the number of power amplifiers with the number of capacitors The number parameter can be preset for each frequency channel.

When the controller 111 does not satisfy all of the received comparison signals on a specified condition (for example, a condition in which the peak voltage is larger than the reference voltage) for each frequency channel, the controller 111 sets the variable resistor for peak voltage The power amplifier number parameter and the capacitor number parameter are set for each frequency channel by adjusting the reference voltage variable resistor 107-1 and / or the reference voltage variable resistor 107-1 and then using the comparison signal from the comparator 109 which is received again.

The controller 111 controls the number of power amplifiers, the number of capacitors, the reference resistance variable resistor 107-1 and / or the peak resistance variable resistor 105-1, May be mapped to (parameter) frequency channel identifiers and stored in memory (or internal registers).

After the scanning process or the calibration process is completed, the controller 111 determines the corresponding parameter in the memory (register) according to the frequency channel information of the input signal and controls the power amplifier 101, the capacitor 103 ) And / or variable resistors to enable efficient power amplification for each frequency channel.

The process performed by the controller 111 will be described in more detail with reference to FIGS. 3 and 4. FIG.

3 is a diagram showing a schematic control flow for correcting the output power.

The control flow of Fig. 3 is performed by the output power correction apparatus 100. Fig. The control flow of FIG. 3 is performed using the blocks of FIG. 2 and is preferably controlled by the controller 111.

First, the output power correction apparatus 100 (the controller 111) determines whether or not an output signal of the available frequency channel (for example, the TVWS band) (Subband of each channel available for radio signal output) (S101).

In the parameter setting process, the output power correction apparatus 100 sets the number of power amplifiers for each channel, the number of capacitors, the variable resistor for reference voltage 107-1 and / or the variable resistor for peak voltage 105-1 The resistance value can be set. The parameters for each frequency channel may be different, thereby enabling dynamically adaptive power amplification and output for each frequency channel within a wide range of frequency bands.

The parameter setting process (S101) will be described in detail with reference to FIG.

The setting process of the parameter is performed at the initialization of the output power correction apparatus 100, and the parameter can be stored in the memory. Alternatively, the parameter setting process may be performed according to the user's input (input) or automatically during the booting process after power-on.

Thereafter, the output power correction apparatus 100 recognizes frequency channel information of an input signal to be transmitted as a radio signal (S103). For example, the controller 111 receives frequency channel information to encode an input signal transmitted from the baseband chipset through a control signal. The frequency channel information may be a frequency channel number and the frequency channel information may be written to a register or memory within the controller 111 that is accessible to the baseband chipset.

The output power correction apparatus 100 includes at least one power amplifier 101 corresponding to frequency channel information among a plurality of controllable power amplifiers 101 and one or more capacitors 103 corresponding to frequency channel information among a plurality of controllable capacitors 103 (S105).

For example, the controller 111 searches frequency channel-specific parameters stored in a memory according to received frequency channel information, determines a predetermined number of power amplifier parameters and a number of capacitor parameters corresponding to frequency channel information (see S101) do. The controller 111 selects at least one power amplifier 101 in the plurality of power amplifiers 101 according to the determined number of power amplifier parameters and one or more capacitors 103 according to the number of capacitors parameter And is selected by a plurality of capacitors (103). The controller 111 can select a series of power amplifiers 101 of the number of power amplifier parameters among the plurality of power amplifiers 101 and select a series of capacitors 103 of the number of capacitor parameters among the plurality of capacitors 103. [

Thereafter, the output power correction apparatus 100 amplifies the input signal (S107) by connecting the selected one or more capacitors 103 to the ground and activating the selected one or more power amplifiers 101. [ The controller 111 generates a cap enable signal corresponding to the selected one or more capacitors 103 and outputs it to a switch or the like connected to the capacitor 103 and outputs a power enable signal for activating the selected one or more power amplifiers 101 And outputs it to the selected power amplifier 101.

Accordingly, the output power correction apparatus 100 corrects or adapts the corresponding output power for each channel, thereby enabling efficient power amplification for each frequency channel.

4 is a diagram showing an exemplary concrete control flow of a process of setting parameters for each frequency channel. 4A shows a whole parameter setting process including a variable resistance setting, and FIG. 4B shows a test process using a power amplifier 101 and a capacitor 103 for parameter setting. 4B may be part of the process of FIG. 4A. The process of FIG. 4 shows a specific implementation example of the parameter setting process for each frequency channel of FIG. 3 and is performed before S103 of FIG. 4 is performed by the output power correcting apparatus 100 and preferably by the control of the controller 111 of the output power correcting apparatus 100. [

First, the output power correction apparatus 100 recognizes a frequency channel for parameter setting (S201). The control flow of FIG. 4 is performed for each frequency channel so that each parameter is set for all frequency channels within the wideband frequency band.

In order to recognize a frequency channel, the controller 111 receives a frequency channel identifier (information) from a baseband chipset or the like via a control signal, stores it in a register or a memory, and then transmits a parameter scan command And writing the command in the command register of the controller 111).

The controller 111 first sets the peak voltage variable resistor 105-1 to the reference resistance value (S203). The reference resistance value may be set to a constant size ratio with respect to the fixed resistor 105-3 for the peak voltage and may be three times of the fixed resistor 105-3 for the peak voltage, for example. With this reference resistance value setting, a peak voltage having a fixed ratio of magnitude to the fixed resistor can be output from the peak voltage detection circuit 105.

Further, the controller 111 sets the reference resistance variable resistor 107-1 to the reference resistance value (S205). The reference resistance value is set to a constant ratio size with respect to the fixed resistor 107-3 for the reference voltage. For example, the reference resistance value may be 3.2 times the fixed resistance or the like. With this reference resistance value setting, a reference voltage having a certain ratio size with respect to the fixed resistor can be output from the reference voltage generating circuit 107.

Then, the controller 111 sets the number of test power amplifiers to be tested for parameter setting (S207). For example, the controller 111 sets the number of reference power amplifiers preset in a memory or the like or pre-encoded in a program or the like as the number of test power amplifiers. The number of reference power amplifiers may be 10, for example, the number of power amplifiers 101 that are minimally activated among the plurality of power amplifiers 101 (36, etc.).

The controller 111 activates the power amplifier 101 corresponding to the number of test power amplifiers (S209). For example, the controller 111 generates and outputs a power enable signal of a series of (adjacent) power amplifiers 101 corresponding to the number of test power amplifiers among the plurality of power amplifiers 101, respectively. The selected power amplifiers 101 amplify the input signal (the signal encoded in the corresponding frequency channel) and output it as an output signal.

Further, the controller 111 sets the number of test capacitors (S211). For example, the controller 111 sets the number of reference capacitors pre-set in a memory or the like or pre-encoded in a program or the like as the number of test capacitors. The number of reference capacitors may be, for example, zero or one.

Thereafter, the controller 111 connects the capacitor 103 corresponding to the number of test capacitors among the plurality of capacitors 103 to the ground Gnd (S213). For example, the controller 111 generates and outputs a cap enable signal of a series of (adjacent) capacitors 103 corresponding to the number of test capacitors among the plurality of capacitors 103 (for example, 20) . The capacitor 103 thus selected is connected to the ground via a switch or the like.

Here, the processes of S207 and S209 and the processes of S211 and S213 may be performed independently, so that the subsequent relationship may be reversed or performed at the same time.

After setting the power amplifier 101 and the capacitor 103 to amplify the input signal, the peak voltage sensing circuit 105 senses the peak voltage of the output signal connected to the power amplifier 101 and the capacitor 103 (S215) do. This peak voltage has a voltage magnitude by the variable resistor 105-1 for peak voltage. The reference voltage generating circuit 107 generates a reference voltage. The generated reference voltage has a voltage magnitude proportional to the reference voltage variable resistor 107-1.

The comparator 109 compares the detected peak voltage with the generated reference voltage (S217) and outputs a comparison signal indicating the comparison result. For example, the comparator 109 compares the peak voltage with the reference voltage to output a Vcomp signal of logic '1' to the controller 111 when the peak voltage is high, and a Vcomp signal of logic '0' . Alternatively, the comparator 109 may output the opposite logic signal. The logic signal may be a digital signal or an analog signal recognized by the controller 111.

The controller 111 determines that the peak voltage satisfies a specified condition (for example, the peak voltage is larger than the reference voltage and the peak voltage is smaller than the reference voltage according to the design variant) The number of capacitors is matched and written in the memory (S219). For example, the controller 111 matches the number of test power amplifiers and the number of successful test capacitors to the current frequency channel under test and stores it in a memory or the like.

The controller 111 determines whether the test for all the capacitors is completed (S223). For example, the controller 111 may determine whether testing has been completed for all of the capacitors through a number of capacitors (e.g., 20, etc.) with the number of test capacitors.

If all of the capacitors 103 are not tested, the controller 111 increases the number of test capacitors (S225) and repeats S213 to S223. For example, the controller 111 may increase the number of test capacitors by one and then repeat.

If all the capacitors 103 have been tested, the controller 111 determines whether the test for all the power amplifiers has been completed (S227). For example, the controller 111 can determine whether the test for all the power amplifiers has been completed by determining whether the number of test power amplifiers is equal to the number of the plurality of power amplifiers (for example, 36, etc.) provided.

If all the power amplifiers 101 have not been tested, the controller 111 increases the number of test power amplifiers (S229) and repeats the steps S209 to S227. For example, the controller 111 may increment the number of test power amplifiers by one and then repeat.

5 and 6 show an example of simulation of an output signal in which an input signal is amplified and output through repetition of S209 to S217.

5 and 6 show the output signal of the output power correcting apparatus 100 simulated by the antenna side through the impedance matching circuit and the lower side waveforms of Figs. 5 and 6 show the simulated output waveform before the impedance matching circuit Represents an output signal of the output power correcting apparatus 100. Fig.

As shown in FIG. 5, it can be seen that the magnitude of the output signal varies depending on the number of activated power amplifiers 101 (the number of test power amplifiers). The waveform of FIG. 5 is an output signal when the number of power amplifiers 101 (PA_CELL) is sequentially increased from 10 (reference number) to 36 (total number). As can be seen from FIG. 5, as the number of power amplifiers 101 increases, the output increases in proportion to the number of outputs.

The diagram of FIG. 6 shows the output signal simulation results in a test for the total number of capacitors within the number (15 and 16) of specific power amplifiers 101. The waveform of FIG. 6 shows the output signal when the number of capacitors is sequentially increased from 1 to 20. 6, it is possible to amplify the maximum power of the output signal within a specific number of the number of power amplifiers 101 by a specific number of capacitors through the test.

5 and 6, an output power compensating apparatus 100 according to the present invention includes a plurality of power amplifiers 101 and a plurality of capacitors 103, To enable efficient power amplification and further to detect efficient (optimized or matched) power amplification on an arbitrary frequency channel and to enable the corresponding power amplification.

Referring again to FIG. 4, as the test for all the power amplifiers is completed, the controller 111 determines a common number of successive capacitors corresponding to the number of tested test power amplifiers (S231). For example, the controller 111 determines the number (s) of capacitors that are common (all) successful in all power amplifier numbers (e.g., 10 to 36). Alternatively, the controller 111 determines the number of commonly successful capacitors in a number of power amplifiers (e.g., 10 to 36 out of 10, etc.).

The controller 111 determines whether there is a common number of successive capacitors corresponding to the number of test power amplifiers (S233). If none of them exists, the controller 111 changes the reference voltage variable resistor 107-1 (S235) and repeats the steps S207 to S233.

For example, the controller 111 increases the reference voltage variable resistor 107-1 to a resistance value proportional to the resistance value of the reference voltage fixing resistor 107-3 (0.04 times or the like). Accordingly, the output value of the reference voltage can be increased at a constant rate.

If a test is made in the range of the variable resistors 107-1 for all the reference voltages with or without the number of success capacitors, the controller 111 performs the process of S237 and the following steps.

The controller 111 again determines the number of successive capacitors common to the plurality of test power amplifiers (S237). For example, the controller 111 determines the number (s) of capacitors that are successful in all power amplifier numbers (e.g., 10 to 36). Alternatively, the controller 111 determines the number of capacitors that succeeded in the number of power amplifiers (e.g., 10 to 36 out of 10, etc.). This process can be omitted depending on the design example.

The controller 111 determines whether there is a common number of successive capacitors corresponding to the number of test power amplifiers (S239). If none exists, the controller 111 changes the peak voltage variable resistor 105-1 (S241) and repeats the processes of S205 to S239.

For example, the controller 111 increases the resistance of the peak voltage variable resistor 105-1 to a resistance value proportional to the resistance value of the peak voltage fixed resistor 105-3 (0.04 times or the like). Thus, the output value of the peak voltage can be increased at a constant rate.

If so, the controller 111 determines various parameters to be set corresponding to the frequency channel at which the test is currently performed (S243) and stores it in the memory. For example, the controller 111 determines the number of capacitors parameters in a common number of successive capacitors. If there are several success capacitors, the number of successive capacitors corresponding to the specified condition (for example, the number closest to the middle number (10, etc.)) is determined as the number of capacitors.

In addition, the controller 111 determines the number of power amplifier parameters in the number of test power amplifiers matched to the number of successive capacitors. When there are a plurality of matched test power amplifiers, the controller 111 sets the number of test power amplifiers matching the specified condition (for example, the number closest to the intermediate number (18, etc., or the minimum number) .

Further, the controller 111 determines the variable resistance parameter for the peak voltage and the variable resistance parameter for the reference voltage. For example, the controller 111 may set the minimum value among the variable resistance values to the variable resistance parameter corresponding to the number of the succeeding capacitors. The steps S233 and S239 are configured to recognize the minimum resistance value. If the minimum resistance value is recognized, the test is not performed for the other variable resistance values. Otherwise, the test is performed for all the variable resistance values It may be deformed.

The controller 111 maps the capacitor number parameter, the number of power amplifiers parameter, the variable resistance parameter for peak voltage and / or the variable resistance parameter for reference voltage to the identifier (e.g., frequency channel number) of the frequency channel under test And outputs the test completion signal for the current frequency channel by using a baseband chipset or the like.

For example, the controller 111 may set the completion flag in a register or the like, and the baseband chipset may read the completion flag through the control signal and proceed with a test for parameter setting for another frequency channel.

Through the above process, the output power correction apparatus 100 sets the setting of the power amplifier 101, the capacitor 103, and the variable resistance value effective for all the frequency channels, and sets the parameters set at the time of signal output through the frequency channel So that the output signal can be amplified.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. The present invention is not limited to the drawings.

100: Output power compensation device
101: Power amplifier 103: Capacitor
105: Peak voltage sensing circuit
105-1: variable resistor for peak voltage 105-3: fixed resistor for peak voltage
107: Reference voltage generating circuit
107-1: variable resistor for reference voltage 107-3: fixed resistor for reference voltage
109: comparator 111: controller

Claims (11)

A plurality of power amplifiers each for power amplifying an input signal according to each power enable signal;
A plurality of capacitors coupled in parallel to the output signals of the plurality of power amplifiers and coupled to ground in accordance with respective cap enable signals;
A peak voltage sensing circuit for sensing a peak voltage of the output signal;
A comparator for comparing the peak voltage with a reference voltage; And
And a controller for previously determining a number of power amplifier parameters and a number of capacitors parameter for each frequency channel according to a comparison signal from the comparator and for determining a predetermined number of power amplifier parameters corresponding to a frequency channel of the frequency channel information of the input signal among the plurality of power amplifiers And outputting a power enable signal of at least one of the plurality of capacitors and a cap enable signal of at least one capacitor selected in accordance with a predetermined number of capacitor parameters corresponding to a frequency channel of frequency channel information of the input signal, And a controller for outputting a control signal,
Output power correction device. delete delete The method according to claim 1,
And a reference voltage generating circuit for generating a reference voltage,
Wherein the comparator compares a peak voltage from the peak voltage sense circuit with a reference voltage from the reference voltage generation circuit,
Output power correction device. The method according to claim 1,
The controller sequentially outputs a cap enable signal for connecting a sequentially increasing number of capacitors to a ground while outputting a power enable signal to a series of power amplifiers corresponding to the number of reference power amplifiers, and sequentially outputs a cap enable And a comparator for receiving a comparison signal from the comparator during the output of the signal, and setting the number of power amplifiers and the number of capacitors for each frequency channel according to the received comparison signals,
Output power correction device. 5. The method of claim 4,
Wherein the peak voltage sensing circuit includes a first variable resistor for adjusting the peak voltage,
Wherein the reference voltage generating circuit includes a second variable resistor for adjusting the reference voltage,
The controller sequentially outputs a cap enable signal for connecting a sequentially increasing number of capacitors to a ground while outputting a power enable signal to a series of power amplifiers corresponding to the number of reference power amplifiers, and sequentially outputs a cap enable Receiving a comparison signal from the comparator during the output of the signal and adjusting one or more variable resistances of the first variable resistor or the second variable resistor when all of the received comparison signals do not satisfy the specified condition, The number of power amplifiers and the number of capacitors are set for each frequency channel,
Output power correction device. Recognizing frequency channel information of an input signal;
Selecting one or more power amplifiers and one or more capacitors corresponding to the frequency channel information among a plurality of power amplifiers and a plurality of capacitors; And
And connecting the selected one or more capacitors to ground and activating one or more selected power amplifiers to amplify the input signal, the method comprising the steps of:
Before the recognition of the frequency channel information of the input signal,
(a) activating power amplifiers corresponding to a number of test power amplifiers determined from the number of reference power amplifiers;
(b) connecting a capacitor of a number of test capacitors determined from the number of reference capacitors to ground;
(c) sensing a peak voltage of an output signal coupled to the capacitor and the power amplifier;
(d) comparing the peak voltage with a reference voltage;
(e) recording the number of successive capacitors by matching the number of test power amplifiers when the peak voltage meets a specified condition according to the comparison; And
(f) increasing the number of test capacitors and repeating steps (c) to (e).
Output power correction method. 8. The method of claim 7,
Wherein the selecting comprises determining a predetermined number of power amplifier parameters and capacitor number parameters corresponding to a frequency channel according to frequency channel information of the input signal, selecting one or more power amplifiers according to the determined number of power amplifier parameters, Lt; RTI ID = 0.0 > a < / RTI >
Output power correction method. delete 8. The method of claim 7,
(g) increasing the number of test power amplifiers and repeating steps (b) to (f);
(h) determining a common number of successive capacitors corresponding to a plurality of test power amplifiers; And
(i) determining a power amplifier number parameter and a capacitor number parameter of a designated frequency channel from the number of one or more common successive capacitors and the corresponding number of test power amplifiers;
Output power correction method. 11. The method of claim 10,
If there is no common number of successive capacitors in step (h), (j) changing the value of the variable resistor to adjust the reference voltage or the peak voltage; And
(k) repeating the steps (a) to (h).
Output power correction method.

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