KR101940523B1 - Apparatus and method for warp scheduling - Google Patents

Abstract

The present invention relates to warp scheduling capable of increasing parallelism in processing an instruction. An operation method of an electronic device comprises the steps of: determining an instruction causing latency above a threshold value; assigning a priority to warp corresponding to the determined instruction; and executing the instruction according to the priority of the warp.

Description

[0001] APPARATUS AND METHOD FOR WARP SCHEDULING [0002]

The present invention relates to warp scheduling and, more particularly, to warp scheduling based on latency of instructions to a warp.

Graphics processing units (GPUs) are widely used to handle general workloads as well as graphics workloads. GPUs can provide much higher performance than central processing units (CPUs) for parallel applications. In particular, the computing power of a GPU can be achieved using multiple streaming multiprocessors (SMs) and gigabytes of high memory bandwidth. As a result, the GPU has become a computing platform for handling general-purpose workloads and has received increasing attention in research.

Because the GPU architecture for general-purpose computing is designed with high-throughput focus, a non-speculative on-demand processor pipeline is a compromise for many computing units. The GPU supports fast context switching to overcome the overhead of long latency operations such as global load, which is one important issue, to reserve as many concurrent warps as possible to hiding this latency. In other words, you can change immediately whenever warp execution is interrupted, and you can swap another warp immediately, increasing resource utilization without penalty. To ensure that the pipeline continues to be active under such long delay time operations, the warp scheduler can execute the next instruction by selecting a ready warp in the warp pool of each cycle. In theory, the GPU can achieve high thread level parallelism (TLP) in this way, but the pipeline still suffers due to the long inactivity time that lowers the utilization of hardware resources.

The warp scheduler can play a key role in increasing the utilization of hardware resources in the GPU. A commonly used round robin (RR) warp reservation policy can assign the same priority to all warps. However, previous studies have shown that the long memory fetch latency caused by off-chip DRAM bandwidth, which is limited by traditional RR scheduling, is not concealed and the GPU SM utilization is greatly reduced. However, these RR schemes can waste warp / thread parallelism to hide short delay time operations. On the other hand, if all the warps execute a long delay time operation, the RR scheduling can not hide such a delay time, which can lead to serious performance degradation.

[Patent Document 1] Korean Patent No. 10-1236562

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and it is an object of the present invention to provide an apparatus and method for warp scheduling.

It is also an object of the present invention to provide an apparatus and method for warp scheduling based on the latency of an instruction for a warp.

The objects of the present invention are not limited to the above-mentioned objects, and other objects not mentioned can be clearly understood from the following description.

According to an aspect of the present invention, there is provided a method of operating an electronic device, including: determining an instruction to generate a latency of a threshold value or more; Assigning a priority to a warp corresponding to the determined instruction; And executing the instruction according to the priority of the warp.

In an embodiment, determining the instruction comprises: determining a first instruction to generate a delay time greater than or equal to the threshold value; And determining a second instruction to generate a delay time that is less than the threshold value.

In an embodiment, the first priority of the warp corresponding to the first instruction may be higher than the second priority of the warp corresponding to the second instruction.

In an embodiment, the step of executing the instruction comprises: performing the first instruction according to the first priority and the second priority; And performing the second instruction after performing the first instruction.

In an embodiment, a warp corresponding to the first instruction is included in a guiding pool, and a warp corresponding to the second instruction may be included in a filling pool.

In an embodiment, the electronic device determines an instruction that causes a latency above a threshold value, assigns a priority to a warp corresponding to the determined instruction, and updates the instruction according to the priority of the warp And may include a running warp scheduler.

In an embodiment, the warp scheduler may determine a first instruction to generate a delay time that is greater than or equal to the threshold value, and determine a second instruction to generate a delay time that is less than the threshold value.

In an embodiment, the first priority of the warp corresponding to the first instruction may be higher than the second priority of the warp corresponding to the second instruction.

In an embodiment, the warp scheduler may perform the first instruction in accordance with the first priority and the second priority, and may perform the second instruction after performing the first instruction.

In an embodiment, a warp corresponding to the first instruction is included in a guiding pool, and a warp corresponding to the second instruction may be included in a filling pool.

The above and other objects, features and advantages of the present invention will be more apparent from the following detailed description taken in conjunction with the accompanying drawings, in which: FIG.

The present invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the invention to those skilled in the art. Quot; a "general inventor") to fully disclose the scope of the invention.

According to an embodiment of the present invention, the parallelism of the instruction processing can be improved by arranging the instructions in units of warp so as to preferentially execute the instructions that generate the long delay time

The effects of the present invention are not limited to the effects described above, and the potential effects expected by the technical features of the present invention can be clearly understood from the following description.

1 is a functional block diagram of a basic GPU architecture according to an embodiment of the present invention.
2 is a diagram illustrating an example of warp scheduling according to an embodiment of the present invention.
3 is a functional block diagram of an electronic device according to an embodiment of the present invention.
4 is a functional block diagram of a warp issuing unit according to an embodiment of the present invention.
5 is a flowchart of a method of operating a warp scheduler according to an embodiment of the present invention.
6 is a diagram illustrating pseudo code of a warp scheduler according to an embodiment of the present invention.
7 is a graph of performance of a warp scheduler according to an embodiment of the present invention.
8 is a miss ratio graph of the L1 data cache of the warp scheduler according to an embodiment of the present invention.
9 is a graph showing a miss ratio of the L2 cache of the warp scheduler according to an exemplary embodiment of the present invention.
10 is a cache access graph of a warp scheduler according to an embodiment of the present invention.
11 is a stall cycle graph of a warp scheduler according to an embodiment of the present invention.
12 is another stall cycle graph according to an embodiment of the present invention.
13 is another performance graph of a warp scheduler according to an embodiment of the present invention.

While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will herein be described in detail.

Various features of the invention disclosed in the claims may be better understood in view of the drawings and detailed description. The devices, methods, processes and various embodiments disclosed in the specification are provided for illustration. The disclosed structural and functional features are intended to enable a person skilled in the art to practice various embodiments and are not intended to limit the scope of the invention. The terms and phrases disclosed are intended to facilitate understanding of the various features of the disclosed invention and are not intended to limit the scope of the invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

Hereinafter, a description will be given of warp scheduling based on a latency of an instruction for a warp according to an embodiment of the present invention. Here, the warp is a set of 32 threads, which can mean a basic unit for performing operations in a graphics processing unit (GPU).

1 is a functional block diagram of a basic GPU architecture according to an embodiment of the present invention.

Referring to FIG. 1, the GPU 100 may include a streaming multiprocessor (SM) 110, an interconnect network 120, a memory controller 130, and a GDDR RAM 140.

In one embodiment, the GPU 100 may include multiple SMs 100. Each SM 110 may typically comprise 8 to 32 single instruction multiple thread (SIMT) lanes. For example, the GPU 100 may include 15 SMs 110 each having 32 SIMT widths, i.e., 32 instructions per cycle (IPC). One instruction from each of the 32 threads can be issued collectively. Every SIMT lane runs in a scalar register to execute a separate thread and process it in the lock phase. In addition, the SM 110 may include an L1 data cache, a texture cache, and a constant cache.

The interconnect network 120 may be coupled to the SM 100. The SM 110 is a multithreaded, pipelined and primarily register file (i.e., an operand collector), an execution unit (Arithmetic Logic Unit), a Floating Point Unit (SFU) / special function units (SFU) And a load / store unit (LD (load) / ST (store)). GPU 100 may include multiple levels of memory hierarchy. To support parallel computing, the GPU 100 may provide a vast on-chip register file per SM 110 to accommodate multiple threads. On-chip storage can be partitioned into special-purpose caches such as L1 data cache, read-only texture, constant cache, and low-latency shared memory. Depending on the destination of the data, the memory request may be transferred to the corresponding cache memory. The dedicated L1 data cache of each SM 110 has a short latency and is accessible to all threads in a cooperative thread array (CTA). Each memory controller is associated with a shared L2 cache bank slice with a memory controller and can be defined as a memory partition. Global memory (also known as device memory) is located off-chip with long latency and is accessible by all thread blocks in the grid.

With a new parallel programming model such as CUDA and OpenCL, GPU (general purpose computing on graphics processing units) applications can be implemented in a hierarchical structure. At the top level, the kernel can implement a specific module of an application. Threads in the kernel can be grouped into CTAs or thread blocks (TBs). This is a concept that puts all synchronization and barrier primitives between warp threads and helps the underlying hardware to execute the CTA in any order to maximize throughput. In turn, each CTA can be subdivided into warps, which typically include 32 sibling threads. Parallel kernel calls can be allowed on the same or on multiple GPUs. If your application contains multiple CUDA streams, multiple kernels can run simultaneously. The SM architecture is based on a SIMT execution model that executes threads in a warp, so instruction fetch and decode overhead can be redeemed.

To be efficient, thread scheduling can be performed as a multi-step process. Initially, the kernel of the GPGPU application is run on the GPU, and the global CTA scheduler can allocate the CTA of the started kernel to all available SMs. In this operation, the CTA allocation can be performed in a round robin (RR) manner. GPU 100 may utilize computational resources more efficiently through fine-grained multi-threaded (FGMT) and may assign one or more CTAs to SM 110. However, the number of CTAs that can be executed simultaneously in the SM 110 may be limited by hardware resources. That is, if the SM 110 can execute multiple CTAs with sufficient CTAs, the CTA allocations may continue until the maximum number is reached. After CTA allocation, the warp associated with the initiated CTA is scheduled as a SIMT lane of the corresponding SM (110). A number of warp schedulers may be used, such as loose round-robin (LRR), two-level scheduling, and greedy-then-oldest (GTO).

In one embodiment, if there is no desired data in the register file, the data needed to access the local memory and perform the instruction may be requested. If a data request (or memory request) in the local memory fails, the data request may be requested to access the GDDR RAM 140. In this case, the data request to access the GDDR RAM 140 may be processed by the memory controller 130.

2 is a diagram illustrating an example of warp scheduling according to an embodiment of the present invention.

Referring to FIG. 2, there are six warps W1, ..., W6 running concurrently on the SM, each of which can execute an instruction, which includes memory and computation, Can be classified into two types of operations. W1, W3, W5, and W6 execute commands in the same order as mem-> mem-> compt-> mem, but W2 and W4 can execute commands in the same order as compt-> compt-> mem-> mem. In general, calculation operations generally have a short latency, but a memory operation can have a long delay time in case of a cache miss and a short delay time in case of a cache hit. Therefore, it can be assumed that the delay time of the memory operation hitting in the cache memory is slightly longer than the delay time of the calculation operation. In this case, the delay time of the calculation operation and the delay time of the memory operation of the cache hit can be confirmed in Fig. If the memory operation is missed in the cache memory, the requested data can be fetched from the lower memory. As a result, a much longer delay time may be required for this type of operation as compared to the calculation operation.

In one embodiment, the GPU can perform rapid context switching. That is, the activation of the pipeline can be maintained by immediately moving the access priority for hardware resources from one warp to another.

In the case of the conventional RR algorithm, the warp can be scheduled in the RR scheme. That is, when the currently executed warp is stopped, the predefined warp can be selected to execute the next command regardless of the state of the warp. As a result, the idle time may become longer and the performance may be seriously degraded.

In the conventional loose round robin (LRR) algorithm, the scheduling order of the warp is more flexible, so that a ready warp can be replaced immediately if a predefined warp is not prepared. This basically solves the problem of the RR scheme and can significantly increase the use of hardware resources.

Using the conventional GTO algorithm, the hardware resources can maintain the data locality (internal warp data locality) and can be utilized effectively.

However, the above-described method does not maintain inter-warp locality, and it can be confirmed that parallel processing that overlaps a long delay time is not sufficient. In particular, since all the calculation instructions are consumed in each calculation area, a stall cycle occurs when the scheduler can not find the preparation instruction, so that all calculation instructions in each calculation area may be exhausted. This problem can be put into an inactive state because there is no warp that is not stalled to allocate to the SM.

A solution to the above-described problem may be provided in accordance with various embodiments of the present invention to enhance the ability to hide the long latency for existing warp schedulers of the GPU. If you have a sufficient amount of concurrent threads, you can hide the long latency with the above scheduling policy as well as the computational characteristics, as well as the use of parallel processing. The warp scheduling according to various embodiments of the present invention may provide a solution for storing available TLPs and for hiding several long latency operations. In a GPGPU application, each warp can perform a few simple computations and / or a small number of global loads separated by a shared memory store before reaching a real computing area with a short latency operation. When these global loads are close to each other, changing the priority for the stall for each long delay time load can result in several small calculation areas that are insufficient to overlap with the subsequent global load. Thus, a different approach to TLP savings can be made by continuously reserving warps that perform long latency operations. If the long delay time is closely located, the other warp may be used to overlap the warp before overlapping the remainder of the long delay time. This approach can highly utilize the powerful parallelism of the GPU and avoids the problem of insufficient TLP that overlaps the long latency in the future.

Since W1, W3, W5, and W6 execute a long delay time operation, W2 and W4 are prioritized and can be reserved in an RR manner. The long delay time due to the former warp may overlap with the latter warp. If these warps can not hide the delay time from each other, W2 and W4 can perform a short delay time operation scheduled to overlap with the rest of the previous long delay time. With this strategy, the stall period still occurs, but the stall period may be shorter than the warp scheduling technique described above. That is, a solution according to various embodiments of the present invention can provide the best throughput. Thus, this can be an effective way of concealing long delays because it saves parallel processing as well as SM idle time for the required amount of time. Higher utilization of hardware resources can improve the overall performance of the GPU.

3 is a diagram illustrating an electronic device 300 in accordance with an embodiment of the present invention. In one embodiment, the electronic device 300 may include a shader core.

3, electronic device 300 includes a fetch unit 310, an I-cache unit 320, a decoding unit 330, an I-buffer unit 340, a scoreboard ) 350, a warp issue unit 360, a register unit 370, an ALU 380, and a MEM 390. [

The fetch unit 310 may select a program counter (PC) and an empty slot in the I-buffer 340 for warp every cycle. The instruction may be decoded through the decoding unit 330 before being placed in the empty slot of the I-buffer 340 after being fetched from the I-cache 320. [ The instruction may wait in the I-buffer 340 until a ready bit is set by the scoreboard 350, i.e., until the previous instruction from this warp is completed.

Warp issue unit 360 may select a warp based on a particular scheduling algorithm and execute it with instructions prepared in I-buffer 340. Thereafter, the slot in the I-buffer 340 corresponding to the issued instruction may be marked as invalid to signal the fetch unit 310 to fetch the next instruction for this warp. The issued instruction may be executed in ALU 380 or MEM 390, depending on the type of instruction, based on the operand from register unit 370. [ Thus, the warp scheduling algorithm according to various embodiments of the present invention may be implemented in warp issue unit 360. [ That is, the warp issuing unit 360 may operate as a warp scheduler of the electronic device 300.

4 is a functional block diagram of the warp issuing unit 460 according to an embodiment of the present invention. In one embodiment, the warp issue unit 460 may be a detailed structure of the warp issue unit 360 of FIG.

Referring to FIG. 4, a warp may be stored in a warp pool prior to scheduling. Warp issue unit 460 may perform the sort process to classify the warp according to the nature of the next instruction. Through the classification process, an entry of the I-buffer 340 corresponding to each warp can be examined to identify the type of instruction for which the warp will be issued. Scoreboard 350, on the other hand, can be used to predict whether the next issued instruction will require a long delay time. After the classification process, all warps, except the last issued warp, may be stored in either a guiding pool or a filling pool. The guiding pool may include a warp where a long latency load operation is issued at the next scheduling time. The filling pool may include a warp in which a short delay load operation is issued. If the next command this warp executes changes its type, you can move the warp of a specific pool to another pool. Generally, the guiding pool's warp may be higher than the filling pool's warp. If the warping of both the guiding pool and the pooling pool is not issued, the last issued warp may be scheduled.

The warp scheduler according to various embodiments of the present invention may implement very simple hardware logic. The main computational overhead can arise from the classification process, including access to I-buffers and scoreboards. While it may be delayed to sort the warp and push it into the warp pool, this operation may be performed with a simple parallel operation and may have little effect on the system. In terms of storage overhead, additional repositories may be required to implement separate warp pools.

5 is a flow diagram of a method of operating an electronic device 500 in accordance with an embodiment of the present invention. In one embodiment, the electronic device 500 may include a shader core.

Referring to FIG. 5, in step S501, the electronic device 500 may determine an instruction that causes a latency of more than a threshold value. In one embodiment, the electronic device 500 may determine a first instruction to generate a delay time that is above a threshold value. In addition, the electronic device 500 may determine a second instruction to generate a delay time that is less than a threshold value.

In step S503, the electronic device 500 may assign a priority to the warp corresponding to the determined command. In one embodiment, the first priority of the warp corresponding to the first instruction may be higher than the second priority of the warp corresponding to the second instruction.

In step S505, the electronic device 500 may execute an instruction in accordance with the priority of the warp. In one embodiment, the electronic device 500 may perform a first instruction in accordance with a first priority and a second priority. In addition, the electronic device 500 may perform a first instruction and then a second instruction.

6 is a diagram illustrating pseudo code of a warp scheduler according to an embodiment of the present invention.

Referring to FIG. 6, the pseudo code of the warp scheduler according to various embodiments of the present invention may include an alignment step and a scheduling step.

In the alignment step, all warps can be examined and pushed to either the guiding pool or the peeling pool. If the warp executes a long delay load at the next scheduling time, it can be pushed to the guiding pool, or it can be pushed to the fill pool. The operation may be implemented using a warp ID.

In the scheduling step, since the warp from the guiding pool causes a long delay time, the warp scheduler according to various embodiments of the present invention gives the warp from the guiding pool a higher priority than the warp from the filling pool . Guiding warps are scheduled in the LRR scheme and can be prioritized until the system can no longer issue guiding warp types. For example, if the guiding warp is not ready, for example if the next command is not buffered, the warp from the filling pool can be swapped immediately to overlap the long latency caused by the previous guiding warp. The filling warp may also be scheduled in the LRR manner until any guiding warp is ready for scheduling. If warp is not available for any reason, the last issued warp may be issued. In a filling pool, a warp with a ready instruction of an I-buffer may have a higher priority than another filling warp. The warp pool's warp can move to another pool. I-buffers can be accessed using warp IDs. The return result may be the type of the instruction (opcode) and the operand required to execute the corresponding instruction of the warp ID. Likewise, scoreboards can be accessed via warp IDs. The access result of the I-buffer and the scoreboard can be used as information for predicting whether or not the next command of the warp is a long latency load operation.

7 is a graph of performance of a warp scheduler according to an embodiment of the present invention.

Referring to FIG. 7, the effect of the warp scheduling on the GPU can be confirmed. All results of warp scheduling according to various techniques can be normalized to a basic GPU using the LRR policy. Performance improvements of up to 19.6% for all applications used in this operation are not slowing down the application. 23.1%, 61.1% and 52.6%, respectively, in memory intensive applications such as MUM, EPP and SAOP. Especially in the case of SP, performance is less concentrated in memory than other applications, but performance can be improved by 101.3%.

Comparing the warp scheduler according to various embodiments of the present invention with a warp scheduler such as two-level and GTO, the warp is classified into an active set and a pending set according to the delay time. Level scheduler slightly improves GPU performance by 0.5% below average.

On the other hand, the GTO scheduler can achieve an excellent result of 15.8% on average. Overall, previous studies show that applications show better performance than RR warp scheduling policies when they show data areas within a high level of warp. Once the results are normalized to 2-level and GTO, the warp scheduler according to various embodiments of the present invention can see an average performance improvement of 18.5% and 5.6%, respectively.

8 is a miss ratio graph of the L1 data cache of the warp scheduler according to an embodiment of the present invention.

Referring to FIG. 8, the miss rate of the L1 data cache can be confirmed when the warp scheduler is applied. For example, in comparison to the baseline, the warp scheduling according to various embodiments of the present invention can reduce the average cache miss ratio of 8.2%. This means that warp scheduling according to various embodiments of the present invention can maintain data locality, but it has little effect on the number of cache accesses to the L1 data cache. A reduction in the L1 data cache miss ratio can be an important contributor to overall performance improvement. For example, the L1 data cache miss ratio of MIT, EPP, and SAOP is significantly improved to 14.8%, 38.3%, and 37.3%, respectively, such that these applications make significant use of warp scheduling in terms of performance in various embodiments of the present invention The reason can be explained. However, the cache miss ratio is not the only factor that affects performance because the performance improvement of HW and MS is small, but these applications can confirm that the cache miss ratio is low. A cache-unfriendly application, SP, does not reduce the rate of L1 data cache misses, but it does show excellent performance.

9 is a graph showing a miss ratio of the L2 cache of the warp scheduler according to an exemplary embodiment of the present invention.

Referring to FIG. 9, in the case of the L2 cache, the warp scheduler according to various embodiments of the present invention can confirm that the application has various effects. It can be seen that cache access to the L2 cache for these applications is significantly reduced.

10 is a cache access graph of a warp scheduler according to an embodiment of the present invention.

Referring to FIG. 10, it can be seen that most applications have a lower or equal L2 cache miss ratio compared to the baseline, but some applications have a higher L2 cache miss ratio. On average, it can be seen that the warp scheduler according to various embodiments of the present invention generates 2.8% more cache misses in the L2 cache. In the GPU architecture, because the cache size of the L2 cache is generally large, the miss ratio of the L2 cache is smaller than the miss ratio of the L1 data cache. Also, because the L2 cache is an off-chip memory, it can have a weak impact on performance when compared to the L1 data cache. Even if the ratio of L2 cache misses of Mum, EPP and SAOP is greatly increased, there is no performance degradation.

11 is a stall cycle graph of a warp scheduler according to an embodiment of the present invention.

Referring to FIG. 11, more pressure may be placed on the NoC and memory system if a warp that can perform a long delay operation is scheduled to be closely spaced. The memory system of the GPU is not negatively affected by the warp scheduler according to various embodiments of the present invention because it provides high bandwidth. The influence of the warp scheduler according to various embodiments of the present invention on the NoC bandwidth can be confirmed. Since NoC is responsible for breaking memory requests for global loads with data from lower memory, such as L2 cache and main memory, GPU performance can be degraded if NoC is interrupted.

12 is another stall cycle graph according to an embodiment of the present invention.

Referring to FIG. 12, the number of stall cycles in a memory channel due to NoC congestion can be confirmed when a warp scheduler according to various embodiments of the present invention is applied. It can be seen that, compared to the baseline, most applications exhibit a lower number of stall cycles or the same number of stall cycles. The warp scheduler according to various embodiments of the present invention slightly increases the NoC stall cycle only for SP and NW but does not identify a performance penalty in the application because it significantly reduces the pipeline stall in the memory stage for the application .

13 is another performance graph of a warp scheduler according to an embodiment of the present invention.

Referring to FIG. 13, it can be seen that the warp scheduling according to various embodiments of the present invention and the performance of the prior art are normalized to the baseline. Warp scheduling according to various embodiments of the present invention may be compared to cache management techniques for the GPU.

One of the cache management techniques may consist of two separate components: request reordering and cache bypassing. Therefore, since additional storage (e.g., SRAM 3 KB) is required to implement order reordering, warp scheduling according to various embodiments of the present invention can be compared to cache bypassing components. The cache bypass scheme may be selected in a bypass-on-associativity-stall manner. The MRPB bypassing technique can outperform the baseline by an average of 7.6%.

In the case of decoupled LIDs intended for bypassing requests with low reuse frequency and long reuse distance, the bypassing technique is performed only in cache-incompatible applications such as SP and NW, and has a small performance impact on other applications I can go crazy. This technology can provide an average performance improvement of 9.8%. Compared to the two techniques described above, the warp scheduler according to various embodiments of the present invention can outperform more applications and improve average performance.

As described above, the warp scheduling policy according to various embodiments of the present invention can alleviate the disadvantage of the basic scheduling policy (referred to as L3WS). A method of effectively utilizing warp parallelism in accordance with various embodiments of the present invention has been described to improve the overall performance of the GPU. The warp scheduler according to various embodiments of the present invention can use the TLP more accurately by classifying the warp into separate warp pools depending on the nature of the instruction to be issued to the warp. Warps that perform long latency operations are designated with high priority and can be classified as guiding warps. On the other hand, the warp that performs the short delay operation has a low priority and can be scheduled to overlap the delay time caused by the guiding warp. Thereby, the warp scheduler according to various embodiments of the present invention can mitigate TLP shortage problems and improve system performance.

An instruction that generates a long delay time from the scoreboard can be predicted to separately classify the memory access instruction that generates the long delay time. The command can be stored in a separate queue structure and executed first. The parallelism of the instruction processing can be improved by arranging the instructions in units of warp so that the instruction that generates the long delay time can be preferentially executed.

The foregoing description is merely illustrative of the technical idea of the present invention and various changes and modifications may be made by those skilled in the art without departing from the essential characteristics of the present invention.

Accordingly, the embodiments disclosed herein are for the purpose of describing, not limiting, the technical spirit of the present invention, and the scope of the present invention is not limited by these embodiments.

The scope of protection of the present invention should be construed according to the claims, and all technical ideas within the scope of the same should be understood as being included in the scope of the present invention.

100: GPU
110: SM
120: Interconnect Network
130: Memory controller
140: GDDR RAM
300: electronic device
310: Fetch unit
320: I-cache unit
330: decoding unit
340: I-buffer unit
350: Scoreboard
360: warp issue unit
370: register unit
380: ALU
390: MEM
460: warp issuing unit

Claims (10)

A method of operating an electronic device,
Determining an instruction to generate a latency of a threshold value or more based on operand related information of a scoreboard and an instruction type;
Assigning a priority to a warp corresponding to the determined instruction; And
Executing the instruction according to the priority of the warp;
≪ / RTI >
The method according to claim 1,
Wherein determining the instruction comprises:
Determining a first instruction to generate a delay time greater than or equal to the threshold value; And
Determining a second instruction to generate a delay time that is less than the threshold value;
≪ / RTI >
3. The method of claim 2,
Wherein the first priority of the warp corresponding to the first instruction is higher than the second priority of the warp corresponding to the second instruction.
The method of claim 3,
Wherein executing the instruction comprises:
Performing the first instruction according to the first priority and the second priority; And
Performing the second instruction after performing the first instruction;
≪ / RTI >
The method of claim 3,
The warp corresponding to the first instruction is included in a guiding pool,
Wherein the warp corresponding to the second instruction is included in a filling pool.
In an electronic device,
Determining an instruction to generate a latency of a threshold value or more based on operand related information of a scoreboard and an instruction type,
Assign a priority to the warp corresponding to the determined instruction,
And a warp scheduler that executes the instruction in accordance with the priority of the warp.
The method according to claim 6,
The warp scheduler includes:
Determining a first instruction to generate a delay time greater than or equal to the threshold value,
And to generate a delay time less than the threshold value.
8. The method of claim 7,
Wherein the first priority of the warp corresponding to the first instruction is higher than the second priority of the warp corresponding to the second instruction.
9. The method of claim 8,
The warp scheduler includes:
Performing the first instruction according to the first priority and the second priority,
And performs the second instruction after performing the first instruction.
9. The method of claim 8,
The warp corresponding to the first instruction is included in a guiding pool,
Wherein the warp corresponding to the second instruction is included in a filling pool.

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