KR101926862B1 - Variable resistor and resistance type memory device - Google Patents

Abstract

The present invention relates to a variable resistance body and a resistive memory element. A resistive memory device according to an embodiment of the present invention includes a resistive memory including an array of a plurality of memory cells arranged at intersections of first wirings and second wirings extending to intersect with the first wirings, Wherein each of the plurality of memory cells comprises: an anode electrode; A first dielectric layer formed on the anode electrode, the first dielectric layer having the first dielectric constant; A second dielectric layer formed on the first dielectric layer, the second dielectric layer having a second dielectric constant smaller than the first dielectric constant; A cathode electrode formed on the second dielectric layer; And a charge trap layer between the first dielectric layer and the second dielectric layer, wherein bit information is added to a resistance value of the memory cell based on a magnitude of a trap charge of a charge trap layer induced by applying a voltage signal to each memory cell .

Description

[0001] The present invention relates to a variable resistor and a resistive memory device,

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a variable resistor and a resistive memory device.

Recently, the demand for portable digital applications such as digital cameras, MP3 players, personal digital assistants (PDAs), and mobile phones has increased, and the variable resistance memory market is rapidly expanding. As a programmable variable resistance memory element, a flash memory is typical. Flash memory devices use a single transistor memory cell that is highly integrated, highly reliable, and low in power consumption. Typically, the single transistor memory cell is a field effect transistor with a floating gate.

As a disadvantage of the flash memory device having such a floating gate, there is a long recording time for storing a charge in the floating gate, and a high electric field is applied to the gate insulating film to reduce the reliability and short life due to dielectric breakdown of the gate insulating film .

SUMMARY OF THE INVENTION It is an object of the present invention to provide a variable resistor which can easily adjust the conductance.

Another object of the present invention is to provide a resistive memory device which achieves high integration while improving programming speed compared to a flash memory, and improving reliability and lifetime.

According to an aspect of the present invention, there is provided an organic light emitting display comprising: an anode; A first dielectric layer formed on the anode electrode, the first dielectric layer having the first dielectric constant; A second dielectric layer formed on the first dielectric layer, the second dielectric layer having a second dielectric constant smaller than the first dielectric constant; A cathode electrode formed on the second dielectric layer; And a charge trap layer between the first dielectric layer and the second dielectric layer.

In one embodiment, the potential barrier between the first dielectric layer and the anode electrode may be greater than the potential barrier between the second dielectric layer and the cathode electrode. The thickness of the first dielectric layer may be greater than the thickness of the second dielectric layer.

The charge trap layer may be the interface layer itself of the first dielectric layer and the second dielectric layer. In another embodiment, the charge trap layer may comprise a plasma damage layer, a defect surface layer formed by heat treatment of the reactive gas atmosphere, and / or an impurity doped layer, or a combination of two or more thereof. In yet another embodiment, the charge trap layer may comprise any of nano-dots and nanosheets or a combination thereof. In yet another embodiment, the charge trap layer may comprise any one or combination of metal, metal oxide, metal nitride, and semiconductor layers.

According to another aspect of the present invention, there is provided a semiconductor memory device including an array of a plurality of memory cells arranged at intersections of first wirings and second wirings extending to intersect with the first wirings, A resistive memory element is provided. Wherein each of the plurality of memory cells comprises: an anode electrode; A first dielectric layer formed on the anode electrode, the first dielectric layer having the first dielectric constant; A second dielectric layer formed on the first dielectric layer, the second dielectric layer having a second dielectric constant smaller than the first dielectric constant; A cathode electrode formed on the second dielectric layer; And a charge trap layer between the first dielectric layer and the second dielectric layer, wherein bit information is added to a resistance value of the memory cell based on a magnitude of a trap charge of a charge trap layer induced by applying a voltage signal to each memory cell .

In some embodiments, the potential barrier between the first dielectric layer and the anode electrode may be greater than the potential barrier between the second dielectric layer and the cathode electrode. The thickness of the first dielectric layer may be greater than the thickness of the second dielectric layer.

The charge trap layer may be the interface layer itself of the first dielectric layer and the second dielectric layer. The charge trap layer may include any one of a plasma damage layer, a defect surface layer formed by heat treatment of a reactive gas atmosphere, and an impurity doped layer or a combination of two or more thereof. In another embodiment, the charge trap layer may comprise either nano-dots or nanosheets, or a combination thereof. In yet another embodiment, the charge trap layer may comprise any one or combination of metal oxide, metal nitride, and semiconductor layers.

Wherein at least one of the first and second dielectric layers is SiO ₂ . _{Si 3 N 4, Al 2 O} 3, Ta 2 O 5, HfO 2, TiO 2, Y 2 O 3, La 2 O 3, ZrO 2, SrTiO 3, BaTiO 3, PbTiO 3, Pb (Zr, Ti) O ₃ , (Hf, Zr) O ₂ , (Ba, Sr) TiO ₃ , SrBi ₂ Ta ₂ O ₉ , KxWO ₃ and Bi ₄ Ti ₃ O ₁₂ Or the like. Wherein at least one of the anode electrode and the cathode electrode is formed of at least one of platinum (Pt), tungsten (W), gold (Au), platinum (Pt), palladium (Pd), rhodium (Rh), iridium (Ir) ), Tantalum (Ta), molybdenum (Mo), chromium (Cr), vanadium (V), titanium (Ti), aluminum (Al), copper (Cu), silver (Ag) A conductive nitride of a metal, and a conductive oxide of these metals, or a combination thereof.

Either the first wiring or the second wiring may be a word line and the other may be a bit line.

According to an embodiment of the present invention, a variable resistance body having a self-rectifying property by a lamination structure of dielectric layers having different dielectric constants and a resistance value varying according to the size and / or the type of charge trapped in the charge trap layer Can be provided.

According to another embodiment of the present invention, a memory cell including a charge trap layer between the first dielectric layer and the second dielectric layer having different dielectric constants has a self-rectifying characteristic without a separate steering element, And a resistive memory element having nonvolatility can be provided by the resistance value of the memory cell due to the size of the trap charge of the charge trap layer.

FIG. 1A is an equivalent circuit diagram of a memory cell shown in FIG. 1A, and FIG. 1C is a cross-sectional view illustrating a memory cell according to an embodiment of the present invention. Grams.
FIGS. 2A and 2B are energy band diagrams for explaining the rectifying characteristics of a memory cell according to an embodiment of the present invention, and FIG. 2C is an energy band diagram for explaining a resistance change when charges are trapped.
FIGS. 3A and 3B are graphs showing the relationship between voltage and current for driving a memory cell according to an embodiment of the present invention. FIG.
4 is a cross-sectional view illustrating a memory device according to another embodiment of the present invention.
5 is a block diagram illustrating a memory device according to one embodiment of the present invention.
Figure 6 is a block diagram illustrating an electronic system including resistive memory elements in accordance with one embodiment of the present invention.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

The embodiments of the present invention are described in order to more fully explain the present invention to those skilled in the art, and the following embodiments may be modified into various other forms, It is not limited to the embodiment. Rather, these embodiments are provided so that this disclosure will be more faithful and complete, and will fully convey the scope of the invention to those skilled in the art.

Like numbers refer to like elements in the drawings. Also, as used herein, the term " and / or " includes any and all combinations of any of the listed items.

The terms used herein are used to illustrate the embodiments and are not intended to limit the scope of the invention. Also, although described in the singular, unless the context clearly indicates a singular form, the singular forms may include plural forms. Also, the terms "comprise" and / or "comprising" used herein should be interpreted as referring to the presence of stated shapes, numbers, steps, operations, elements, elements and / And does not exclude the presence or addition of other features, numbers, operations, elements, elements, and / or groups.

Reference herein to a layer formed " on " a substrate or other layer refers to a layer formed directly on top of the substrate or other layer, or may be formed on intermediate or intermediate layers formed on the substrate or other layer Layer. ≪ / RTI > It will also be appreciated by those skilled in the art that structures or shapes that are " adjacent " to other features may have portions that overlap or are disposed below the adjacent features.

As used herein, the terms "below," "above," "upper," "lower," "horizontal," or " May be used to describe the relationship of one constituent member, layer or regions with other constituent members, layers or regions, as shown in the Figures. It is to be understood that these terms encompass not only the directions indicated in the Figures but also the other directions of the devices.

In the following, embodiments of the present invention will be described with reference to cross-sectional views schematically illustrating ideal embodiments (and intermediate structures) of the present invention. In these figures, for example, the size and shape of the members may be exaggerated for convenience and clarity of explanation, and in actual implementation, variations of the illustrated shape may be expected. Accordingly, embodiments of the present invention should not be construed as limited to any particular shape of the regions shown herein. In addition, reference numerals of members in the drawings refer to the same members throughout the drawings.

As used herein, the term substrate refers to a semiconductor layer formed on a base structure such as silicon, silicon-on-insulator (SOI) or silicon-on-sapphire (SOS) or other underlying structure, a doped or undoped semiconductor Layer and a strained semiconductor layer. The base structure and the semiconductor are not limited to a silicon-based material but may be a III-V semiconductor material such as a silicon-germanium, a germanium and a gallium-gallium-based compound material, a II-VI semiconductor material such as ZnS, ZnSe, and CdSe , Mixed semiconductor materials, oxide semiconductor materials such as ZnO, MgO, MO ₂ , nanoscale materials such as carbon nanocrystals, or composite materials thereof.

In another embodiment, the substrate may be flexible to implement a flexible memory device, in which case the substrate may be formed of a resin-based material. The resin-based material may be, for example, various cellulose-based resins; Polyester resins such as polyethylene terephthalate (PET) and polyethylene naphthalate (PEN); Polyethylene resin; Polyvinyl chloride resin; Polycarbonate (PC); Polyethersulfone (PES); Polyetheretherketone (PEEK); And polyphenylene sulfide (PPS), or a combination thereof. These materials are merely illustrative, and the present invention is not limited thereto.

1A is a cross-sectional view showing a plurality of memory cells MC1, MC2, MCn of a resistive memory device 100 according to an embodiment of the present invention, and FIG. 1B is a cross-sectional view of a memory cell MCn shown in FIG. 1C is an energy band diagram of the memory cell MCn. The energy band diagram ignores the difference in work function between the anode electrode AE and the cathode electrode CE in the case where no charge is present in the memory cell MCn and a bias is applied to both ends of the memory cell MCn And shows the flat band of the memory cell MCn in the case where it is not. Energy band Diagram X of the coordinate axis indicates the distance, and y indicates the energy level.

1A, the memory cells MC1 and MC2 according to one embodiment include an anode electrode AE, a first dielectric layer DE1 on the anode electrode AE, a second dielectric layer DE2 on the first dielectric layer DE1, A cathode electrode CE on the second dielectric layer DE2 and a charge trap layer CL between the first dielectric layer DE1 and the second dielectric layer DE2. In some embodiments, the anode electrode AE may be electrically connected to the word line WL, and the cathode electrode CE may be electrically connected to the bit line BL. The word line WL may be inter-compatible with the bit line BL, and the present invention is not limited thereto.

The word lines WL and bit lines BL spaced apart from each other can extend in the y direction (direction perpendicular to the paper) and in the x direction to define intersections, and memory cells MC1 and MC2 Thereby achieving a cross point array structure having an output of 4F2. 1A, the anode electrode AE, the first dielectric layer DE1, the charge trap layer CL, the second dielectric layer DE2, and the cathode electrode CE are perpendicular to the substrate 10 z direction. However, the present invention is not limited thereto. For example, either the word line WL or the bit line BL may have a planar structure other than a line pattern on the substrate 10, or three-dimensionally arranged in space, and may be formed on at least a part of these lines The memory cell may be provided by stacking the anode electrode AE, the first dielectric layer DE1, the charge trap layer CL, the second dielectric layer DE2, and the cathode electrode CE in sequence or in reverse order.

The word line WLn formed on the substrate 10 may be a metal wiring pattern layer containing a metal such as aluminum, copper, an alloy thereof or a conductive metal oxide, or an n-type or p-type high concentration impurity layer formed through an impurity implantation process have. The metal pattern interconnection layer may be formed by a photolithography and etching process, forming a suitable metal film on the substrate 10, or may be formed by a damascene or dual damascene process. The high concentration impurity layer may be formed by implanting n-type or p-type impurity into the active region of the memory cell array region of the substrate 10. [

The anode electrode layer AE, the first dielectric layer DE1, the charge trap layer CL, the second dielectric layer DE2 and the cathode layer CE are sequentially formed on the word line WLn and patterned to form a columnar structure Of the memory cells MC1 and MC2 can be manufactured. Thereafter, an interlayer insulating film (ID) can be manufactured by forming an insulating film such as silicon oxide or silicon nitride on the substrate 10 and performing a planarization process.

The bit line BL may be formed on the interlayer insulating film ID. Although the word line WL and the bit line BL are shown as separate structures from the electrodes AE and CE in the illustrated embodiment, they may be integrally formed of the same metal, or a diffusion barrier layer Other metal layers for the Schottky barrier layer may also be formed.

The memory cells MC1 and MC2 of FIG. 1A can be represented by a diode component DI and a variable resistance component Rw connected in series between the word line WL and the bit line BL have. The diode component DI serves as a current steering element to enable access to selected ones of the adjacent memory cells and the variable resistance component Rw allows the memory cells MCn to have non-volatile characteristics. These features and advantages will be described later with reference to Figs. 2A to 2C.

1C, an anode electrode AE is arranged on the word line WL side and a cathode electrode CE is arranged on the bit line BL side in the current path from the word line WL to the bit line BL. ) Is disposed, the dielectric constant of the first dielectric layer DE1 may be selected from a material larger than the dielectric constant of the second dielectric layer DE2.

As the first dielectric layer DE1 and the second dielectric layer DE2, a suitable dielectric selected from the dielectrics listed in Table 1 may be used. Among these dielectrics, dielectrics having a dielectric constant larger than SiO ₂ are referred to as high-k dielectrics in particular, and the listed dielectrics are only exemplary and the present invention is not limited thereto, and other known dielectrics may be used. For example, a first dielectric layer (DE1) and a second dielectric layer _{(DE2), SrTiO 3, PbTiO} 3, (Hf, Zr) O 2, Pb (Zr, Ti) O 3, BaTiO 3, SrBi 2 Ta 2 O ₉ , K _x WO _3, and Bi ₄ Ti ₃ O ₁₂ may be used as the perovskite material.

Dielectric layer Dielectric constant (k) Band gap Eg (EV)) SiO ₂ 3.9 8.9 Si ₃ N ₄ 7 5.1 Al ₂ O ₃ 9.1 8.6 Ta ₂ O ₅ 26 4.5 HfO ₂ 25 5.7 TiO ₂ 80 3.5 Y ₂ O ₃ 15 5.5 La ₂ O ₃ 30 4.2 (Ba, Sr) TiO ₃ 300 3.5

As listed in Table 1, dielectric constants and band gaps of the dielectric layers DE1 and DE2 are property values inherent to these materials, but when applied to real memory cells, they can be adjusted for control of the charge injection barrier. For example, it is possible to control these physical properties by doping the host matrix of the listed dielectric layers with other elements or using a plurality of laminated structures. These dielectric layers may be formed by chemical vapor deposition, atomic layer deposition, evaporation or sputtering, or by other known chemical, physical vapor deposition, or plasma enhanced vapor deposition.

In some embodiments, the thickness of the first dielectric layer DE1 may be greater than the thickness of the second dielectric layer DE2. This difference in thickness can serve to control the threshold voltage of the rectifying effect of the dielectric layers DE1 and DE2 described below. However, this is illustrative, and the thickness of the first dielectric layer DE1 may be equal to or less than the thickness of the second dielectric layer DE2. The band gap Eg1 of the first dielectric layer DE1 may be smaller than the band gap Eg2 of the second dielectric layer DE2 but this is illustrative and the band gap Eg1 of the first dielectric layer DE1 is May be larger than the band gap Eg2 of the second dielectric layer DE2.

The dielectric layers DE1 and DE2 may be in contact with the anode electrode AE and the cathode electrode CE, respectively, to provide a potential barrier for the charge (phi _A , phi _B ). Potential barrier between In some embodiments, the anode electrode (AE) and the cathode electrode (CE) is the electrodes are each in contact with the dielectric layer (DE1, DE2) ф _A, ф _B is ф _A> ф be selected to satisfy the relation of _B . However, the potential barrier? _A ,? _B may or may not be nearly the same, and even the electrode material may be selected to satisfy the relationship of? _A <? _B.

Suitable electrode materials include platinum (Pt), tungsten (W), gold (Au), platinum (Pt), palladium (Pd), rhodium (Rh) iridium (Ir), ruthenium (Ru) (Mo), chromium (Cr), vanadium (V), titanium (Ti), aluminum (Al), copper (Cu), silver (Ag), nickel (Ni), conductive nitrides of these metals, Conductive oxide, or a combination thereof. These electrode materials have suitable electron affinities (XA, XB).

The charge trap layer CL between the dielectric layers DE1 and DE2 includes trapping sites TS for trapping and discharging electrons injected from the electrodes AE and CE and the cathode electrode CE. Trap sites TS may trap and emit holes injected from anode electrode AE as described above.

The trap sites TS of the charge trap layer CL may be provided by the interface itself between these dielectric layers, or they may be intentionally formed. For example, the charge trap layer CL may be formed by forming a first dielectric layer DE1 and then forming a defect surface layer by plasma damage or a heat treatment in a reactive gas atmosphere or by forming a first dielectric layer DE1 and a second dielectric layer DE2), and then doping these interface layers with impurities. In another embodiment, the charge trap layer CL may be a metal, metal oxide, metal nitride, or semiconductor layer having a structure such as a nano dot and a naphtha sheet formed of various metals, semiconductors or a combination thereof, or having a trap site .

As another embodiment, it is possible to artificially form defects such as oxygen vacancies in the surface layer of the second dielectric layer DE2 and the first dielectric layer DE1 belonging to the vicinity of the interface between the second dielectric layer DE1 and the first dielectric layer DE1 Or may form an impurity doped or undoped polycrystalline layer.

The materials of the above-described charge trap layer CL are illustrative, and the present invention is not limited thereto. For example, the charge trap layer CL is suitable for nanostructures or bulk structures as long as it can provide a localized trap site to ensure good charge retention time. This charge trap layer CL not only remarkably suppresses the data retention time reduction due to the leakage current by appropriately selecting the thickness of the adjacent dielectric layers DE1 and DE2 but also prevents the trap levels and / May be provided to implement multi-bit driving.

FIGS. 2A and 2B are energy band diagrams for explaining the rectifying characteristics of a memory cell according to an embodiment of the present invention, and FIG. 2C is an energy band diagram for explaining a resistance change when charges are trapped.

The dielectric constant difference of the dielectric layers DE1 and DE2 of the memory cell MCn induces an electric field difference applied to each of these dielectric layers by a voltage bias applied to the memory cell MCn. For example, in the case where there is no charge in the charge trap layer CL, a boundary condition according to Equation 1 is established because the total flux density is continuous between the dielectric layers DE1 and DE2.

[Formula 1]

(where E1 is the intensity of the electric field applied to the first dielectric and E2 is the electric field strength applied to the second dielectric)

According to Equation 1, when the dielectric constant of the first dielectric layer DE1 is larger than the dielectric constant of the second dielectric layer DE2, as described above, since the intensity of the electric field applied to the dielectric is inversely proportional to the dielectric constant, ) May induce a larger electric field in the second dielectric layer DE. As a result, band bending of the second dielectric layer DE2 becomes worse than that of the first dielectric layer DE2.

2A, when a voltage is applied from the anode electrode AE to the cathode electrode CE in the memory cell MCn, that is, when a positive bias is applied, the first dielectric layer A larger electric field can be induced in the second dielectric layer DE2 than in the first dielectric layer DE1. As a result, the tunneling distance is significantly reduced by energy band bending in the second dielectric layer DE2, and Fowler-Nordheim Tunneling (arrow A1) or avalanche injection ; The arrow A2), the current flows through the dielectric layers DE1 and DE2. Further, since a strong electric field E2 is applied to the second dielectric layer DE2, conduction components by direct tunneling can also be induced when the thickness of the second dielectric layer DE2 is sufficiently small.

2B, when a voltage is applied to the memory cell MCn from the cathode electrode CE toward the anode electrode AE, that is, when a reverse bias is applied, the first dielectric layer DE1 is electrically connected to the second dielectric layer DE1, An electric field smaller than the electric field DE2 is induced. As a result, conduction by tunneling (arrow B1) or avalanche injection (arrow B2) is difficult to occur in the anode electrode CE.

As described above with reference to Figs. 2A and 2B, the potential barrier of the bending energy band of the dielectric layer can be selectively overcome by a large electric field applied to the second dielectric layer DE2, so that only when a positive bias is applied, The self-rectifying characteristic in which the current flows is realized. Accordingly, according to the embodiment of the present invention, a self-diode component DI connected in series between the word line WL and the bit line BL as shown in FIG. 1B can be implemented. The diode component DI may serve as a current steering device that allows programming or reading operations only to selected ones of adjacent memory cells in a memory cell having an array of cross-point structures, A switching element can be substituted, so that a memory element which is economical and highly integrated can be achieved.

Referring to FIG. 2C, the charge can be stored in a discrete trap of the charge trap layer CL of the memory cell MCn. The trap charge TC is injected through the second dielectric layer DE2 via the Fowler node or direct tunneling during the programming operation to be trapped and localized at the trap site IS and the adjacent first dielectric layer DE1 and the second dielectric layer DE1, Lt; RTI ID = 0.0 &gt; DE2. &Lt; / RTI &gt; In some embodiments, when the dielectric constant and thickness of the first dielectric layer DE1 are larger than the second dielectric layer DE2, the tunneling occurs mainly through the second dielectric layer DE2, so that the first dielectric layer DE1 The leakage current can be prevented and the charge trap for the programming can be detrapped only through the second dielectric layer DE2 between the charge trap layer CL and the cathode electrode CE.

In the above-described embodiment, only the electron tunneling is exemplified. However, this is an example. In the forward driving, a hole tunnel occurs due to the direct tunneling through the first dielectric layer DE1 and is trapped in the charge trap layer CL, May be neutralized.

As described above, when trap charge TC is present in the charge trap layer CL, the electric field applied to each of the dielectric layers DE1 and DE2 is expressed by Equations 2 and 3.

[Formula 2]

[Formula 3]

In Equations 2 and 3,? ₀ is the dielectric constant of vacuum, Vappl is the voltage applied between the anode electrode AE and the cathode electrode CE,? 1 and? 2 and d1 and d2 are the first and second dielectric layers DE1 , DE2), respectively.

Referring to Equations 2 and 3, when there is a trap charge in the charge trap layer CL, the electric fields E1 and E2 induced in each dielectric layer can be reduced as compared with the case where there is no trap charge. As a result, when the applied voltage Vappl is a forward voltage, the current due to tunneling is reduced. As described above, the difference in magnitude of the current flowing from the anode electrode AE to the cathode electrode CE in the case where there is trapped charge in the charge trap layer CL and in the case where there is no trapped charge can be evaluated as a difference in resistance value, The trap layer CL implements the variable resistance component Rw in the memory cell MCn, as shown in Fig. 1B.

For example, when there is a negative trap charge TC as shown in FIG. 2C, the variable resistance component becomes a high resistance state (HRS), and when there is no trap charge TC, And becomes a low resistance state (LRS), and this resistance state can be reversibly switched by applying an appropriate programming or erasing voltage to the memory cell MCn.

Logic values " 1 " and " 0 " are assigned to the resistance states corresponding to the trap charge TC, and arbitrary memory cells address by the selection of the bit line BL and the word line WL, By sensing, the stored information can be read, and this read-out method can non-destructively read the information stored in the memory cell, thus realizing a non-volatile memory operation.

3A and 3B are graphs showing a relationship between a voltage and a current relating to driving of a memory cell according to an embodiment of the present invention. Fig. 3A relates to a nonvolatile memory driving method using an electron trap, To a nonvolatile memory driving method using a Hall trap. It is assumed that all dominant currents are generated by conduction by electrons.

Referring to FIG. 3A, when a positive voltage is applied to a memory cell in which electrons are not trapped, the memory cell is in a low resistance state (LRS). Thereafter, when the voltage increases, the programming operation may be performed by the trap of the electrons tunneled from the cathode electrode to the charge trap layer of the memory cell (indicated by? In Fig. 3A). In this case, the memory cell becomes a high resistance state (HRS) by electrons trapped in the conduction by electrons. When the polarity applied to the memory cell is reversed, the trapped electrons can be de-trapped from the charge trap layer. However, it is to be understood that, after an electron trap has occurred at a positive voltage, an erase operation may be performed in which further trapping of the trapped electrons occurs when the voltage is further increased.

Referring to FIG. 3B, when a positive voltage is applied to the hole-trapped memory cell, the memory cell may be in the low resistance state (LRS), unlike the case of the electron trap. When the voltage is increased, the trapped hole is de-trapped and the data erase operation in which the memory cell becomes the high resistance state (HRS) can be performed. The polarity applied to the memory cell is reversed, and if the reverse voltage is increased, the programming operation by the hole trap (the part indicated by? In FIG. 3B) may occur.

The reading operation of the bit information of the memory cell can be performed in a low voltage region where no trap occurs. Although the embodiments described above mainly relate to the case where the dominant current appears by the electron conduction, conversely, the dominant current conduction may also be caused by the hole conduction, and the erase operation is terminated by the tunneling of the trapped charges, Or alternatively, may occur by recombination occurring as the charge having the opposite polarity to the trapped charge in the charge trap layer is trapped. Further, the terms programming and erase operations are mutually compatible, so that a case where a charge is trapped and becomes a high resistance state is referred to as an erase operation, and a case where a charge is trapped to become a low resistance state may be referred to as a programming operation.

4 is a cross-sectional view showing a memory device 200 according to another embodiment of the present invention. As for the constituent elements of these drawings which have the same reference numerals as the constituent elements of the above-mentioned drawings, the above-mentioned disclosure can be referred to and the following description is not repeated.

Referring to FIG. 4, the resistive memory device 2000 may have a three-dimensional vertical structure in which two-layer memory stacks ST1 and ST2 are stacked. Each of the memory stacks ST1 and ST2 includes first to third wiring layers 20a, 20b and 20c which are coupled with the memory cells MCn. In some embodiments, the one wiring layer 20b of the resistive memory element 2000 may be shared by two memory stacks ST1 and ST2 as shown. The first and third wiring layers 20a and 20c may be word lines and the second wiring layer 20b may be a bit line. The memory cells MCn of the memory stacks ST1 and ST2 can be electrically isolated by the respective interlayer insulating films ID1 and ID2.

The illustrated arrangements can be variously modified with reference to the above-described disclosure. For example, the positions of the cathode electrode and the anode electrode are reversed, so that the order of the dielectric layers can also be reversed. And may have a plurality of stacks of three or more.

5 is a block diagram illustrating a memory device 1000 in accordance with one embodiment of the present invention.

Referring to FIG. 5, the memory device 1000 may be coupled to the host 1510. Host 1510 may be an example processor or memory controller. In one embodiment, the memory device 1000 may include an address interface 1001, a control interface 1002, and a data interface 1003, each coupled to a processor 1510 for memory read and programming access .

In some embodiments, a combined type of interface 1004, such as an address / data interface, may be used as is well known in the art. The interface 1004 may be a synchronous memory interface such as SDRAM or DDR-SDRAM. Inside the memory device 1000 an internal memory controller 1010 can manage internal operations, e.g., non-volatile memory array 1020 and update the RAM control register 1030. RAM control register 1030 may be used by internal memory controller 1010 during operation of memory device 1000.

Non-volatile memory array 1020 may include a series of memory banks or segments ARn, and each bank 1020n may be logically grouped or grouped into a series of blocks. The memory address may be performed by the address interface 1001 and may be divided into row and column address portions.

During a read operation, the row address is latched and decoded by the row decode circuit 1040 to select and activate the row or page of memory cells of the selected memory bank. The encoded bit information in the output signal of the selected row of memory cells may be coupled to a local bit line (not shown) and a global bit line (not shown) and detected by a sense amplifier 1050 coupled to a memory bank .

During a read operation, the column address is also latched and decoded by the column decode circuit 1060. [ The output of the column decode circuit 1060 can select predetermined column data from an internal data bus (not shown). The internal data bus is coupled to the outputs of the respective sense amplifiers 1060 and is coupled to the I / O buffer 1070 for signal delivery from the memory device 1000 via the data interface 1003 .

In a write operation, the row decode circuit 1040 selects a row page, and the column decode circuit 1060 can select a write sense amplifier 1050. The data values to be written are coupled from the I / O buffer 1070 via the internal data bus to the write sense amplifiers 1050 selected by the column decode circuit 1060 and the selected resistive type May be written to memory cells (not shown). The recorded cells can then be reselected by the row and column decode circuits 1040 and 1060 and the sense amplifiers 1050 to be read and verified that the correct value has been programmed into the selected memory cell.

The resistive memory elements disclosed with reference to the drawings attached hereto may be implemented as single memory cells or may be integrated with other devices within a chip, such as other heterogeneous devices, e.g., a logical processor, an image sensor, Together, they may be implemented in the form of a system on chip (SOC). Further, the wafer chip on which the resistance type memory element is formed and the other wafer chip on which the dissimilar device is formed may be bonded to each other by using an adhesive, soldering or wafer bonding technique, and individualized to form a single chip.

In addition, the resistive memory devices according to the above-described embodiments can be implemented in various types of semiconductor packages. For example, the resistive memory devices according to embodiments of the present invention may be implemented in a package on package (PoP), ball grid arrays (BGAs), chip scale packages (CSPs), plastic leaded chip carriers (PLCC) Linear Package (PDIP), Die in Waffle Package, Die in Wafer FoSM, Chip On Board (COB), Ceramic Dual In-Line Package (CERDIP), Plastic Metric Quad Flat Package (MQFP), Thin Quad Flat Package Small Outline Package (SSOP), Thin Small Outline Package (TSOP), Thin Quad Flat Package (TQFP), System In Package (SIP), Multi Chip Package (MCP), Wafer-level Fabricated Package (WFP) or a Wafer-Level Processed Stack Package (WSP). The package in which the resistive memory elements according to the embodiments of the present invention are mounted may further include a controller and / or a logic element for controlling the same.

Figure 6 is a block diagram illustrating an electronic system 2000 that includes resistive memory elements in accordance with one embodiment of the present invention.

6, an electronic system 2000 includes a controller 2010, an input / output device (I / O) 2020, a storage device 2030, an interface 2040 and a bus 2050 . The controller 2010, the input / output device 2020, the storage device 2030 and / or the interface 2040 may be coupled to each other via the bus 2050.

The controller 2010 may include at least one of a microprocessor, a digital signal process, a microcontroller, and logic elements capable of performing similar functions. The input / output device 2020 may include a keypad, a keyboard, a touch screen, or a display device. The storage device 2030 may store data and / or instructions, and the storage device 2030 may include the resistive memory elements disclosed herein.

In some embodiments, the memory device 2030 may have a hybrid structure that further includes other types of semiconductor memory devices (e.g., a DRAM device and / or an Slam device). The interface 2040 may perform the function of transmitting data to or receiving data from the communication network. Interface 2040 may be in wired or wireless form. To this end, the interface 2040 may include an antenna or a wired or wireless transceiver. Although not shown, the electronic system 2000 is an operation memory for improving the operation of the controller 2010, and may further include a high-speed DRAM and / or an SRAM.

The electronic system 2000 is a personal digital assistant (PDA). A portable computer, a tablet PC, a wireless phone, a mobile phone, a digital music player, a memory card, or information in a wireless environment. And / or &lt; RTI ID = 0.0 &gt; and / or &lt; / RTI &gt; The above-described variable resistor may be used as a fuse or an anti-fuse, or may be used as a logic device using the same.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention as defined in the appended claims. It will be clear to those who have knowledge.

Claims (19)

An anode electrode;
A first dielectric layer formed on the anode electrode, the first dielectric layer having a first dielectric constant;
A second dielectric layer formed on the first dielectric layer, the second dielectric layer having a second dielectric constant smaller than the first dielectric constant;
A cathode electrode formed on the second dielectric layer; And
And a charge trap layer between the first dielectric layer and the second dielectric layer. The method according to claim 1,
Wherein the potential barrier between the first dielectric layer and the anode electrode is greater than the potential barrier between the second dielectric layer and the cathode electrode. The method according to claim 1,
Wherein the thickness of the first dielectric layer is thicker than the thickness of the second dielectric layer. The method according to claim 1,
Wherein the charge trap layer is an interface layer itself of the first dielectric layer and the second dielectric layer. The method according to claim 1,
Wherein the charge trap layer includes any one of a plasma damage layer, a defect surface layer formed by heat treatment of a reactive gas atmosphere, and an impurity doped layer or a combination of two or more thereof. The method according to claim 1,
Wherein the charge trap layer comprises any one of nano dots and nanosheets, or a combination thereof. The method according to claim 1,
Wherein the charge trap layer comprises any one of a metal, a metal oxide, a metal nitride, and a semiconductor layer, or a combination thereof. 1. A resistive memory device comprising an array of a plurality of memory cells arranged at intersections of first wirings and second wirings extending to intersect with the first wirings,
Wherein each of the plurality of memory cells includes:
An anode electrode;
A first dielectric layer formed on the anode electrode, the first dielectric layer having a first dielectric constant;
A second dielectric layer formed on the first dielectric layer, the second dielectric layer having a second dielectric constant smaller than the first dielectric constant;
A cathode electrode formed on the second dielectric layer; And
And a charge trap layer between the first dielectric layer and the second dielectric layer, and allocating bit information to the resistance value of the memory cell by the magnitude of the trap charge of the charge trap layer induced by applying a voltage signal to each memory cell Resistance type memory element. 9. The method of claim 8,
Wherein a potential barrier between the first dielectric layer and the anode electrode is greater than a potential barrier between the second dielectric layer and the cathode electrode. 9. The method of claim 8,
Wherein the thickness of the first dielectric layer is thicker than the thickness of the second dielectric layer. 9. The method of claim 8,
Wherein the charge trap layer is the interface layer itself of the first dielectric layer and the second dielectric layer. 9. The method of claim 8,
Wherein the charge trap layer includes any one of a plasma damage layer, a defect surface layer formed by heat treatment of a reactive gas atmosphere, and an impurity doped layer or a combination of two or more thereof. 9. The method of claim 8,
Wherein the charge trap layer comprises any one or combination of nano dots and nanosheets. 9. The method of claim 8,
Wherein the charge trap layer comprises any one of a metal, a metal oxide, a metal nitride, and a semiconductor layer, or a combination thereof. 9. The method of claim 8,
Wherein at least one of the first and second dielectric layers is SiO ₂ . _{Si 3 N 4, Al 2 O} 3, Ta 2 O 5, HfO 2, TiO 2, Y 2 O 3, La 2 O 3, ZrO 2, SrTiO 3, BaTiO 3, PbTiO 3, Pb (Zr, Ti) O ₃ , (Hf, Zr) O ₂ , (Ba, Sr) TiO ₃ , SrBi ₂ Ta ₂ O ₉ , KWO ₃ and Bi ₄ Ti ₃ O ₁₂ . 9. The method of claim 8,
Wherein at least one of the anode electrode and the cathode electrode is formed of at least one of platinum (Pt), tungsten (W), gold (Au), platinum (Pt), palladium (Pd), rhodium (Rh), iridium (Ir) ), Tantalum (Ta), molybdenum (Mo), chromium (Cr), vanadium (V), titanium (Ti), aluminum (Al), copper (Cu), silver (Ag) A conductive nitride of a metal, and a conductive oxide of these metals, or a combination thereof. 9. The method of claim 8,
Wherein one of the first wiring and the second wiring is a word line and the other is a bit line. The method according to claim 1,
Wherein a magnitude of a current flowing from the anode electrode to the cathode electrode varies depending on whether a charge or a hole is trapped in the charge trap layer. 9. The method of claim 8,
Wherein a magnitude of a current flowing from the anode electrode to the cathode electrode varies depending on whether a charge or a hole is trapped in the charge trap layer.

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