KR101926860B1 - Semiconductor memory device and operating method thereof - Google Patents

Abstract

The present invention relates to a semiconductor memory device and a method of operating the same. A method of operation of a semiconductor memory device according to an embodiment of the present invention includes changing an erase bias to be used in an erase operation every time a program erase cycle reaches log scale values that increase in a unit of magnitude.

Description

Technical Field [0001] The present invention relates to a semiconductor memory device and a method of operating the same,

The present invention relates to a semiconductor memory device and a method of operating the same.

A semiconductor memory device is a memory device implemented using semiconductors such as silicon (Si), germanium (Ge), gallium arsenide (GaAs), indium phosphide (InP) to be. Semiconductor memory devices are classified into a volatile memory device and a nonvolatile memory device.

The volatile memory device is a memory device in which data stored in the volatile memory device is lost when power supply is interrupted. Volatile memory devices include static RAM (SRAM), dynamic RAM (DRAM), and synchronous DRAM (SDRAM). A nonvolatile memory device is a memory device that retains data that has been stored even when power is turned off. A nonvolatile memory device includes a ROM (Read Only Memory), a PROM (Programmable ROM), an EPROM (Electrically Programmable ROM), an EEPROM (Electrically Erasable and Programmable ROM), a flash memory device, a PRAM ), RRAM (Resistive RAM), and FRAM (Ferroelectric RAM). Flash memory devices are largely divided into NOR type and NAND type.

The memory cell of a semiconductor memory device, for example, a flash memory device, varies in threshold voltage as the program / erase cycle increases. The operation bias of the semiconductor memory device is required to be changed in accordance with the change in the threshold voltage.

An embodiment of the present invention is to provide a semiconductor memory device and a method of operating the same which improve the speed and reliability of the erase operation.

A method of operation of a semiconductor memory device according to an embodiment of the present invention includes changing an erase bias to be used in an erase operation each time a program erase cycle reaches a log scale value that increases in a certain unit.

A method of operating a semiconductor memory device according to another embodiment of the present invention stores a value of a first step pulse used in an erase operation when a program erase cycle reaches a first threshold value; Storing a value of a second step pulse used in an erase operation when the program erase cycle reaches a second threshold value; And changing the erase bias based on the difference of the first and second step pulses when the program erase cycle reaches a third threshold value. The difference between the log scale values of the second and third thresholds and the log scale values of the first and second thresholds are the same.

As an embodiment, an erase operation after the program erase cycle reaches the third threshold value will be performed using the modified erase bias.

Another aspect of the present invention relates to a semiconductor memory device. A semiconductor memory device according to an embodiment of the present invention includes: a memory cell array including a plurality of memory cells; And a peripheral circuit configured to count a program erase cycle of the memory cell array and to change an erase bias to be used for the erase operation for the memory cell array each time the program erase cycle reaches a log scale value that increases by a certain magnitude, .

A method of operating a semiconductor memory device according to another embodiment of the present invention includes: storing a value of a first step pulse used in a first erase operation; Determining whether a second step pulse that is larger in magnitude than the first step pulse by a predetermined value is used in the second erase operation; And determining a program erase cycle in which the erase bias is to be changed based on the log scale values of the program erase cycles corresponding to the first and second erase operations, in accordance with the determination result.

As an embodiment, the difference between the log scale values of the program erase cycles corresponding to the first and second erase operations and the difference between the program erase cycle corresponding to the second erase operation and the log scale values of the determined program erase cycle Can be the same.

As an embodiment, the erasing bias is changed based on the difference of the first and second step pulses; And performing an erase operation corresponding to the determined program erase cycle using the modified erase bias.

A semiconductor memory device according to another embodiment of the present invention includes: a nonvolatile memory including a plurality of memory cells; And a peripheral circuit configured to count a program erase cycle of the nonvolatile memory. Wherein when the first step pulse is used in the first erase operation and the second step pulse used in the second erase operation is larger than the first step pulse by a predetermined value, And to determine a program erase cycle at which the erase bias is to be changed based on the log scale values of the program erase cycles.

According to an embodiment of the present invention, a semiconductor memory device and an operation method thereof are provided in which the speed and reliability of the erase operation are improved.

1 is a block diagram showing a semiconductor memory device 100 according to an embodiment of the present invention.
2 is a flowchart showing an erasing operation of the semiconductor memory device 100 of FIG.
FIG. 3 is a diagram showing step pulses applied to the substrate of the memory cell array 110. FIG.
4 is a diagram showing a relationship between a threshold voltage of a memory cell and a program erase cycle.
5 is a flowchart showing a method of operating the semiconductor memory device 100 according to an embodiment of the present invention.
6 is a flowchart showing a method of changing an erase bias.
7 is a flowchart showing another embodiment of a method of changing erase bias.
8 is a block diagram illustrating a memory system 1000 in accordance with an embodiment of the present invention.
FIG. 9 is a block diagram illustrating a computing system 2000 that includes the memory system 1000 of FIG.

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention, and how to accomplish it, will be described with reference to the embodiments described in detail below with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein but may be embodied in other forms. It is to be understood that both the foregoing general description and the following detailed description of the present invention are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.

Throughout the specification, when a part is referred to as being "connected" to another part, it includes not only "directly connected" but also "indirectly connected" . Throughout the specification, when an element is referred to as "comprising ", it means that it can include other elements as well, without excluding other elements unless specifically stated otherwise.

1 is a block diagram showing a semiconductor memory device 100 according to an embodiment of the present invention.

Referring to FIG. 1, a semiconductor memory device 100 includes a memory cell array 110, an address decoder 120, a read and write circuit 130, a voltage generator 140, and a control logic 150.

The memory cell array 110 is connected to the address decoder 120 via word lines WL and to the read and write circuit 130 via bit lines BL. The memory cell array 110 includes a plurality of memory blocks BLK1 to BLKz. The plurality of memory blocks BLK1 to BLKz include a plurality of memory cells. In an exemplary embodiment, the plurality of memory cells may be non-volatile memory cells. In an exemplary embodiment, each of the plurality of memory cells may be a single level cell or a multi level cell.

The memory cells arranged in the row direction are connected to the word lines WL. The memory cells arranged in the column direction are connected to the bit lines BL. For example, memory cells arranged in one column form one cell string, and each cell string will be connected to each bit line.

The memory cells connected to one word line constitute at least one page. The program operation and the read operation of the semiconductor memory device 100 may be performed page by page. The erase operation of the semiconductor memory device 100 may be performed on a memory block basis.

The address decoder 120, the read and write circuit 130, the voltage generator 140 and the control logic 150 are provided as a peripheral circuit for controlling the memory cell array 110.

The address decoder 120 is coupled to the memory cell array 110 via word lines WL. Address decoder 120 is configured to operate in response to control of control logic 150. The address decoder 120 receives an address ADDR from an input / output buffer (not shown) in the external or semiconductor memory device 100.

The address decoder 120 is configured to decode the block address of the received address ADDR. The address decoder 120 will select at least one memory block according to the decoded block address.

In a program operation or a read operation, the address decoder 120 is configured to decode the row address of the received address ADDR. The address decoder 120 selects the word lines WL according to the decoded row address. The address decoder 120 will decode the column address of the received address ADDR and send the decoded column address Yi to the read and write circuit 130, for example, during a read operation.

In an exemplary embodiment, the address decoder 120 may include a block decoder, a row decoder, a column decoder, an address buffer, and the like.

The read and write circuit 130 is connected to the plurality of memory blocks BLK1 to BLKz through the bit lines BL. The read and write circuit 130 operates in response to control of the control logic 150.

During a program operation or a read operation, the read and write circuit 130 exchanges data with external or input / output buffers (not shown). At the time of programming, the read and write circuitry 130 receives the data (DATA) and programs the received data (DATA) into the memory cells of the selected word line. In a read operation, the read and write circuit 130 reads data from the memory cells of the selected word line and outputs data (DATA) corresponding to the decoded column address Yi in the read data.

As an example embodiment, the read and write circuitry 130 may include page buffers (or page registers), column select circuitry, and the like.

The voltage generator 140 is configured to generate a plurality of voltages using the power supply voltage supplied to the semiconductor memory device 100. For example, the voltage generator 140 may include a plurality of pumping capacitors, and may selectively activate a plurality of pumping capacitors to generate a plurality of voltages. With the control of the control logic 150, the voltages generated at the voltage generator 140 will be determined.

In the erase operation, erase pulses P generated in the voltage generator 140 are applied to the substrate of the memory cell array 110. When the erase pulses P are applied to the substrate, the address decoder 120 provides the ground voltage to the word lines WL connected to the selected memory block and the word lines WL connected to the unselected memory blocks It can be flared.

The control logic 150 is coupled to the address decoder 120, the read and write circuitry 130 and the voltage generator 140. The control logic 150 is configured to control all operations of the semiconductor memory device 100. In response to the control signal CTRL, the control logic 150 will control the address decoder 120, the read and write circuitry 130 and the voltage generator 140.

The control logic 150 is configured to count a program erase cycle of the semiconductor memory device 100 and store the program erase cycle in the register 151. [ It will be appreciated that the program erase cycle may be counted in various ways. For example, the program erase cycle may be determined according to the number of times program operations are performed. As another example, the program erase cycle may be determined according to the number of times erase operations have been performed. As another example, the program erase cycle may be determined according to the total number of times program operations and erase operations have been performed.

The data stored in the register 151 will be stored in the meta area of the memory cell array 110. For example, the program erase cycle stored in the register 151 will be stored in the first memory block BLK1 of the memory cell array 110 at power-off time. At power-on, the program erase cycle stored in the first memory block BLK1 will be loaded into the register 151 via the read and write circuitry 130. [

The control logic 150 controls the voltage generator 140 to change the erase bias used in the erase operation to change the erase bias used for the erase operation. ≪ RTI ID = 0.0 > . The erase bias can be defined according to the erase pulses P. For example, the erase bias may be defined as the voltage level of the start pulse among the erase pulses P. As another example, the erase bias may be defined as the voltage difference between the erase pulses P.

The semiconductor memory device 100 may further include an input / output circuit (not shown). The I / O circuitry will operate in response to control of the control logic 150. The input / output circuit will receive the control signal CTRL and the address ADDR from the outside and deliver the received control signal CTRL and address ADDR to the control logic 150 and the address decoder 120, respectively. The input / output circuit may be configured to transfer data (DATA) from the outside to the read / write circuit 130 and to transfer the data (DATA) from the read / write circuit 130 to the outside.

In an exemplary embodiment, the semiconductor memory device 100 may be a flash memory.

According to an embodiment of the present invention, the erase bias used for the erase operation is changed as the program erase cycle increases. By using a suitable erase bias, the reliability and speed of the erase operation will be improved.

According to the embodiment of the present invention, the erase bias is not changed each time the erase operation is performed, but is changed each time the program erase cycle is increased by a certain magnitude. Therefore, the time required for changing the erase bias will be relatively reduced.

2 is a flowchart showing an erasing operation of the semiconductor memory device 100 of FIG.

Referring to FIGS. 1 and 2, in step S1, an erase pulse is first applied to the substrate of the memory cell array 110. FIG. As the erase pulse is applied, the threshold voltages of the memory cells of the selected memory block will decrease.

In step S2, it is determined whether the threshold voltages of the memory cells of the selected memory block have reached a desired level. When the threshold voltages of the memory cells of the selected memory block reach a desired level, the erase operation is ended. If the threshold voltages of the memory cells of the selected memory block have not reached the desired level, step S3 is performed. In step S3, the erase pulse is increased by a predetermined pulse increment Vd.

For example, the read and write circuit 122 senses the threshold voltages of the memory cells via bit lines BL and generates an erase pass or erase fail based on the sensed data (DATA) To the control logic 150. The control logic 150 controls the voltage generator 140 to terminate the erase operation according to the received sensing signal or to generate an erase pulse that is increased by a predetermined pulse increment Vd.

FIG. 3 is a diagram showing step pulses applied to the substrate of the memory cell array 110. FIG.

Referring to FIG. 3, the step pulse includes a plurality of erase pulses P1 to Pn. The first to n < th &gt; erase pulses P1 to Pn gradually increase. The first erase pulse P1 as a start pulse has a start voltage Vstr. The second erase pulse P2 has a voltage level higher than the start voltage level Vstr by a predetermined pulse increase amount Vd. The k-th erase pulse (1 <k <n, k is an integer) will have a voltage level higher than the (k-1) -th erase pulse by a predetermined pulse increment Vd. That is, the step pulse will gradually increase from the start voltage level Vstr by the predetermined pulse increase amount Vd to reach the end voltage Vend.

As described with reference to FIG. 2, it is determined whether or not the threshold voltages of the memory cells erased after each erase pulse is applied in the erase operation reach a desired voltage level, and whether or not the next erase pulse is applied is determined according to the determination result do. At this time, although each erase operation is performed using the same erase bias (e.g., the same start voltage and the same pulse increment), the number of erase pulses applied may be different. That is, the step pulses used in each erase operation may be different from each other.

The difference in step pulse will mean that the end voltage (Vend) level of the step pulse is different. The difference in the step pulse will mean that the number of erase pulses applied is different.

4 is a diagram showing a relationship between a threshold voltage of a memory cell and a program erase cycle.

Referring to FIG. 4, the horizontal axis represents the log scale of the program erase cycle. The vertical axis represents the threshold voltage of the memory cell. In the description with reference to FIG. 4, it is assumed that the data stored in the memory cell does not fluctuate.

As the program erase cycle increases, the threshold voltage of the memory cell increases. The log scale value of the program erase cycle and the threshold voltage of the memory cell are proportional. This is due to various causes such as electrons being trapped in the oxide insulating layer of the memory cell as the program and erase operations are repeated.

As the threshold voltage of the memory cell increases, the end voltage level of the step pulse used in the erase operation will also increase. That is, the number of times the erase pulses are applied in the erase operation will increase. It is assumed that the end voltage level of the step pulse used when the program erase cycle is 1 is 15V and the end voltage level of the step pulse used when the program erase cycle is 100 times is 16V. At this time, it can be predicted that the end voltage level of the step pulse to be used when the program erase cycle is 10,000 is 17V. As the end voltage level of the step pulse increases, the time required for the erase operation will increase. In accordance with an embodiment of the present invention, each time the program erase cycle reaches thresholds that increase by a certain magnitude, the erase bias used in the erase operation is changed.

5 is a flowchart showing a method of operating the semiconductor memory device 100 according to an embodiment of the present invention.

Referring to FIG. 5, first, it is determined whether a program erase cycle is reached in one of the log scale values increasing in units of a predetermined size (S10). If so, the erase bias is changed (S20). That is, the erase bias is changed every time a program erase cycle reaches log scale values that increase in units of a certain size. Thus, the speed of the erase operation is improved compared to when the erase bias is changed each time the erase operation is performed. This will be described in more detail with reference to FIG.

6 is a flowchart showing a method of changing an erase bias.

Referring to FIGS. 1 and 6, in step S110, an erase operation is performed. As the erase operation is performed, the program erase cycle will increase.

In step S120, the value of the first step pulse used in the erase operation when the program erase cycle reaches the first threshold value is stored in the register 151. [ Step S120 includes steps S121 and S122.

In step S121, it is determined whether the program erase cycle has reached the first threshold value. If so, step S122 is performed. In step S122, the value of the first step pulse used in the erase operation is stored in the register 151. [

As an exemplary embodiment, which step pulse is used for the erase operation may be stored in various ways. The value of the step pulse can be stored by storing the end voltage level of the applied step pulse in the erase operation. As another example, the value of the step pulse can be stored by storing in the register 151 the number of erase pulses applied in the erase operation. Hereinafter, it is assumed that the end voltage level of the step pulse is stored for convenience of explanation.

In step S130, an erase operation is performed. In step S140, the value of the second step pulse used for the erase operation when the program erase cycle reaches the second threshold value is stored in the register 151. [ Step S140 includes steps S141 and S142.

In step S141, it is determined whether or not the program erase cycle has reached the second threshold value. If so, step S142 is performed. In step S142, the value of the second step pulse used for the erase operation is stored. The end voltage level of the second step pulse will be stored in the register 151. [

In step S150, an erase operation is performed. In step S160, when the program erase cycle reaches the third threshold value, the erase bias to be used for the erase operation is changed. According to the embodiment of the present invention, a program clearance cycle (third threshold value) at which the erase bias is to be changed is determined in accordance with log scale values (log scale values of the first and second thresholds) which increase to a constant magnitude.

The third threshold value may be determined by adding the difference between the log scale values of the first and second threshold values and the log scale value of the second threshold value. That is, the difference of the log scale values of the second and third thresholds is equal to the difference of the log scale values of the first and second thresholds. That is, the log scale values of the first to third thresholds are increased in units of a constant size. Step S160 includes steps S161 and S162.

In step S161, it is determined whether or not the program erase cycle has reached the third threshold value. If so, step S162 is performed. In step S162, the erase bias to be used for the erase operation is changed. The erase bias to be used for the erase operation is changed based on the difference of the first and second step pulses. As an exemplary embodiment, the start voltage level and the pulse increment of the step pulse to be used for the erase operation can be determined according to the difference in the end voltage levels of the first and second step pulses. For example, the greater the difference in the end voltage levels of the first and second step pulses, the more the start voltage level and the pulse increase amount of the step pulse to be used in the erase operation will increase.

As an exemplary embodiment, the erase bias change of the test memory cell array generated through the same process as that of the memory cell array 110 can also be performed in the same manner as described with reference to Fig. The erase bias applied to the test memory cell array can be changed each time the program erase cycle (Test pattern cycle, TP cycle) of the test memory cell array reaches log scale values increasing in a constant unit.

7 is a flowchart showing another embodiment of a method of changing erase bias.

Referring to FIGS. 1 and 7, in step S210, a first erase operation is performed when the program erase cycle is i cycles.

In step S220, the value of the first step pulse used in the first erase operation and the corresponding program erase cycle value (i) are stored in the register 151. [

In step S230, a second erase operation is performed when the program erase cycle is j times. At this time, each of the first and second erase operations will mean any erase operation.

In step S240, step S250 is selectively performed depending on whether the second step pulse used in the second erase operation is larger than the first step pulse by a predetermined value CV. In step S250, a program erase cycle for which the erase bias is to be changed is determined based on the program erase cycle (i) and the program erase cycle (j). The log scale value of the program erase cycle for which the erase bias is to be changed can be calculated by adding the difference between the log scale values of the program erase cycles (i, j) and the log scale value of the program erase cycle (j). That is, the log scale value of each of the program erase cycle (i), the program erase cycle (j), and the determined program erase cycle will increase to a certain magnitude.

At this time, the erase bias to be changed is determined according to the difference between the first and second step pulses. For example, the greater the difference in the end voltage levels of the first and second step pulses, the more the start voltage level and the pulse increase amount of the step pulse to be used in the erase operation will increase.

As a result, the program erase cycle in which the erase bias is to be changed is determined based on the step pulse used in the current erase operation (second erase operation) and the step pulse used in the previous erase operation (first erase operation) .

8 is a block diagram illustrating a memory system 1000 in accordance with an embodiment of the present invention.

8, the memory system 1000 includes a semiconductor memory device 1100 and a controller 1200. [

The semiconductor memory device 1100 includes a memory cell array 1100, an address decoder 1120, a read and write circuit 1130, a voltage generator 1140 and control logic 1150. Except for the control logic 1150, the memory cell array 1100, the address decoder 1120, the read and write circuit 1130 and the voltage generator 1140 are connected to the memory cell array 110, The address decoder 120, the read and write circuit 130, and the voltage generator 140. Hereinafter, a duplicate description will be omitted.

The control logic 1150 controls all operations of the semiconductor memory device 1100. The control logic 1150 is configured to control the voltage generator 1140 under the control of the controller 1200 to change the erase bias used for the erase operation.

The controller 1200 is connected to the host (Host) and the semiconductor memory device 1100. The controller 1200 is configured to provide a control signal CTRL and an address ADDR to the semiconductor memory device 1100 and exchange data (DATA) with the semiconductor memory device 1100. In an exemplary embodiment, the control signal CTRL, address ADDR, and data DATA may be transmitted on one common channel CH.

 In response to a request from the host (Host), the controller 1200 is configured to access the semiconductor memory device 1100. For example, the controller 1200 is configured to control the read, program and erase operations of the semiconductor memory device 1100. The controller 1200 is configured to provide an interface between the semiconductor memory device 1100 and the host. The controller 1200 is configured to drive firmware for controlling the semiconductor memory device 1100.

The controller 1200 includes a register 1210. The controller 1200 is configured to count a program erase cycle of the semiconductor memory device 1100 and store the program erase cycle in the register 1210. [ The data stored in the register 1210 is stored in the meta area (for example, BLK1) of the memory cell array 1110 and the data stored in the meta area of the memory cell array 1110 when the power is turned on is Will be loaded into register 1210.

The function of determining the program erase cycle at which the erase bias is to be changed may be performed by the controller 1200. [ The controller 1200 according to the embodiment of the present invention can control the semiconductor memory device 1100 to change the erase bias used for the erase operation every time the program erase cycle reaches log scale values that increase by a certain amount have.

Further, the controller 1200 can receive the first step pulse value used in the first erase operation and the second step pulse value used in the second erase operation from the semiconductor memory device 1100 through the channel CH . If the second step pulse is greater than the first step pulse by a predetermined value (CV, see FIG. 7), the controller 1200 determines whether the erase bias is changed based on the program erase cycles corresponding to the first and second erase operations It is possible to determine the program erase cycle to be performed. For example, the difference between the log scale values of the program erase cycles corresponding to the first and second erase operations, and the difference between the program erase cycle corresponding to the second erase operation and the log scale values of the determined program erase cycle are the same . The erase bias to be changed (e.g., at least one of the start voltage level and the pulse increase amount) may be determined according to the difference in the end voltage levels of the first and second step pulses.

In an exemplary embodiment, the controller 1200 includes components such as a processing unit, a random access memory (RAM), a host interface, and a memory interface. The processing unit controls all operations of the controller 1200.

The RAM is used as at least one of an operation memory of the processing unit, a cache memory between the semiconductor memory device 1100 and the host, and a buffer memory between the semiconductor memory device 1100 and the host. At this time, the function of the register 1210 of Fig. 8 can be performed by the RAM (RAM).

The host interface includes a protocol for performing data exchange between the host (Host) and the controller 1200. As an exemplary embodiment, the controller 1200 may be implemented using a universal serial bus (USB) protocol, a multimedia card (MMC) protocol, a peripheral component interconnection (PCI) protocol, a PCI- Through at least one of various interface protocols such as a protocol, a Serial-ATA protocol, a Parallel-ATA protocol, a small computer small interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, (Host). The memory interface interfaces with the semiconductor memory device 1100. For example, the memory interface includes a NAND interface or a NOR interface.

The memory system 1000 may be further configured to include error correction blocks. The error correction block is configured to detect and correct errors in data read from the semiconductor memory device 1100 using an error correction code (ECC). In an exemplary embodiment, the error correction block is provided as a component of the controller 1200. In another embodiment, the error correction block may be provided as a component of the semiconductor memory device 1100.

The controller 1200 and semiconductor memory device 1100 may be integrated into one semiconductor device. In an exemplary embodiment, the controller 1200 and the semiconductor memory device 1100 may be integrated into one semiconductor device to form a memory card. For example, the controller 1200 and the semiconductor memory device 1100 may be integrated into a single semiconductor device and may be a PC card (PCMCIA), a compact flash card (CF), a smart media card (SM, SMC ), A memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), and a universal flash memory device (UFS).

The controller 1200 and the semiconductor memory device 1100 may be integrated into a single semiconductor device to form a solid state drive (SSD). A semiconductor drive (SSD) includes a storage device configured to store data in a semiconductor memory. When the memory system 1000 is used as a semiconductor drive (SSD), the operating speed of the host connected to the memory system 1000 is dramatically improved.

As another example, memory system 1000 may be a computer, an Ultra Mobile PC (UMPC), a workstation, a netbook, a personal digital assistant (PDA), a portable computer, a web tablet, A mobile phone, a smart phone, an e-book, a portable multimedia player (PMP), a portable game machine, a navigation device, a black box (black) a digital audio recorder, a digital audio player, a digital picture recorder, a digital video recorder, a digital video recorder, a digital video player, a digital video player, a device capable of transmitting and receiving information in a wireless environment, one of various electronic devices constituting a home network, a computer network,Any of a variety of electronic devices that comprise, there is provided in one of any of a variety of electronic devices constituting a telematics network, RFID device, or varied the various components of the electronic device, such as one of the elements that make up the computing system.

As an exemplary embodiment, semiconductor memory device 1100 or memory system 1000 may be implemented in various types of packages. For example, the semiconductor memory device 1100 or the memory system 1000 may include a package on package (PoP), ball grid arrays (BGAs), chip scale packages (CSPs), plastic leaded chip carriers (PDIP), Die in Waffle Pack, Die in Wafer Form, Chip On Board (COB), Ceramic Dual In Line Package (CERDIP), Plastic Metric Quad Flat Pack (MQFP), Thin Quad Flatpack SOIC), Shrink Small Outline Package (SSOP), Thin Small Outline (TSOP), Thin Quad Flatpack (TQFP), System In Package (SIP), Multi Chip Package (MCP), Wafer-level Fabricated Package Level Processed Stack Package (WSP) or the like.

FIG. 9 is a block diagram illustrating a computing system 2000 that includes the memory system 1000 of FIG.

9, a computing system 2000 includes a central processing unit 2100, a random access memory (RAM) 2200, a user interface 2300, a power supply 2400, and a memory system 1000 .

The memory system 1000 is electrically coupled to the central processing unit 2100, the RAM 2200, the user interface 2300, and the power source 2400 via the system bus 2500. Data that is provided through the user interface 2300 or processed by the central processing unit 2100 is stored in the memory system 1000.

In FIG. 9, the semiconductor memory device 1100 is shown connected to the system bus 2500 through a controller 1200. However, the semiconductor memory device 1100 can be configured to be connected directly to the system bus 2500. At this time, the function of the controller 1200 will be performed by the central processing unit 2100. Then, the function of the register 1210 will be performed by the RAM 2200. [

While the invention has been shown and described with reference to certain preferred embodiments thereof, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention. Therefore, the scope of the present invention should not be limited to the above-described embodiments, but should be determined by the equivalents of the claims of the present invention as well as the claims of the following.

110: memory cell array
120: address decoder
130: Read and Write Circuit
140: Voltage generator
150: control logic
151: Register
Vstr: Starting voltage
Vd: pulse increase amount
Vend: Termination voltage

Claims (9)

A method of operating a semiconductor memory device for storing and erasing data in accordance with a program operation and an erase operation, the method comprising:
Changing the level of the erase bias to be used for the erase operation every time a program erase cycle reaches a log scale value that increases in a constant unit,
The change of the level of the erase bias may be performed,
The erase operation being performed with respect to a voltage level of the first of the erase pulses used in the erase operation, or with respect to a voltage difference between the erase pulses. Store the value of the first step pulse used in the erase operation when the program erase cycle reaches the first threshold value;
Storing a value of a second step pulse used in an erase operation when the program erase cycle reaches a second threshold value;
And changing the level of the erase bias based on the difference of the first and second step pulses when the program erase cycle reaches a third threshold,
Wherein the difference between the log scale values of the second and third thresholds and the log scale values of the first and second thresholds are the same. 3. The method of claim 2,
Wherein an erase operation after the program erase cycle reaches the third threshold value is performed using the level of the modified erase bias. A memory cell array including a plurality of memory cells; And
Configured to count the program erase cycles of the memory cell array and to change the level of the erase bias to be used in the erase operation for the memory cell array each time the program erase cycle reaches a log scale value that increases by a certain magnitude, Circuit,
The change of the level of the erase bias may be performed,
Wherein the erase operation is performed with respect to a voltage level of a first one of erase pulses used in the erase operation, or with respect to a voltage difference between the erase pulses. Storing a value of a first step pulse used in a first erase operation;
Determining whether the second step pulse used in the second erase operation is larger than the first step pulse by a predetermined value;
And determining a program erase cycle in which the level of the erase bias is to be changed based on the log scale values of the program erase cycles corresponding to the first and second erase operations in accordance with the determination result . 6. The method of claim 5,
The difference between the log scale values of the program erase cycles corresponding to the first and second erase operations and the difference between the program erase cycles corresponding to the second erase operation and the log scale values of the determined program erase cycle are the same . 6. The method of claim 5,
Change the level of the erase bias based on the difference of the first and second stepped pulses;
And performing an erase operation corresponding to the determined program erase cycle using the level of the altered erase bias. A nonvolatile memory including a plurality of memory cells; And
And a peripheral circuit configured to count a program erase cycle of the nonvolatile memory,
Wherein when the first step pulse is used in the first erase operation and the second step pulse used in the second erase operation is larger than the first step pulse by a predetermined value, And to determine a program erase cycle at which the level of the erase bias is to be changed based on the log scale values of the program erase cycles. delete

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