KR101925565B1 - ELO method using crack pattern - Google Patents

ELO method using crack pattern Download PDF

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KR101925565B1
KR101925565B1 KR1020160184217A KR20160184217A KR101925565B1 KR 101925565 B1 KR101925565 B1 KR 101925565B1 KR 1020160184217 A KR1020160184217 A KR 1020160184217A KR 20160184217 A KR20160184217 A KR 20160184217A KR 101925565 B1 KR101925565 B1 KR 101925565B1
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epilayer
semiconductor substrate
silicon
pattern
epi
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KR1020160184217A
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Korean (ko)
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KR20180079600A (en
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오세웅
신찬수
최재혁
이규범
박원규
이태영
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(재)한국나노기술원
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Priority to PCT/KR2017/000636 priority patent/WO2018124366A1/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/7806—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices involving the separation of the active layers from a substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02293—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process formation of epitaxial layers by a deposition process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices

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  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
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  • Manufacturing & Machinery (AREA)
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Abstract

Disclosed herein is a method for isolating an epilayer from a semiconductor substrate, the method comprising: forming a pattern on the semiconductor substrate to determine a crack array of the epilayer; A second step of growing an epitaxial layer on the semiconductor substrate on which the pattern is formed, a third step of forming a cracking array in the epi layer in correspondence with the pattern, and a third step of etching the cracks of the epi layer And separating the epilayer from the semiconductor substrate by forming a fluid channel that penetrates the solution to provide a path through which the etchant solution can penetrate the epilayer along the cracking arrangement. And a method of separating an epi layer using a crack pattern as a technical point. Accordingly, the present invention has an advantage in that a cracking pattern is formed on a semiconductor substrate, thereby forming a fluid channel that provides a path through which the etching solution can penetrate into the epi layer, thereby quickly separating the epi layer from the semiconductor substrate.

Description

ELO method using crack pattern "

The present invention relates to a method for separating an epilayer from a semiconductor substrate, which forms a cracking pattern on a semiconductor substrate to form a fluid channel that provides a path through which the etching solution can penetrate into the epilayer, And a method of separating an epi layer using a crack pattern for separating the epi layer.

In the field of heterogeneous epitaxial growth, a technical approach is needed to obtain a high quality epilayer by material misc synthesis between the epi layer and the substrate.

Particularly, the thermal expansion coefficient difference between the epi layer and the substrate is subjected to severe tensile or compressive stress on the epi layer when the temperature is lowered from room temperature to the epi growth temperature. At this time, when the thermal expansion coefficient of the epi layer is large, the epi layer undergoes tensile stress, and cracks appear in the epi layer when subjected to a tensile stress exceeding the critical value.

FIG. 1 and FIG. 2 show cracks according to the difference in thermal expansion coefficient when an epi layer based on a compound semiconductor is formed on a silicon-based substrate.

Thus, a device using a compound semiconductor using a conventional silicon-based substrate has cracks due to a difference in thermal expansion coefficient between the substrate and the epi layer grown thereon, and such cracks generally occur in [110], [1-10 ] Direction, and the time at which the cracks are observed appears when the thickness of the epi-thin film grown on the substrate exceeds the critical thickness. This is because as the thickness of the epi-thin film increases, the elastic deformation energy corresponding to the difference in thermal expansion coefficient accumulates.

On the other hand, the epitaxial lift-off technique (ELO) is a process in which epitaxial layers are separated from each other during the epitaxial layer separation process, There is a further delay problem.

In addition, the epitaxial layer separation technique is in the growth of heteroepitaxial layer, and its main purpose is to form a large particle, but the process time increases with increasing the size of the substrate.

Therefore, the separation of the epi layer is an important concern in shortening the process time. In some cases, a hydrophilic etching solution is used as the prior art. In this case, however, the penetration of the etching solution is supplied only on the side surface, , There is a limit to shortening the ELO process time.

In addition, although a technique of rapidly separating the epi layer by applying a constant physical force is shown, it is difficult to control the precise weight, and there is a problem that damage is caused by the physical thin film of the epi layer in this process.

The present invention relates to an epilayer separation method using a cracking pattern for quickly separating an epilayer from a semiconductor substrate by forming a fluid channel that provides a path through which an etching solution can penetrate into an epilayer as a cracking pattern is formed on a semiconductor substrate The purpose of that is to provide.

According to another aspect of the present invention, there is provided a method of separating an epi layer of a heterogeneous material from a semiconductor substrate, the method comprising: a first step of forming a pattern for determining a crack array of the epi layer on the semiconductor substrate; A second step of growing an epitaxial layer on the semiconductor substrate on which the pattern is formed, a third step of forming a cleavage array in the epi layer in correspondence to the pattern, and a third step of impregnating the etching solution into the crack- And a fourth step of separating an epilayer from the semiconductor substrate by forming a fluid channel that provides a path through which the etching solution penetrates the epilayer along a cracking arrangement. The layer separating method is a technical point.

The present invention also provides a method of separating an epi layer of a heterogeneous material from a silicon based epi-thin film semiconductor substrate, comprising the steps of: (a) forming a pattern for determining a crack array of the epi-film on the silicon; (B) growing an epitaxial layer on the silicon on which the pattern is formed; (c) forming a cleavage array in the epitaxial layer in correspondence with the pattern; (c) forming an epitaxial layer on the epilayer (D) forming a fluid channel to penetrate the etch solution into the cracked array of the epilayed film to provide the epilayed film and the epilayer along the cracks, And separating the epi layer from the silicon based epi-thin film semiconductor substrate. The epitaxial layer separation method is another technical point.

Here, the semiconductor substrate is preferably any one of silicon, GaN, GaAs, and SiC.

It is preferable that the pattern formed on the semiconductor substrate or the pattern formed on the silicon is formed in a directional form with respect to the stress generated between the semiconductor substrate and the epi layer, It is preferable to form it in a form in which it can be formed.

Also, it is preferable that a sacrificial layer is formed on the silicon-based epilayer before forming the epilayer on the epilayer, and an epilayer is grown on the sacrificial layer to form an epitaxial layer and an epilayer It is preferable that fluid channels corresponding to the above-described cracks are formed, respectively.

Meanwhile, the fluid channel formed in the epi layer may replace an isolation process in manufacturing an array type device.

The present invention has the effect of rapidly separating an epilayer from a semiconductor substrate by forming a fluid channel that provides a path through which an etchant can penetrate into the epilayer as a cracking pattern is formed on a semiconductor substrate.

Also, as the wet etching proceeds along the fluid channel, the etching region of the semiconductor substrate, the silicon including the sacrificial layer, the epilayer or the epilayer is quickly exposed, so that the separation of the epilayer from the semiconductor substrate is smooth, An epi layer is provided and an ELO process reproducibility is excellent.

Also, by separating the high quality semiconductor substrate by the fast ELO process, the semiconductor substrate can be reused and the process cost is reduced.

In addition, since the fluid channel according to the present invention forms an array at a periphery thereof rather than a region that operates as an element, it is possible to replace the isolation process when manufacturing an array type device, Thereby simplifying the process and improving the stability of the process.

As a result, the etching process time can be shortened due to the penetration of the etching solution through the fluid channel, and the separation time can be shortened while minimizing damage to the semiconductor substrate or the epi layer, .

FIG. 1 is a view showing a crack according to a difference in thermal expansion coefficient when an epi layer based on a compound semiconductor is formed on a silicon-based substrate. FIG.
FIG. 2 is a cross-sectional view (a) and a perspective view (b) showing a pattern formed on a semiconductor substrate according to an embodiment of the present invention.
FIG. 3 is a top view schematically showing a case where a cracked array is formed in an epi layer manufactured according to an embodiment of the present invention. FIG.
Figure 4 is a cross-sectional schematic diagram of a device with a fluid channel formed in accordance with another embodiment of the present invention.
5 is a cross-sectional view of a device having a fluid channel formed therein according to the embodiment of FIGS. 5 through 4. FIG.
FIGS. 6 to 4 are data obtained by measuring the silicon substrate-based epilayem semiconductor substrate separation time and the width of the fluid channel according to the etching time in the device having the fluid channel according to the embodiment of FIGS.

The present invention relates to a method for separating an epilayer from a semiconductor substrate, which forms a cracking pattern on a semiconductor substrate to form a fluid channel that provides a path through which the etching solution can penetrate into the epilayer, And a method of separating an epi layer using a crack pattern for separating the epi layer.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings. FIG. 2 is a cross-sectional view (a) and a perspective view (b) showing a pattern formed on a semiconductor substrate according to an embodiment of the present invention, and FIG. 3 is a cross- FIG. 4 is a cross-sectional schematic view of a device having a fluid channel according to another embodiment of the present invention, FIG. 5 is a cross-sectional view of a device having a fluid channel formed according to the embodiment of FIG. And FIG. 6 is a data obtained by measuring the separation time of the silicon-based epilayem semiconductor substrate and the width of the fluid channel according to the etching time in the device having the fluid channel according to the embodiment of FIG.

As shown in the figure, the method for separating an epi layer using a cracking pattern according to the present invention is a method for separating an epi layer 200 of a dissimilar material from a semiconductor substrate 100, A first step of forming a pattern 110 for determining a crack array L of the layer 200 and a second step of forming an epitaxial layer 200 on the semiconductor substrate 100 on which the pattern 110 is formed A third step of forming a cracking arrangement L in the epilayer 200 in correspondence to the pattern 110 and a third step of forming an etch solution L in the cracks L of the epilayer 200, A fluid channel 300 is formed in the epitaxial layer 200 along the cleavage array L to provide a path through which the etchant can penetrate the epitaxial layer 200 to form an epitaxial layer 200 from the semiconductor substrate 100 And a fourth step of separating the liquid.

A pattern 110 is formed on the semiconductor substrate 100 to determine a cracking arrangement L of the epi layer 200 in a first step and a semiconductor substrate 100 having the pattern 110 formed thereon, The epitaxial layer 200 is grown on the epitaxial layer 200 in the epitaxial layer 200 according to the pattern 110. In the third step,

Here, the semiconductor substrate 100 may be made of any one of silicon, GaN, GaAs, and SiC, and various types of substrates may be used depending on the type of device to be implemented. The epitaxial layer 200 deposited on the semiconductor substrate 100 is formed of a different material from the semiconductor substrate 100.

Generally, when an epi layer 200 of a heterogeneous material is grown on a semiconductor substrate 100, cracks are generated due to a difference in thermal expansion coefficient between the semiconductor substrate 100 and the epi layer 200 grown thereon .

This crack formation is caused by the elastic strain due to the lattice constant at the growth temperature and the lattice constant at the room temperature being different from each other, and as the thickness of the epi layer 200 increases, the elasticity due to the difference in the thermal expansion coefficient The energy due to deformation gradually increases, and this energy is propagated to the place where the stress is concentrated in the crystal, so that a crack is formed in the epi layer 200.

Therefore, since the cracks are formed in a direction in which stress is concentrated depending on the types of the semiconductor substrate 100 and the epi-layer 200, when the pattern 110 is to be formed on the semiconductor substrate 100, Respectively.

That is, the pattern 110 formed on the semiconductor substrate 100 is formed in a directional form with respect to the stress generated by the difference in lattice constant between the semiconductor substrate 100 and the epi layer 200 grown thereon desirable.

The pattern 110 formed on the semiconductor substrate 100 is formed in a specific crystal orientation depending on the type of the semiconductor substrate 100 and the epi-thin film 120, since the stress is generally concentrated in a specific crystal direction.

For example, as shown in FIG. 2, when the semiconductor substrate 100 is made of silicon or GaAs, cracks are formed in the [110] direction and the [1-10] direction, The crack array L formed in the epi layer 200 is controlled in the direction of the pattern 110 as shown in FIG. 3, 110] direction and the [1-10] direction.

As described above, according to the present invention, the pattern 110 is formed on the semiconductor substrate 100 in consideration of the cracking direction, so that the cracking arrangement L in the epi layer 200 is formed in the pattern 110 so that the direction and position thereof can be controlled.

Therefore, in the semiconductor substrate 100 according to the present invention, a pattern 110 is formed with respect to a specific crystal direction in which stress can be concentrated on the semiconductor substrate 100 along the direction of the lattice arrangement L of the epilayed film 120 Thereby inducing the stress to be concentrated around the pattern 110.

Here, when the semiconductor device is fabricated in a cell unit, the spacing and arrangement of the patterns 110 formed on the semiconductor substrate 100 are formed so that the cracks L are formed as regions in which the devices do not function as devices Decide.

A fluid channel (not shown) is provided to penetrate the etching solution into the cracks L of the epi layer 200 to provide a path through which the etch solution can penetrate the epi layer 200 along the cracks L 300 are formed to separate the epi layer 200 from the semiconductor substrate 100 (step 4).

That is, the epitaxial layer 200 on which the cracking pattern 110 is formed is grown on the semiconductor substrate 100 and the cracked array L is formed. The epitaxial layer 200 is separated into the semiconductor substrate 100, As shown in FIG. 3, as the etching solution is infiltrated along the cracks L of the epi layer 200 at the moment of dipping in the wet etching solution, the semiconductor substrate 100 or the entire region of the epi layer 200, the fluid channel 300 is formed in the epi layer 200 at the same time.

The wet etching proceeds with the etching solution being infiltrated along the fluid channel 300 so that the etching region of the semiconductor substrate 100 and the epi layer 200 is quickly exposed to form an epi layer 200 Can be smoothly separated.

As a result, the etch process time can be shortened due to the rapid penetration of the etching solution through the fluid channel 300, the separation time can be shortened while minimizing damage to the semiconductor substrate 100 or the epi layer 200, The present invention is also applicable to a substrate.

In another embodiment of the present invention, there is provided a method of separating an epilayer 200 of a heterogeneous material from a silicon-based epi-thin film 120 semiconductor substrate 100, the method comprising: (a) forming a pattern 110 for determining a crack array (L), (b) growing an epilayed film 120 on the silicon on which the pattern 110 is formed, Forming an epilayer 200 on the epilayed film 120 by forming a slit array L in the epilayed film 120 corresponding to the epilayed film 120; (L) of the etching solution to penetrate the etching solution into the cracking arrangement (L) of the etching solution (120) to form the epilayer (120) and the epilayer (200) (E) forming an epitaxial layer (200) from the silicon-based epi-thin film (120) semiconductor substrate (100) And a step of separating the liquid from the liquid.

That is, the semiconductor substrate 100 is a silicon-based epi-thin film 120 semiconductor substrate. In this case, a pattern 110 for determining a cracking arrangement L of the epilayed film 120 is formed on the silicon and a cracking arrangement L corresponding to the pattern 110 is formed on the epilayed film 120 , Which is used as a heterogeneous substrate in the ELO process.

The epitaxial layer 120 is formed on the epi-thin film 120 using the epi-thin film 120 on which the silicon-based cleavage array L is formed as a semiconductor substrate 100. In this case, a separate slit L is formed in the epilayed film 120 according to the slit L of the epilayed film 120.

The etch solution is infiltrated into the cleavage array L of the epilun film 120 so that the epilayer 120 and the epilayer 200 along the cleavage array L are allowed to penetrate the etching solution The epi-layer 200 is separated from the silicon-based epi-thin film 120 semiconductor substrate 100 by forming a fluid channel for providing the fluid channel.

A sacrificial layer 130 is formed on the silicon-based epilayed film 120 before the epilayer 200 is formed on the epilayed film 120. An epitaxial layer 130 is formed on the sacrificial layer 130, The fluid channels 300 corresponding to the cracks L are formed on the epilayers 120 and the epilayer 200 on the upper and lower portions of the sacrificial layer 130 by growing the sacrificial layer 200.

The pattern 110 formed on the silicon is formed in a directional form with respect to the stress generated between the silicon and the epi-thin film 120 in the same manner as described above, and can be stressed in a specific crystal direction It is preferable to form it into a shape.

As the wet etching proceeds along the fluid channel 300, the etch regions of the silicon, the epilayers 120 and the epilayers 200 including the sacrificial layer 130 are quickly exposed to form the silicon-based epilayers 120), the epi layer 200 can be smoothly separated from the semiconductor substrate 100.

As a result, the etching process time can be shortened due to the penetration of the rapid etching solution through the fluid channel 300 and the separation of the silicon-based epi-thin film 120 and the epi-layer 200 can be minimized The time can be shortened and the present invention can be applied to a large-sized substrate.

FIG. 4 is a cross-sectional view of a silicon-based epi-thin film 120 according to an embodiment of the present invention. Referring to FIG. 4, the semiconductor substrate 100 includes GaAs as an epilayer 120, AlAs as a sacrificial layer 130, ) 200, GaInP is used.

4, fluid channels 300 are formed in the epilayer 120 and the epilayer 200 at the upper and lower portions of the sacrificial layer 130, respectively, so that the sacrificial layer 130 and the etched region are exposed Thereby separating the epi layer 200 from the silicon-based epi-thin film 120 semiconductor substrate 100 quickly.

FIG. 5 is a graph showing the relationship between the growth rate of GaAs (AlAs) 130, GaAs 200, and GaInP grown on the silicon substrate epitaxial layer 120 manufactured according to the embodiment of FIG. , And H 3 PO 4 : H 2 O 2 : DI = 2: 1: 5 for 3 minutes.

As shown in FIG. 5, it can be confirmed that a fluid channel 300 is formed in each of the epilayer 120 and the epilayer 200 around the sacrificial layer (AlAs) 130.

FIG. 6 is a graph illustrating the relationship between the separation time of the silicon-based epi-thin film 120 and the width of the fluid channel 300 in the device having the fluid channel 300 according to the embodiment of FIG. to be.

As can be seen, the longer the etch time, the greater the width of the fluid channel 300 and the shorter the total ELO process time. In general, the 4-inch semiconductor substrate 100 requires an ELO process time of about 25 hours, but according to the present invention, it takes about 6 hours.

Meanwhile, the separated epi layer 200 may be transferred or bonded to a separate substrate and used as a device for various purposes. The semiconductor substrate 100 or the silicon-based epi thin film separated from the epi layer may be reused, . Here, another etch resistant film (for example, GaInP having a high etch selectivity relative to the epitaxial layer) may be further formed in the region where the cracks (L) of the silicon-based epilayers are formed to minimize defects in the epi- can do.

In addition, the fluid channel 300 formed in the epi layer in accordance with the present invention may replace an isolation process when fabricating an array type device. That is, by considering the element formation region when forming the cracked array L, the fluid channel 300 can be substituted for the isolation process, while preventing cracks in the element region.

Since the fluid channel 300 is formed not in the region where the device operates but in the periphery thereof, it is possible to replace the isolation process in manufacturing an array type device, thereby eliminating the need for an isolation process The process can be simplified and the process stability can be enhanced.

Accordingly, the present invention is for rapidly separating an epilayer from a semiconductor substrate by forming a fluid channel that provides a path through which an etching solution can penetrate into an epilayer as a cracking pattern is formed on a semiconductor substrate.

Also, as the wet etching proceeds along the fluid channel, the etching region of the semiconductor substrate, the silicon including the sacrificial layer, the epilayer or the epilayer is quickly exposed, so that the separation of the epilayer from the semiconductor substrate is smooth, Providing an epi layer and an ELO process reproducibility.

Also, by separating the high quality semiconductor substrate by the fast ELO process, the semiconductor substrate can be reused and the process cost is reduced.

In addition, since the fluid channel according to the present invention forms an array at a periphery thereof rather than a region that operates as an element, it is possible to replace the isolation process when manufacturing an array type device, Thereby simplifying the process and enhancing the stability of the process.

As a result, the etching process time can be shortened due to the penetration of the etching solution through the fluid channel, and the separation time can be shortened while minimizing damage to the semiconductor substrate or the epi layer, .

100: semiconductor substrate 110: pattern
120: epilayer 130: sacrificial layer
200: Epi layer 300: Fluid channel
L: Arrangement

Claims (9)

delete delete delete delete A method for separating an epilayer of a heterogeneous material from a silicon-based epitaxial semiconductor substrate,
(A) forming a pattern on the silicon to determine a crack array of the epilayed film;
Growing (b) growing an epilayer on the patterned silicon;
(C) forming a cracking array in the epilayed film corresponding to the pattern;
(D) forming an epi layer on the epi-thin film;
Forming a fluid channel to penetrate the etching solution into the cracked arrangement of the epilayer to provide the epilayer and the epilayer along the cracks to provide a path through which the etching solution can penetrate;
And separating the epi layer from the silicon based epi-thin film semiconductor substrate. 6. The method of claim 5, further comprising forming a sacrificial layer on top of the silicon-based epilayed film and growing an epilayer on top of the sacrificial layer prior to forming the epilayer on the epilayed film,
Wherein a fluid channel corresponding to the cracks is formed in the epilayer and the epilayer of the upper and lower portions of the sacrificial layer, respectively. 6. The method of claim 5, wherein the pattern formed on the silicon comprises:
Wherein the silicon nitride film is formed in a directional form with respect to a stress generated between the silicon and the epilayed film. 8. The method of claim 7, wherein the pattern formed on the silicon comprises:
Wherein the first and second cladding layers are formed in a shape capable of receiving stress in a specific crystal direction. 9. A method according to any one of claims 5 to 8, wherein the fluid channel formed in the epi layer is capable of replacing an isolation process when fabricating an array type device. Lt; / RTI >
KR1020160184217A 2016-12-30 2016-12-30 ELO method using crack pattern KR101925565B1 (en)

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KR1020160184217A KR101925565B1 (en) 2016-12-30 2016-12-30 ELO method using crack pattern
PCT/KR2017/000636 WO2018124366A1 (en) 2016-12-30 2017-01-19 Method for separating epitaxial layer by using crack pattern

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