KR101918102B1 - Leaky integrate-and-fire neuron circuit based on floating-gate integrator and neuromorphic system including the same, method for controlling the neuron circuit - Google Patents

Abstract

A highly integrated, low power consumption artificial neuron circuit using a floating gate integrator comprises a first tunnel junction element sharing a floating gate and a second tunnel junction element, the floating gate integrating a floating gate floating-gate, FG) integrator; A voltage amplifier for adjusting the gate voltage of the transistor to amplify the floating gate voltage output from the floating gate integrator; A voltage output unit for amplifying the output voltage of the voltage amplifier again to generate a spike voltage; And a polarity reverser for applying the spike voltage to the gate to invert the polarity of the spike voltage and to apply charge to the second tunnel junction element to reset the charge of the floating gate. Thus, it is possible to manufacture an artificial neuron element which is easy to control and has a high degree of integration.

Description

TECHNICAL FIELD [0001] The present invention relates to a highly integrated low power consumption artificial neuron circuit using a floating gate integrator, a neuromorphic system including the same, a control method thereof, and a control method thereof. BACKGROUND ART CIRCUIT}

The present invention relates to a highly integrated low power consumption artificial neuron circuit and a neuromorphic system using a floating gate integrator and a control method thereof and more particularly to a neuron morphic system using a floating gate integrator which is a language for signal transmission between artificial neurons in a neuro- To an artificial neuron element serving to generate an action potential.

There are hundreds of billions of neurons (ie, neurons) in the brain, and they are composed of complex neural networks. Neurons exert their intellectual abilities such as learning and memory through synapses that send and receive signals with thousands of other neurons. Neurons are the structural and functional unit of the nervous system and the basic unit of information transmission.

Synapse refers to the junction between neurons and refers to the site where the axons of one neuron are connected to the dendrites of other neurons. In other words, a neuron is made up of synapses with thousands of other neurons. By creating neurons at the level of the neurons that mimic biological neuronal systems, you can create a way to simulate the brain's processing of information and store new types of information processing and storage devices.

The Nyomoplite system is a semiconductor circuit that imitates the action of the nervous system and can be used to implement an intelligent system that can adapt itself to an unspecified environment.

However, the spiking operation frequency of the conventional artificial neuron device is mainly determined by the capacitance of the battery. To realize the frequency of an artificial neuron device similar to an actual neuron, a huge capacitance of tens of picofarads is required. In addition, since a capacitor having a very large area is required to secure the required capacitance, there is a difficulty in integrating the unit artificial neuron elements.

KR 10-2014-0144130A KR 10-2016-0010477 A US 2016-0110644A

Accordingly, it is an object of the present invention to provide a highly integrated low power consumption artificial neuron circuit using a floating gate integrator having a high degree of integration.

It is another object of the present invention to provide a neuromorphic system comprising a highly integrated low power consumption artificial neuron circuit using the floating gate integrator.

It is still another object of the present invention to provide a method of controlling a highly integrated low power consumption artificial neuron circuit using the floating gate integrator.

A highly integrated low power consumption artificial neuron circuit using a floating gate integrator according to one embodiment for realizing the object of the present invention includes a first tunnel junction element sharing a floating gate and a second tunnel junction element, A floating-gate (FG) integrator that adjusts the charge of the floating gate using a phenomenon; A voltage amplifier for adjusting the gate voltage of the transistor to amplify the floating gate voltage output from the floating gate integrator; A voltage output unit for amplifying the output voltage of the voltage amplifier again to generate a spike voltage; And a polarity reverser for applying the spike voltage to the gate to invert the polarity of the spike voltage and to apply charge to the second tunnel junction element to reset the charge of the floating gate.

In an embodiment of the present invention, the highly integrated low power consumption artificial neuron circuit using the floating gate integrator can inject charge into the floating gate using the tunneling phenomenon of the first tunnel junction element and the second tunnel junction element have.

In an embodiment of the present invention, the highly integrated low power consumption artificial neuron circuit using the floating gate integrator can control the thickness of the tunneling barrier of the first tunnel junction element to control the charge relaxation time of the floating gate.

In an embodiment of the present invention, the thicker the tunneling barrier of the first tunnel junction element, the less time the charge of the floating gate is relaxed.

In an embodiment of the present invention, the floating gate integrator may include a transistor that uses the floating gate electrode as a gate electrode, and controls a channel electrical conductivity to control an input voltage of a gate of the voltage amplifier.

In an embodiment of the present invention, the spike voltage output from the voltage output may have an action potential of less than 100 Hz.

In an embodiment of the present invention, the voltage output unit may include a positive feedback capacitor.

The neuromorphic system according to an embodiment of the present invention for realizing another object of the present invention is formed by connecting a plurality of highly integrated low power consumption artificial neuron circuits using the floating gate integrator.

In an embodiment of the present invention, the input voltages of the artificial neuron circuits may be input simultaneously.

In an embodiment of the present invention, the input voltages of the artificial neuron circuits may each be input arbitrarily.

A floating-gate (FG) integrator including a first tunnel junction element and a second tunnel junction element sharing a floating gate according to an embodiment of the present invention; A voltage amplifier for amplifying the floating gate voltage output from the floating gate integrator; A voltage output unit for amplifying the output voltage of the voltage amplifier again to generate a spike voltage; And a polarity reverser applied to the gate to reverse the polarity of the spike voltage and applied to the second tunnel junction element to reset the charge of the floating gate, wherein the floating gate integrator is a highly integrated low- A method of controlling a neuron circuit includes injecting a charge into the floating gate using a tunneling phenomenon of the first tunnel junction element and the second tunnel junction element; Adjusting a charge of the floating gate using a charge relaxation phenomenon of the first tunnel junction element; And controlling the thickness of the tunneling barrier of the first tunnel junction element to adjust the charge relaxation time of the floating gate.

In an embodiment of the present invention, the thicker the tunneling barrier of the first tunnel junction element, the less time the charge of the floating gate is relaxed.

In an embodiment of the present invention, the control method of the highly integrated low power consumption artificial neuron circuit using the floating gate integrator further includes controlling the gate voltage of the transistor included in the voltage amplifier to control the characteristic of the voltage amplitude .

In an embodiment of the present invention, in the method of controlling a highly integrated low power consumption artificial neuron circuit using the floating gate integrator, the floating gate integrator further comprises a transistor using the floating gate electrode as a gate electrode, And controlling the input voltage of the gate of the voltage amplifier by controlling the conductivity.

In an embodiment of the present invention, the spike voltage output from the voltage output may have an action potential of less than 100 Hz.

In an embodiment of the present invention, in the method of controlling a highly integrated low power consumption artificial neuron circuit using the floating gate integrator, the voltage output unit may further include positive feedback including a capacitor.

According to the highly integrated low power consumption artificial neuron circuit using the floating gate integrator, there is no significant correlation between the signal relaxation time of the integrator and the area of the integrator, unlike the battery used for setting the range of the conventional artificial neuron device activity range. It is possible to fabricate an artificial neuron device. In addition, since the artificial neuron circuit according to the present invention has a low charge injection operating voltage due to the floating gate, unlike conventional flash memories, very high reliability can be secured.

In addition, since the floating gate charge control in the artificial neuron circuit according to the present invention is implemented using a separate tunnel junction element, it is possible to include a plurality of charge control tunnel junction elements for realizing a spatial integration function in a real neural network. Further, in the artificial neuron circuit according to the present invention, the input signal is amplified through two-stage voltage amplification, and the floating gate on which the charge is recorded can be erased using the amplified voltage polarity reverser.

The artificial neuron circuit according to the present invention controls the charge relaxation time of the floating gate by using the thickness of the tunneling barrier and the height of the energy barrier of the charge control tunnel junction element so that the area of the floating gate does not greatly affect the charge relaxation time. Therefore, it is possible to fabricate an artificial neuron element circuit with a high degree of integration.

FIG. 1 is a highly integrated low power consumption artificial neuron circuit using a floating gate integrator according to an embodiment of the present invention.
FIG. 2 (a) is an equivalent circuit of the floating gate integrator according to the present invention, and FIG. 2 (b) is a graph showing the charge relaxation time according to the thickness of the tunnel barrier of the tunnel junction element.
3 (a) and 3 (b) are graphs showing the characteristics of the polarity reversal of FIG.
4 is a graph illustrating output characteristics when a DC voltage is input to the artificial neuron circuit according to the present invention.
FIG. 5 is a graph illustrating an output characteristic when a spiking voltage is input to the artificial neuron circuit according to the present invention.
6 is a graph showing circuit characteristics according to parameters of the artificial neuron circuit according to the present invention.
7 is a graph showing power consumption of the artificial neuron circuit according to the present invention.

The following detailed description of the invention refers to the accompanying drawings, which illustrate, by way of illustration, specific embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. It should be understood that the various embodiments of the present invention are different, but need not be mutually exclusive. For example, certain features, structures, and characteristics described herein may be implemented in other embodiments without departing from the spirit and scope of the invention in connection with an embodiment. It is also to be understood that the position or arrangement of the individual components within each disclosed embodiment may be varied without departing from the spirit and scope of the invention. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is to be limited only by the appended claims, along with the full scope of equivalents to which such claims are entitled, if properly explained. In the drawings, like reference numerals refer to the same or similar functions throughout the several views.

Hereinafter, preferred embodiments of the present invention will be described in more detail with reference to the drawings.

FIG. 1 is a highly integrated low power consumption artificial neuron circuit using a floating gate integrator according to an embodiment of the present invention.

The conventionally proposed technique for signal integration uses the delay time of the capacitor and resistor (RC) to control the time interval between action potentials. In this case, since a high capacitance of several tens of picofarads (pF) is required, the size of the unit artificial neuron element is very large and it is difficult to integrate the artificial neuron element because a larger electrostatic capacity is required for realizing an artificial neuron element having many connections .

Since the highly integrated low power consumption artificial neuron circuit 10 (hereinafter, artificial neuron circuit) using the floating gate integrator according to the present invention applies a floating-gate (hereinafter referred to as FG) integrator, the signal relaxation time of the integrator As shown in FIG. As a result, it is possible to fabricate an artificial neuron element having a high degree of integration, and since the charge injection operation voltage is low by FG, unlike the conventional flash memory, very high reliability can be secured.

1, an artificial neuron circuit 10 according to the present invention includes an FG integrator 100, a voltage amplifier 300, a voltage output unit 500, and a polarity inverter 700.

The artificial neuron circuit 10 is composed of twelve MOSFETs M2-M13, a single FG transistor M ₁ + C _FG and a capacitor C ₁ . The FG transistor has separate terminals MT1 and MT2 (tunnel junction elements) for programming the charge in the FG through quantum mechanical tunneling. These FG transistors are also referred to as synaptic transistors.

In the FG transistor, the additional terminal of MT1 and MT2, using a relatively thick gate oxide layer (e.g., 2.5 nm) in the FG transistor M1, provides the charge of FG through quantum mechanical tunneling through MT1 and MT2 tunnel barriers Can be controlled.

Charge transfer therethrough, in other words FG charge, is controlled along the synapse transistor at the vertical tunnel junction of the electrode-barrier-FG-barrier-electrode. In the circuit simulator, the tunnel junction can be realized by shorting the source, drain and body terminals of the MOSFET as shown in Fig. Presynaptic currents also enter the shorted terminal, and all the dielectrics used in the circuit can be SiO ₂ .

Specifically, the FG integrator 100 injects electric charge into the FG by the synapse current generated in the tunnel junction element, and is temporarily trapped. The FG potential (V _FG ) consequently changes the channel conductance of M1. Thus, the FG potential (V _FG ) parameterizes circuit integration.

The implanted charge decays simultaneously over time during synaptic current injection, which implies a leaky integral that underlies the behavior in artificial neuron neurons. Relaxation time of the FG charge is mainly determined by the capacitance, the thickness (d _{tun _ox)} and of the area C and _FG of the tunnel barrier.

The thick gate oxide of M1 scarcely interferes with the charge discharge at the time of interest. Unlike FG transistors, which are nonvolatile memory devices, the approach of the present invention aims at active use of charge / discharge dynamics.

Therefore, a charge holding time of about several seconds (sec) is required. Therefore, the circuit design and programming voltages need to be modified. The various device parameters of the FG integrator in this work are listed in Table 1. In one embodiment of the present invention, the parameters in Table 1 below were used for circuit simulation.

V _{dd +} (V) V _{dd -} (V) V _g1 (V) V _g2 (V) C _FG (f F) C1 (fF) 0.5 -0.5 0.7 0.65 6 0.15

Synaptic transistors have the advantage of using multiple input tunnel junctions to enable spatial integration, which represents the simultaneous integration of synaptic currents through other synapses.

2 (a) shows an FG integrator with _n identical input terminals MT1 _1- MT1 _n . For n = 10, the time-varying V _FG for a single-terminal input spike at 0 s was simulated, and the other nine terminals were grounded. For comparison, the same simulation was performed for n = 1. The input spike amplitude (V _in ) and width (t _sp ) are 0.5 V and 10 μs, respectively.

Figure 2 (b) is a simulation result showing a V _FG decreased have different time constants, that is, the relaxation time that depends on n and d _{_ox tun.} Relaxation time is defined as the time required for V _FG reaches 1 / e of the initial V _FG. The larger the number of input terminals, the shorter the relaxation time because each terminal operates as a charge leakage path.

In particular, the relaxation time 2.7 s for n = 1 is significantly reduced to 0.3 s for n = 10. Referring to Figure 2 (b), the solution to this reduction is to use a thicker tunnel barrier that provides a longer relaxation time.

However, when a thick tunnel barrier is used, charge injection becomes difficult when a spike arrives, so that it is difficult to secure a sufficiently large initial V _FG . Thus, the tunnel barrier thickness that matches the charge injection kinetics and charge relaxation (emission) kinetics can be selected as needed.

The voltage amplifier 300 is a non-inverting common source amplifier, which includes MOSFETs M2-M5 and forms two inverting common source signal amplifiers Amp1 with a p-MOSFET load. The input of _Amp1 (V _{amp_in} ) is controlled by the voltage drop of the M1 channel, which is determined by V _FG . That is, V _FG determines the output of Amp1.

The output of the voltage amplifier 300 is transmitted to the voltage output unit 500, that is, the next amplifier Amp2. The voltage transfer characteristic VTC of each stage of Amp1 is controlled by the constant gate voltages _Vg1 and _Vg2 . Constant gate voltages (V _g1 and V _g2 ) are important factors in designing the width and spike threshold of the output spike.

The signals output from Amp1 (V _{amp_out)} enters into Amp2, V _{amp_out} this exceeds the transition area from the VTC of Amp2 induces direct spike at the output terminal (V _out). The switching region is determined by two identical inverters (M6-M7 and M8-M9). The intermediate voltage V _out = V _{out amp_} is considered to be a threshold voltage of Amp2 for spikes.

Capacitor C1 realizes positive feedback to the input to Amp2, so that the output can be kept high until resetting the FG integrator 100. [ The reset occurs rapidly and continuously after the spike at V _out by the negative feedback achieved by the polarity inverter 700.

The FG integrator 100 needs a reset to complete a single spike. The reset is equivalent to using the electric field to clear the charge on the FG. When a negative voltage is applied to the terminal MT2, the previously injected charge disappears. Therefore, the artificial neuron circuit 10 needs a sub circuit that inverts V _out and relays it to the FG integrator 100.

The polarity inverter 700 inverts the polarity of V _out together with the negative V _dd (V _dd- ) to obtain a negative output at V _inv . Detailed circuitry of the polarity inverter 700 is shown separately in Figure 3 (a). The simulated VTC is shown in Figure 3 (b) at V _dd -0.5V. V _in in FIG. 3 (b) corresponds to V _out in FIG.

The VTC demonstrates a polarity reversal for V _in greater than the mid-voltage. Negative V _inv The pulse is induced in the polarity inverter in response to a positive V _in pulse (amplitude 0.5V and width 25μs), as can be seen in FIG. 3 (b).

If such a negative voltage pulse resets the FG integrator 100, V _FG will eventually _drop below zero. This reset process continues until V _FG is low enough that the input to each amplifier falls below the amplification threshold.

Hereinafter, the circuit operation of the artificial neuron circuit 10 of FIG. 1 will be described in more detail.

First, we verify the spike dynamics of a floating-gate-based leaky integrate-and-fire (FGLIF) neuron circuit (n = 1) under DC input mode, ie at a constant voltage equivalent to a controlled neurophysiology experiment . When a constant voltage is applied to MT1, V _FG (integration) rises due to positive charge injection to _FG , which continues until charge injection and discharge are balanced.

Therefore, the V _FG increase rate decreases greatly toward the specific V _FG level. In contrast, the RC integrator maintains this balance through charging at C and simultaneous discharging through R.

Fig. 4 (a) shows the change in V _{FG over} time during which the artificial neuron circuit 10 generates an output spike under V _in 0.26 V. Fig. Since V _FG initially rises, the channel conductance of M1 also increases. As a result, Referring to Figure 4 (b), V _{amp_out} is increased until it reaches a threshold value (about 0.29V) for a high V _out V _{amp_out} through Amp2 (500). The high _Vout is temporarily maintained in view of the positive feedback through C1.

A high V _out simultaneously triggers the polarity inverter 700 to activate the negative feedback to the FG integrator 100 and reset the FG integrator 100. Thus, since V _{amp_out} falls below the threshold value, high V _out and negative feedback end. This procedure generates a single spike and repeats for the next spike in ISI (interspike interval).

The reset rate determines the spike width. The faster the reset, the narrower the spike width. This relationship is demonstrated by an output spike width of about 25 μs and an output activity a _out (spike frequency) of about 23 Hz (see FIG. 4 (c)).

The gain function of a neuron encodes the information of a neuron and produces a distinguishable output activity for different input activities. To verify the gain function of the FGLIF neurons, the activity of the neurons was evaluated at different constant voltages (Fig. 4 (d)).

As a result, the higher the input voltage, the faster the FG charge rate in ISI, so the ISI is greatly reduced. Therefore, the activity increases greatly with the input voltage. Figure 4 (d) also shows the threshold input for spiking determined by the threshold of Amp2 500 (60, 100 and 190 mV for V _g2 = 0.60, 0.65 and 0.70 V, respectively). The exponential change in voltage is due to the tunnel current changing exponentially with the voltage.

Hereinafter, the case of the spiking input mode will be described.

The spiking input mode realizes the real situation for the operation of a FGLIF neuron in a spiking neural network (SNN). Overall, the response of FGLIF neurons is similar to the DC input mode, but with some differences. The response of the auxiliary circuit scheme to the input spike train (activity: 100 Hz, spike amplitude: 0.42 V, spike width: 25 μs) is shown in FIG. The main difference between the two modes is in integration.

Referring to FIG. 5 (a), the input spike causes a stepwise evolution of V _FG , unlike the former case. However, regardless of the input type, the FG integrator 100 successfully performs the leaky integration. Similar to the direct current input mode, V _{amp_in} is amplified through _Amp1 300 (FIG. 5 (b)) and when V _{amp_out} exceeds the threshold of Amp2 500, a spike is output at V _out c)).

Similarly, the output activity depends on the input spike amplitude and activity, as shown in Figure 5 (d). The larger the input amplitude and / or activity, the higher the output spike activity of the neuron. That is, when information transfer between synaptic neurons is called at the SNN, post-synaptic FGLIF neurons output different activities depending on the activity of pre-synaptic neurons.

The artificial neuron circuit (10) according to the present invention is capable of adjusting circuit parameters. That is, the circuit proposed in the present invention can provide a means for adjusting coupling operations such as relaxation time, spike threshold, spike width and amplitude.

Changes in the relaxation time for the tunnel barrier thickness described above are favored for thicker tunnel barriers, eg 1.5 nm for n = 10, favoring a biologically similar relaxation time scale. The resulting decrease in maximum V _FG can be compensated for by increasing the spike width. For example, d = _{tun _ox} case of 1.5 nm, is The wider the spike (100? S) is up to V _FG in accordance with the simulation can be increased by about one-fold.

Further, the gate voltages V _g1 and V _g2 of the load of Amp1 300 change the VTC. For example, Figure 6 (a) shows the VTC of Amp1 300 for three different V _g2 values at the same V _g1 (0.7 V) where a significant change in VTC is seen. V _g1 is also the same as shown in Fig. 6 (b). However, the VTC simply depends on V _g1 . If a high V _out (spike) is triggered only when V _{amp_out} reaches the threshold of Amp2 500 (indicated by the dashed line in FIG. 6 (a)), then V _{amp_in} for the spike is substantially dependent on V _g2 do.

As shown in Fig. 6 (a), the higher the V _g2 , the higher the V _{amp_in} for the spike. Therefore, the spike requires a high V _FG . The higher V _FG requires a longer integration time at a given input voltage in the DC input mode, or a given input activity (high enough to cause a spike) in the spiking input mode. Thus, the output activity a _out is reduced to V _g2 (Fig. 6 (c)).

For the same reason, the higher the V _FG , the higher the V _in required to output the same activity. As a result, the threshold value of the spike in the DC input mode increases with V _g2 , as can be seen in Fig. 6 (d). Thus, the gain function of the neuron can be easily modified by fine tuning V _g2 .

As shown in Fig. 4 (c) and Fig. 5 (b), when positive feedback is triggered via C1, V _{amp_out} becomes higher than the threshold value of Amp2 500. The overshoot (about 65mV) is mainly determined by the capacitance of C1 and V _{dd +} . The overshoot is independent of V _g2 . V _{amp_in} then decreases immediately upon the start of the negative feedback to the FG integrator 100 through the polarity inverter 700. V _{amp_in} eventually drops below the threshold of Amp2 (500). The time required for this process is equal to the spike width.

The V _{amp_out-} V _{amp_in} relationship of FIG. 6 (a) indicates that the higher V _g2 , the greater the V _{amp_in} should be made larger and the negative feedback to pull V _{amp_out} below the threshold. ΔV _{amp_in} is the standard, in particular, the increase ΔV _{amp _in} required with V _g2, thus sikineunde higher V _g2 is reduced to V _{amp_out} by 65 mV, that is V _inv of the same sound as shown in 6 (e) Fig. It takes longer to reset the FG integrator 100.

As a result, as can be seen in Fig. 6 (f), the higher the V _g2 , the wider the spike. Also, as | V _{dd -} | increases, | V _inv | increases, and resetting FG integrator 100 shortens the time with | V _{dd -} |, narrowing the width of the output spike.

Hereinafter, the power consumption of the artificial neuron circuit 10 of the present invention will be described.

The principle of neuromorphic technology requires a low power consumption. To do this, we evaluated the power consumption of FGLIF neurons that caused varying output activity while keeping the input voltage constant. The average power consumption was assessed for the energy consumed during a single spike period and divided by the period to collect for various output activities.

The result, referring to FIG. 7, is that the average power consumption is moderately proportional to the output activity. In particular, the FGLIF neuron circuit proposed in the present invention consumes less than 30 pW of power over the entire activity range. This is mainly due to the subthreshold operation of Amp1 300 and Amp2 500 and allows low current flow through the series of channels.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the present invention as defined by the following claims. You will understand.

The present invention can be applied to a highly integrated integrator for realizing the operation principle of an artificial neuron element, which is an integral-action potential generation function, and is applicable to simulation of state variables of artificial synapses. In addition, it can be used in various fields such as a semiconductor chip that can realize artificial intelligence capable of self-determination through learning, and a pattern recognition function through massively parallel computation.

10: artificial neuron circuit
100: FG integrator
300: voltage amplifier
500: voltage output section
700: polarity reversal

Claims (16)

A floating gate (FG) integrator comprising a first tunnel junction element sharing a floating gate and a second tunnel junction element, the charge trapping element adjusting charge of the floating gate using charge relaxation;
A voltage amplifier for adjusting the gate voltage of the transistor to amplify the floating gate voltage output from the floating gate integrator;
A voltage output unit for amplifying the output voltage of the voltage amplifier again to generate a spike voltage; And
And a polarity reverser applied to the gate to reverse the polarity of the spike voltage and applied to the second tunnel junction element to reset the charge of the floating gate. The high integration low power dissipation artificial neuron Circuit.
The method according to claim 1,
Wherein the tunneling phenomenon of the first tunnel junction element and the second tunnel junction element is used to inject charge into the floating gate.
The method according to claim 1,
A highly integrated low power dissipative artificial neuron circuit using a floating gate integrator to control the thickness of the tunneling barrier of the first tunnel junction element to adjust the charge relaxation time of the floating gate.
The method of claim 3,
Wherein the thicker the tunneling barrier of the first tunnel junction element, the less time the charge of the floating gate is relaxed.
2. The integrated circuit of claim 1, wherein the floating gate integrator comprises:
And a transistor for controlling an input voltage of a gate of the voltage amplifier by controlling the channel electrical conductivity using the electrode of the floating gate as a gate electrode.
The method according to claim 1,
Wherein the spike voltage output from the voltage output has an action potential of less than 100 Hz.
The method according to claim 1,
Wherein the voltage output comprises a positive feedback capacitor. A highly integrated, low power, artificial neuron circuit using a floating gate integrator.
A neuromorphic system having a plurality of highly integrated low power consumption artificial neuron circuits using the floating gate integrator according to any one of claims 1 to 7.
9. The method of claim 8,
Wherein the input voltages of the artificial neuron circuits are simultaneously input.
9. The method of claim 8,
Wherein the input voltages of the artificial neuron circuits are each arbitrarily input.
A floating gate (FG) integrator including a first tunnel junction element and a second tunnel junction element sharing a floating gate; A voltage amplifier for amplifying the floating gate voltage output from the floating gate integrator; A voltage output unit for amplifying the output voltage of the voltage amplifier again to generate a spike voltage; And a polarity reverser applied to the gate to reverse the polarity of the spike voltage and applied to the second tunnel junction element to reset the charge of the floating gate, wherein the floating gate integrator is a highly integrated low- A method for controlling a neuron circuit,
Injecting charge into the floating gate using a tunneling phenomenon of the first tunnel junction element and the second tunnel junction element;
Adjusting a charge of the floating gate using a charge relaxation phenomenon of the first tunnel junction element; And
Controlling the thickness of the tunneling barrier of the first tunnel junction element to adjust the charge relaxation time of the floating gate. ≪ Desc / Clms Page number 19 >
12. The method of claim 11,
Wherein the thickening of the tunneling barrier of the first tunnel junction element reduces the time that the charge of the floating gate is relaxed.
12. The method of claim 11,
Controlling a gate voltage of a transistor included in the voltage amplifier to control a characteristic of a voltage amplitude. A method of controlling a highly integrated low power consumption artificial neuron circuit using a floating gate integrator.
12. The method of claim 11,
Wherein the floating gate integrator further comprises a transistor using the electrode of the floating gate as a gate electrode to control the channel electrical conductivity of the transistor to control an input voltage of a gate of the voltage amplifier, Control Method of Highly Integrated Low Power Consumption Artificial Neuron Circuit Using Integrator.
12. The method of claim 11,
Wherein the spike voltage output from the voltage output section has an action potential of less than 100 Hz.
12. The method of claim 11,
Wherein the voltage output unit further comprises a positive feedback including a capacitor. 11. The method of claim 9, wherein the voltage output unit includes a capacitor.

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