KR101916819B1 - Method for determining keep-out zone of through silicon via and computer-readerble recording medium storing keep-out zone determinig program - Google Patents

Abstract

A method for determining a keep-out zone of a through silicon via according to the present invention comprises the steps of: measuring a capacitance of a through silicon via to derive a capacitance-bias voltage curve; calculating a flattening voltage capacitance of the silicon through electrode by a capacitance equivalent circuit relation to the through silicon via; calculating a flattening voltage of the through silicon via by the flattening voltage capacitance and the capacitance-bias voltage curve; calculating an interface electrical potential between a substrate unit and a dielectric unit of the through silicon via by the flattening voltage; and calculating a keep-out zone of the through silicon via by the interface electrical potential. Therefore, the keep-out zone of the through silicon via manufactured under the same process condition may be quickly and accurately determined.

Description

 METHOD FOR DETERMINING KEEP-OUT ZONE OF THROUGH SILICON VIA AND COMPUTER-READER RECORDING MEDIUM STORING KEEP-OUT ZONE < RTI ID = 0.0 > DETERMINIG PROGRAM}

The present invention relates to a technique for determining a keep-out zone of a silicon penetrating electrode.

Generally, through silicon vias (TSVs) refer to a packaging technique or an electrode structure for connecting upper and lower chips to electrodes by forming through holes in a silicon substrate. Silicon penetration electrodes can significantly improve speed and power consumption compared to existing wire bonding technology. As the trend of the Internet of Things (IoT) comes, it is a technology to integrate heterogeneous systems with different functions within one platform. It is rising.

The silicon through electrode is a typical type and has a metal-oxide-semiconductor (MOS) structure. Here, the oxide is for DC insulation between the conductive metal and the main surface silicon substrate, and may be generally composed of a dielectric layer of SiO ₂ .

However, as the complexity of the system increases, the number of the silicon through electrodes used in the package is increased compared to the area, thereby shortening the distance between the silicon through electrodes or between the silicon through electrodes and the logic cells, There is a problem that performance is hindered.

To cope with such a problem, a keep-out zone (KOZ) is determined around the silicon through electrode. Specifically, the keep-out zone means from the point where the electric field intensity generated by the voltage applied to the silicon penetrating electrode becomes 0 in the semiconductor (Si).

In order to determine the keep-out zone, there was a calculation method according to the conventional mathematical model. However, in the case of following the assumption or approximation of the conventional calculation method, it is known that the error exceeds 80%, and the keep-out zone can not be determined accurately. Accordingly, the integrated design of the package including the silicon through electrode is not efficiently achieved.

Therefore, it is required to develop a technique for increasing the accuracy of the determination of the keep-out zone of the silicon penetrating electrode. In particular, as shown in Patent Document 1, there are various defects generated in the manufacturing process of the silicon penetrating electrode. However, a technology capable of determining a keep-out zone reflecting the defects in the oxide and the semiconductor-oxide interface during the oxide deposition process It is necessary.

KR 10-1875837 B1 (Registered on July 2, 2018)

An object of the present invention is to provide a method of determining a keep-out zone of a silicon penetrating electrode which is configured to calculate a keep-out zone by measuring a capacitance of a silicon penetrating electrode.

It is another object of the present invention to provide a method of determining a keep-out zone of a silicon penetrating electrode to reflect a defect in the manufacturing process of a silicon penetrating electrode and to calculate a keep-out zone.

According to an aspect of the present invention, there is provided a method of determining a keep-out zone of a silicon penetrating electrode, comprising: measuring a capacitance of a silicon penetrating electrode to derive a capacitance-bias voltage curve; Calculating a flattening voltage capacitance of the silicon through electrode by a capacitance equivalent circuit relation to the silicon through electrode; Calculating a flattening voltage of the silicon through electrode by the flattening voltage capacitance and the capacitance-bias voltage curve; Calculating an interface electrical potential between the substrate portion and the dielectric portion of the silicon through-hole electrode by the flattening voltage; And calculating a keep-out zone of the silicon penetrating electrode by the interface electric potential.

According to another aspect of the present invention, there is provided a method of determining a keep-out zone of a silicon penetrating electrode, comprising: calculating a defect amount per unit area of the silicon penetrating electrode by the flattening voltage; And calculating the flattening voltage of the unmeasured silicon through-hole electrode manufactured under the same process conditions as the silicon through-hole electrode by the amount of defects per unit area, and calculating the interface electric potential, In the step of calculating zones, an interface electric potential and a keep-out zone are calculated for the unmeasured silicon penetrating electrode.

The planarization voltage capacitances ( C ' _{T, FB} )

Lt; / RTI > In this case, ε _Si is the dielectric constant of said substrate, r ₁ is the radius of the outer circumferential surface of the dielectric unit, q is the electron charge, N _a is the doping concentration of acceptor ions in the substrate unit, K is Boltzmann's constant, T is absolute temperature , ε _ox is the dielectric constant, r ₀ the dielectric portion means the radius of the inner peripheral surface of the dielectric portion.

The interface between the electrical potential (φ _S) is,

Lt; / RTI > V _M denotes a maximum voltage applied to the silicon penetrating electrode, V _FB denotes the flattening voltage, and n _i denotes an intrinsic carrier concentration of the substrate portion.

The keep-out zone ( W _KOZ )

Lt; / RTI >

The defect amount ( Q _{t, ox} / q ) per unit area and the flattening voltage ( V _{FB [n]} ) of the non-

Lt; / RTI >

According to another aspect of the present invention, there is provided a computer readable storage medium storing a program for determining a keep-out zone of a silicon penetration electrode by capacitance measurement, wherein the program for determining the keep- Deriving a capacitance-bias voltage curve based on the measured capacitance values, calculating a planarization voltage capacitance of the silicon through-hole electrode by a capacitance equivalent circuit relation to the silicon through-hole electrode, and calculating a capacitance- Calculating a flattening voltage of the silicon penetrating electrode by a bias voltage curve and calculating an interface electric potential between the substrate portion and the dielectric portion of the silicon penetrating electrode by the flattening voltage, And a keep-out zone of the silicon penetrating electrode is calculated.

By determining the keep-out zone of the silicon penetrating electrode according to the present invention, the minimum distance between the silicon penetrating electrodes or the logic cell and ensuring the electrical performance can be accurately calculated, and the integration and miniaturization of the package including the silicon penetrating electrode Can be stably achieved.

Particularly, by determining defects in the manufacturing process of the silicon penetrating electrode to determine the keep-out zone, the keep-out zone of the silicon penetration electrodes manufactured under the same process conditions can be determined quickly and accurately.

BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 shows the structure of a silicon through electrode and the defects in the form of charge that may exist in the dielectric portion.
2 is a view showing the arrangement of a silicon penetrating electrode in consideration of a keep-out zone.
3 is a flowchart showing a method of determining a keep-out zone of a silicon penetrating electrode according to the present invention.
4 is a diagram showing a capacitance equivalent circuit model of a silicon through electrode.
5 is a diagram illustrating a capacitance-bias voltage curve derived in an embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings, which will be readily apparent to those skilled in the art. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. In order to clearly illustrate the present invention, parts not related to the description are omitted, and similar parts are denoted by like reference characters throughout the specification.

Throughout the specification, when an element is referred to as "comprising ", it means that it can include other elements as well, without excluding other elements unless specifically stated otherwise.

FIG. 1 is a view showing the structure of the silicon penetrating electrode 10 and the defects of the charge type that may exist in the dielectric portion 13. Referring to FIG. 1, the silicon penetrating electrode 10 to be measured according to the present invention may include a substrate portion 11, an electrode portion 12, and a dielectric portion 13.

The substrate portion 11 may be made of P type silicon. The electrode unit 12 may have a cylindrical shape penetrating the substrate unit 11 in the thickness direction, and may be formed of a metal material and serve as an electrode.

The dielectric portion 13 may be formed between the outer circumferential surface of the electrode portion 12 and the substrate portion 11 and may be made of SiO ₂ to serve as an insulation between the substrate portion 11 and the electrode portion 12. can do. The dielectric portion 13 is required to have high breakdown voltage and good uniformity characteristics and can be formed by chemical vapor deposition (CVD) or atomic layer deposition (ALD).

1B, defects in the form of charge, which may be present inside the dielectric portion 13 and at the interface 14 (the outer circumferential surface of the dielectric portion 13), may be caused by mobile oxide charges Q _m ), Oxide trap charges ( Q _ot ), fixed oxide charges ( Q _t ), and interface trap charges ( Q _it ).

On the other hand, FIG. 2 is a diagram showing the arrangement of the silicon through electrodes considering the keep-out zone. As shown in FIG. 2 (a), a keep-out zone must be set between the silicon penetrating electrodes to prevent a degradation of one signal characteristic of the polarity to the noise coupling between the silicon penetrating electrodes. Also, as shown in FIG. 2B, it is necessary to set a keep-out zone so that the performance of the logic cell located nearby can be prevented from being degraded due to the electric field due to the voltage applied to the silicon penetrating electrode .

Specifically, the keep-out zone is a region where the electric field intensity formed by the voltage applied from the dielectric portion 13 of the silicon penetrating electrode 10 to the silicon penetrating electrode 10 reaches zero at the substrate portion 11 It means distance. Since the silicon penetrating electrode 10 has a metal-oxide-semiconductor (MOS) structure, the distance from the substrate portion 11 to the point where the electric field intensity becomes zero is equal to the width of the depletion region. The charge-type defects described above cause a change in the width of the depletion region in the substrate portion 11, so that the keep-out zone is also affected by defects present in the dielectric portion 13 and the interface 14. [

3 is a flowchart showing a method of determining a keep-out zone of a silicon penetrating electrode according to the present invention. Hereinafter, a method of determining the keep-out zone of the silicon penetrating electrode according to the present invention will be described in detail.

A method of determining a keep-out zone of a silicon penetrating electrode according to the present invention includes the steps of deriving a capacitance-bias voltage curve (S10), calculating a flattening voltage capacitance (S20), calculating a flattening voltage (S30) A step (S40) of calculating an interface electric potential, and a step (S50) of calculating a keep-out zone.

In the step (S10) of deriving the capacitance-bias voltage curve, the capacitance of the silicon through electrode is measured. Based on this, a quantitative relationship between the measured capacitance value and the bias voltage can be derived in a graph form. However, it is not always necessary to derive the shape of the curve on the graph, but data of the measured capacitance value and bias voltage value corresponding to each other may be secured in the form of a table.

In step S20 of calculating the flattening voltage capacitance, a capacitance equivalent circuit model of the silicon through electrode can be utilized. The planarization voltage capacitance of the silicon through-hole electrode for which the capacitance was previously measured can be calculated by the equivalent circuit model described later.

Specifically, the planarization voltage capacitances ( C ' _{T, FB} )

Lt; / RTI > In this case, ε _Si is billion in the substrate portion 11, the dielectric constant, r ₁ is the radius of the outer peripheral surface of the dielectric portion (13), q is a charge quantity of electron ^{(1.0662 × 10 19 C),} N a is the substrate portion 11 of the K is the Boltzmann constant (1.3801 x 10 ^-19 m ² / (kg ² K)), T is the absolute temperature, ε _ox is the dielectric constant, r ₀ of the dielectric portion 13 may indicate the radius of the inner peripheral surface of the dielectric portion (13).

In the step S30 of calculating the flattening voltage, the calculated flattening voltage capacitance value may be substituted into the capacitance-bias voltage curve to calculate a flat-band voltage. That is, the calculated flattening voltage capacitances C ' _{T and FB} correspond to the capacitance values of the capacitance-bias voltage curve, and the bias voltage values corresponding to the capacitance values can be the flattening voltage V _FB .

Next, in step S40 of calculating the interfacial electrical potential, the leveling voltage ( V _FB ) value may be used to calculate the interfacial electrical potential at the interface 14 between the substrate portion and the dielectric portion. Specifically, the interface electric potential phi _S is,

. ≪ / RTI > At this time, V _M means the maximum voltage applied to the silicon through electrode. In addition, n _i denotes the intrinsic carrier concentration of the substrate portion 11,

Can be calculated by the following equation.

When the interface electric potential phi _S is calculated, a keep-out zone can be calculated by the interface electric potential value (step S50 of calculating a keep-out zone). In the step of calculating the keep-out zone ( W _KOZ )

Can be used.

According to the method of determining the keep-out zone of the silicon penetrating electrode of the present invention as described above, the distance of the desired keep-out zone to be secured in the region of the substrate portion 11 around the dielectric portion 13 can be calculated. By improving the accuracy with which the keep-out zone is determined in accordance with the method of the present invention, the reliability of the design can be ensured when the circuit is integrated and miniaturized.

The method of determining a keep-out zone of a silicon penetrating electrode according to the present invention is a method of determining a keep-out zone of a silicon penetrating electrode according to the present invention, Out zones can be calculated together.

As shown in FIG. 3, the method of determining a keep-out zone of a silicon penetrating electrode according to the present invention includes a step S60 of calculating a defect amount per unit area, a step S70 ).

In the step S60 of calculating the defective amount per unit area, the flattening voltage V _FB calculated in the step S30 for calculating the flattening voltage may be used. Specifically, the amount of defects per unit area ( Q _{t, ox} / q )

Can be calculated by the following relational expression.

Further, in the step S70 of calculating the flattening voltage of the unmeasured silicon through-hole electrode, the flattening voltage V _{FB [n]} of the unmeasured silicon through-

Can be calculated according to the following equation.

Further, each of the calculated flattening voltage V _{FB [n]} values of the unmeasured silicon penetrating electrode is calculated in the step S40 of calculating the interface electric potential and the step S50 of calculating the keep-out zone, The interface electric potential phi _S and the keep-out zone W _KOZ can be calculated. As a result, the keep-out zone W _KOZ of each unmeasured silicon penetrating electrode can be calculated and determined.

As described above, according to the present invention, by measuring the capacitance of one of the silicon penetration electrodes fabricated under the same process conditions, the keep-out zone of the remaining silicon penetration electrodes can also be quickly determined. In addition, defects in the manufacturing process of the silicon penetrating electrode are reflected, and high accuracy can be secured.

Hereinafter, relational expressions relating to the above-described steps, including the equivalent circuit model of the silicon penetrating electrode, will be described. FIG. 4 is a diagram showing a capacitance equivalent circuit model of a silicon through electrode, which is an equivalent circuit model at a high frequency.

First, the mathematical expression used to determine the capacitance at the silicon through electrode,

And the nonlinear Poisson equation. Here, φ (r) means that the electric potential (electric potential), φ _S is the dielectric part and the base plate surface electric potential of between (hereinafter, the interface electric potential "), and, ρ _ox (r) is the dielectric part charge Density of the oxide film trap charge ( Q _ot ) and the density of the flow ion charge ( Q _m ).

The boundary conditions of the above differential equation are as follows:

, Wherein, V _bias is the bias voltage, Φ _MS is applied to the silicon through-electrode is the work function difference, Q _f between the electrode portion and the base portion is fixed charges (fixed oxide charges), Q _it is the interface trapped charge (interface trap respectively.

Using the solution of the Poisson equation satisfying the above boundary condition,

Can be obtained. Here, C ' _ox is the capacitance of the unit length single dielectric portion, Q _ox is the charge amount of the dielectric portion per unit area due to ρ _ox ( r ), and Q _{t, ox} means the sum of Q _it , Q _f and Q _ox .

Further, in the above relational expression, the surface charge Q _S ( φ _S ) due to holes, electrons, and ionized acceptors in the silicon of the P type,

Can be expressed as a relational expression. Here, + can be interpreted as being used in the depletion region, the inversion region, and the accumulation region, using accumulation, depletion and inversion regions.

4, the capacitance C ' _S ( φ _S ) per unit length in the substrate portion with respect to the interface electric potential with respect to the substrate portion,

Can be expressed as However, in the above equation, φ _S = 0 can not be defined. To define C ' _S (0) = C' _{S, FB} in a flat band with φ _S = 0 ,

And the Poisson equation. When the Poisson equation is solved using the same boundary condition as above, C ' _{S, FB} = C' _S (0) is defined as follows.

On the other hand, the keep-out zone extends to the point where the electric field inside the substrate portion becomes zero, which coincides with the width of the depletion region. Using the fact that C ' _S (W _KOZ ) which can be expressed as a function of the width of the keep-out zone is the same as C' _S ( φ _S ) in the above equation, the keep-out zone ( W _KOZ )

Can be calculated as follows.

Hereinafter, an embodiment of determining a keep-out zone by applying a method of determining a keep-out zone of a silicon penetrating electrode according to the present invention will be described with reference to FIG. FIG. 5 is a diagram showing a passivity-bias voltage curve derived in an embodiment of the present invention. FIG.

This embodiment is directed to silicon through electrodes having various sizes and manufactured under the same process conditions as in the following table.

In the step of deriving the capacitance-bias voltage curve, one silicon penetrating electrode TSV1 may be selected to measure the capacitance, and a capacitance-bias voltage curve as shown in Fig. 5 may be derived. Further, in the step of calculating the flattening voltage capacitance, the flattening voltage capacitances C ' _{T and FB} of the silicon penetrating electrode TSV1 can be calculated ( C' _{T, FB} = 4.302 fF / μm). Next, the leveling voltage ( V _FB ) of the silicon penetrating electrode TSV1 can be calculated by substituting the flattening voltage capacitance value for the capacitance-bias curve.

Next, in the step of calculating the defective amount per unit area, the amount of defects per unit area generated in the process can be calculated using the flattening voltage value of the silicon penetrating electrode TSV1. Further, the flattening voltage for the unmeasured silicon penetrating electrodes TSV2, TSV3, TSV4, TSV5 can be calculated by the calculated amount of defects per unit area. At this time, values related to the size of each silicon through electrode can be used as shown in the following table.

The interface electric potential and the keep-out zone of each of the silicon penetrating electrodes TSV1, TSV2, TSV3, and TSV4. TSV5 can be calculated by calculating the next interfacial electrical potential and calculating the keep-out zone . Specific values are shown in the table below.

Meanwhile, the present invention may be a computer-readable recording medium storing a program for determining a keep-out zone of a silicon penetrating electrode by a capacitance measurement value. At this time, the program for determining the keep-out zone may derive a bias voltage-capacitance curve based on the measured capacitance values, and calculate a planarization voltage capacitance of the silicon penetration electrode by a capacitance equivalent circuit relation to the silicon penetration electrode Calculating a flattening voltage of the silicon through electrode by the flattening voltage capacitance and the bias voltage-capacitance curve, and calculating a flattening voltage of the silicon through electrode based on the flattening voltage, Calculating a potential, and calculating a keep-out zone of the silicon penetrating electrode by the interface electric potential.

The computer-readable medium of the present invention may be any available medium that can be accessed by a computer, and may include both volatile and non-volatile media, removable and non-removable media. For example, a hard disk, a flexible disk, a compact disk, a magnet optical disk, a memory card, or the like.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. There will be. It is therefore to be understood that the above-described embodiments are illustrative in all aspects and not restrictive. For example, each component described as a single entity may be distributed and implemented, and components described as being distributed may also be implemented in a combined form.

The scope of the present invention is defined by the appended claims rather than the foregoing description, and all changes or modifications derived from the meaning and scope of the claims and their equivalents should be interpreted to be included in the scope of the present invention do.

10: Silicon penetrating electrode
11:
12:
13:
14: Interface

Claims (7)

Measuring a capacitance of the silicon penetrating electrode to derive a capacitance-bias voltage curve;
Calculating a flattening voltage capacitance of the silicon through electrode by a capacitance equivalent circuit relation to the silicon through electrode;
Calculating a flattening voltage of the silicon through electrode by the flattening voltage capacitance and the capacitance-bias voltage curve;
Calculating an interface electrical potential between the substrate portion and the dielectric portion of the silicon through-hole electrode by the flattening voltage; And
And determining a keep-out zone of the silicon penetration electrode by the interfacial electrical potential.
The method according to claim 1,
Calculating a defect amount per unit area of the silicon through-hole electrode by the flattening voltage; And
Further comprising the step of calculating a flattening voltage of the unmeasured silicon through-hole electrode manufactured under the same process conditions as the silicon through-hole electrode by the defect amount per unit area,
Wherein the step of calculating the interfacial electric potential and the step of calculating the keep-out zone calculate an interfacial electrical potential and a keep-out zone with respect to the unmeasured silicon penetrating electrode, Out zone determination method.
The method according to claim 1,
Wherein the flattening voltage capacitances ( C ' _{T, FB} ) are calculated according to equations (1) to (3).
[Equation 1]

&Quot; (2) "

&Quot; (3) "

(Ε _Si is the dielectric constant of said substrate, r ₁ is the radius of the outer circumferential surface of the dielectric unit, q is the electron charge, N _a is the doping concentration of acceptor ions in the substrate unit, K is Boltzmann's constant, T is absolute temperature, ε _ox is the dielectric constant of the dielectric portion, r ₀ is the radius of the inner peripheral surface of the dielectric portion)
The method according to claim 1,
Wherein the interfacial electrical potential ( phi _S ) is calculated by the following equations (4) to (6).
&Quot; (4) "

&Quot; (5) "

&Quot; (6) "

(V _M is the maximum voltage, V _FB is the planarization voltage, ε _Si is the dielectric constant of said substrate, ε _ox is the radius, r ₀ of the outer circumferential surface dielectric constant, r ₁ of the dielectric portion is of said dielectric is applied to the silicon through-electrode is Where N is _a doping concentration of acceptor ions in the substrate portion, q is an electron charge amount, and n _i is an intrinsic carrier concentration of the substrate portion), K is a Boltzmann constant, T is an absolute temperature,
The method according to claim 1,
Wherein the keep-out zone ( W _KOZ ) is calculated by Equations (7) to (9).
&Quot; (7) "

&Quot; (8) "

&Quot; (9) "

(Φ _S is the surface electric potential, r ₁ is the dielectric constant radius, q is the electron charge, N _a is the doping concentration, ε _Si of acceptor ions in the substrate portion of the outer surface of the dielectric portion is the substrate portion, K is Boltzmann constant, T is the absolute temperature, and n _i is the intrinsic carrier concentration of the substrate portion)
3. The method of claim 2,
The defect amount per unit area ( Q _{t, ox} / q ) is calculated by the equation (10), and the flattening voltage V _{FB [n]} of the unmeasured silicon penetrating electrode is calculated by the equation , A method of determining a keep-out zone of a silicon penetrating electrode.
&Quot; (10) "

&Quot; (11) "

(Q is the electron charge, ε _ox is the dielectric constant of the dielectric portion, r ₁ is the radius of the outer circumferential surface of the dielectric portion, r ₀ is the radius of the inner peripheral surface of the dielectric unit, Φ _MS is between the electrode portion of the silicon through-electrode and the substrate portion Lt; / RTI >
A computer readable recording medium storing a program for determining a keep-out zone of a silicon penetration electrode by a capacitance measurement value,
Wherein the program for determining the keep-out zone comprises:
Deriving a capacitance-bias voltage curve by the measured capacitance values,
Calculating a flattening voltage capacitance of the silicon through-hole electrode by a capacitance equivalent circuit relation to the silicon through-hole electrode,
Calculating a flattening voltage of the silicon through-hole electrode by the flattening voltage capacitance and the capacitance-bias voltage curve,
And an interface electric potential between the substrate portion and the dielectric portion of the silicon penetrating electrode is calculated by the flattening voltage,
And a keep-out zone of said silicon penetrating electrode is calculated by said interfacial electrical potential.

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