KR101915834B1 - Field Print-wirable Device - Google Patents

Field Print-wirable Device Download PDF

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KR101915834B1
KR101915834B1 KR1020150128019A KR20150128019A KR101915834B1 KR 101915834 B1 KR101915834 B1 KR 101915834B1 KR 1020150128019 A KR1020150128019 A KR 1020150128019A KR 20150128019 A KR20150128019 A KR 20150128019A KR 101915834 B1 KR101915834 B1 KR 101915834B1
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South Korea
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array
type
tfts
region
tft
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KR1020150128019A
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Korean (ko)
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KR20170030740A (en
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김용상
이동훈
조형준
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성균관대학교산학협력단
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Priority to KR1020150128019A priority Critical patent/KR101915834B1/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission
    • H01L27/153—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars
    • H01L27/156—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars two-dimensional arrays

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Geometry (AREA)
  • Thin Film Transistor (AREA)

Abstract

The element array according to this embodiment includes a plurality of N type thin film transistors (TFTs) arranged in an array, a plurality of P type thin film transistors (TFT) arranged in an array, and a plurality of N type TFTs and an insulation layer formed on a plurality of P-type TFTs, and an N-type TFT and a P-type TFT are printed and wired with a conductive material.

Figure R1020150128019

Description

Field Print-wirable Device < RTI ID = 0.0 >

Field of the Invention [0002] The present invention relates to an array of printable wiring in the field.

Field programmable gate arrays (FPGAs) are devices that can be synthesized in the field by describing the necessary circuits in a hardware description language such as VHDL and VARLOG. An FPGA device generally performs a digital operation on a given input signal to provide an output. Currently, a mixed signal FPGA is being studied in which an analog signal and a digital signal are received and processed.

In addition, although the conventional thin film transistor (TFT) technology has been used only for the display field, flexible devices can be formed using thin film transistors, and various applications such as wearable devices and medical care .

Since a general FPGA device is manufactured on a silicon basis, it can not be stretched or compressed in the lateral direction of the substrate, and the device is broken if bent or warped. Therefore, the FPGA device according to the prior art can not be used for an electronic device that needs flexibility such as bending or bending such as wearable electronic devices.

In many applications, a device capable of being synthesized and capable of performing the functions requested in the field is required, but existing FPGAs can not be adapted to the electronic devices requiring flexibility as described above, I never do that.

The main object of the present embodiment is to provide an electronic device which can be implemented in the field to perform a function requested in the field, and which can be used as an electronic device requiring flexibility, such as a wearable device.

The element array according to this embodiment includes a plurality of N type thin film transistors (TFTs) arranged in an array, a plurality of P type thin film transistors (TFT) arranged in an array, and a plurality of N type TFTs and an insulation layer formed on a plurality of P-type TFTs, and an N-type TFT and a P-type TFT are printed and wired with a conductive material.

According to the present embodiment, wiring can be performed in the field using a printing technique, so that a circuit having a function requested in the field can be formed immediately on the spot.

The device array according to the present embodiment is advantageous in that it has no substrate and is flexible in lateral compression and elongation.

Fig. 1 is a diagram schematically showing a top surface of an element array according to this embodiment.
2 is a diagram showing an outline of a cross section of a TFT.
3 is a cross-sectional view schematically showing a state in which an insulating layer formed on an upper portion of the element array and a hole penetrating the insulating layer are formed.
4 (a) is a top view showing a part of a device array in which wiring is performed so that the P-type TFT and the N-type TFT form an inverter, and FIG. 4 (b) Fig.

The description of the present invention is merely an example for structural or functional explanation, and the scope of the present invention should not be construed as being limited by the embodiments described in the text. That is, the embodiments are to be construed as being variously embodied and having various forms, so that the scope of the present invention should be understood to include equivalents capable of realizing technical ideas.

Meanwhile, the meaning of the terms described in the present application should be understood as follows.

The terms "first "," second ", and the like are used to distinguish one element from another and should not be limited by these terms. For example, the first component may be referred to as a second component, and similarly, the second component may also be referred to as a first component.

It should be understood that the singular " include "or" have "are to be construed as including a stated feature, number, step, operation, component, It is to be understood that the combination is intended to specify that it is present and not to preclude the presence or addition of one or more other features, numbers, steps, operations, components, parts or combinations thereof.

Each step may take place differently from the stated order unless explicitly stated in a specific order in the context. That is, each step may occur in the same order as described, may be performed substantially concurrently, or may be performed in reverse order.

The terms "and / or" used herein to describe the embodiments of the present disclosure are used to refer to and respectively. As an example, the description "A and / or B" should be understood to refer to "A, B and both A and B."

The drawings referred to for explaining embodiments of the present disclosure are exaggerated in size, height, thickness, and the like intentionally for convenience of explanation and understanding, and are not enlarged or reduced in proportion. In addition, any of the components shown in the drawings may be intentionally reduced, and other components may be intentionally enlarged.

All terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs, unless otherwise defined. Terms such as those defined in commonly used dictionaries should be interpreted to be consistent with the meanings in the context of the relevant art and can not be construed as having ideal or overly formal meaning unless explicitly defined in the present application .

Hereinafter, an element array according to the present embodiment will be described with reference to the accompanying drawings. Fig. 1 is a diagram schematically showing a top surface of an element array according to this embodiment. 1, the device array 100 according to the present embodiment includes a plurality of N-type TFTs (N-type Thin Film Transistors) 112 arranged in an array, a plurality of P-type TFTs P type Thin Film Transistor 122, and a plurality of N-type TFTs and an insulation layer formed on the plurality of P-type TFTs, wherein the N-type TFT and the P-type TFT are printed with a conductive material, do.

In one embodiment, the device array 100 according to the present embodiment includes a plurality of resistors R 1 , R 2 , ..., R n arranged in an array, a plurality of capacitors C 1 , C 2 , ..., C n ). One end of each of resistors and the other end are holes 140 in the one end and the other end thereof and a plurality of capacitors (C 1, C 2, ... , C n) of the (R 1, R 2, ... , R n) As shown in FIG.

In another embodiment not shown, the device array according to the present embodiment includes a bio sensor for detecting a bio material, a bio sensor for detecting a signal of a living body, an illuminance sensor for detecting the illuminance of light, A gas sensor for detecting a gas component, and the like.

In Fig. 1, an insulating layer (see Figs. 3 and 130) formed on the upper surface of the element array is not shown. The holes 140 are formed in the element array through the insulating layer, and expose the source electrode, the drain electrode, and the gate electrodes.

2 is a diagram showing an outline of a cross section of a TFT. 2, the TFT includes a gate electrode G, an insulator I, an active region A where a channel is formed, a drain electrode D and a source electrode S . A silicon-based field-effect transistor is formed by doping a region of a silicon substrate with a desired conductivity type to form an active region, a drain and a source, and forming a gate insulating film and a gate on the active region. However, the staggered type TFT according to the present embodiment has a structure in which a release film (not shown) is attached to a substrate (not shown), a gate electrode G is formed on the release film, (I). An active region A where a channel is formed on the insulator I is formed and a drain electrode D and a source electrode S are formed so as to be in electrical contact with the active region A. [ The release film and upper elements are then separated from the substrate. Since the thus formed element and element array are formed separately from the silicon substrate, lateral elongation and compressibility are provided, and thus flexibility can be used in the wearable apparatus that is required.

The TFT according to the present embodiment can be formed by forming a gate electrode G, a drain electrode D and a source electrode S in gold and insulator I with PMMA (poly methyl methacrylate) . When the active region A is formed of pentacene, a P-type channel is formed, and thus a P-type TFT can be formed. When the active region A is formed of IGZO (Indium Galium Zinc Oxide) or LTPS (Low Temperature Polycrystalline Silicon), an N type channel is formed, and thus an N type TFT can be formed.

3 is a cross-sectional view schematically showing a state in which an insulating layer 130 formed on an upper portion of an element array and a hole 140 penetrating an insulating layer 130 are formed. Referring to FIG. 3, the source electrode, the drain electrode, and the gate electrode of each TFT included in the device array are exposed to the outside of the insulating layer by the holes 140. In one embodiment, the insulating layer 130 is formed of an oxide, a nitride, or a polymer film, and is patterned to form a hole 140. For example, the patterning process may be performed by a photolithography process using a photoresist.

4A is a top view showing a part of the element array 100 in which the p-type TFT 122 and the n-type TFT 112 are wired so as to form an inverter, and Fig. 4B is a cross- 4 (a) is a cross-sectional view taken along line XX '. 4A and 4B, the holes 140 are filled with a conductive material through a printing process so that the source electrode S of the P-type TFT 122 is connected to the supply voltage Vdd And connects the source electrode S of the N type TFT 112 to the ground power source Vss.

Holes formed in the gate electrodes G of the N type TFT 112 and the P type TFT 122 are buried with a conductive material and electrically connected to each other to perform a wiring process so as to provide an input voltage Vi. In addition, a wiring process is performed so that holes formed in the drain electrodes D of the N-type TFT 112 and the P-type TFT 122 are embedded with a conductive material and electrically connected to each other to provide an output voltage Vo .

In one embodiment, the wiring process is performed by a printing process, and includes an inkjet printing process for forming a wiring by discharging a conductive material through a nozzle, a process for forming a conductive material on a mold, Transfer printing to print on top of the insulating layer or gravure printing and roll-to-roll printing to print conductive material on top of the insulating layer using rollers. Can be used.

Examples of the conductive material used in the wiring process include a conductive metal such as gold (Au), silver (Ag), copper (Cu), aluminum (Al), titanium And organic conductors such as PEDOT: PSS and the like.

According to this embodiment, lateral compression and elongation are provided, thereby providing the advantage of being able to form a flexible electronic device. Furthermore, by using sensors included in transistors, resistors, capacitors, and various sensor arrays, (health care) equipment, and it is also provided with an advantage that it can be implemented as a wearable device.

The present embodiment also provides an advantage that an electronic device performing a printing process and performing a required function in the field can be formed on the spot.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is clearly understood that the same is by way of illustration and example only and is not to be taken by way of illustration, It will be appreciated that other embodiments are possible. Accordingly, the true scope of the present invention should be determined by the appended claims.

100: element array 112: N type TFT
122: P-type TFT 130: insulating layer
140: hole

Claims (11)

A plurality of N type thin film transistors (TFTs) arranged in an array;
A plurality of P-type thin film transistors (TFTs) arranged in an array;
Resistors arranged in an array in a first region;
Capacitors arranged in an array in a second region; And
And an insulation layer formed on the plurality of N type TFTs and the plurality of P type TFTs, the resistors arranged in the array and the capacitors arranged in the array,
Wherein the first region and the second region are spaced apart from each other,
Wherein the plurality of N type TFTs, the plurality of P type TFTs, the resistors arranged in the array, and the capacitors arranged in the array are printed and wired with a conductive material in the field to perform necessary functions in the field. The method according to claim 1,
Wherein the plurality of N type TFTs and the plurality of P type TFTs have a back staggered structure. The method according to claim 1,
Wherein a region where a channel is formed in the plurality of N type TFTs includes any one selected from the group consisting of Indium Gallium Zinc Oxide (IGZO) and Low Temperature Polycrystalline Silicon (LTPS). The method according to claim 1,
Wherein a region where a channel is formed in the plurality of P type TFTs includes Pentacene. The method according to claim 1,
The device array includes:
Further comprising a plurality of holes formed through the insulating layer and exposing electrodes of the N-type TFT and P-type TFT electrodes, respectively,
Wherein the N type TFT and the P type TFT are wired by the conductive material printed on the plurality of holes. delete The method according to claim 1,
The device array
A bio sensor for detecting a bio-material, a bio sensor for detecting a signal of a living body, a light intensity sensor for detecting light intensity and a gas sensor for detecting a desired gas component in air An array of elements further comprising a sensor array in which the sensors are arranged in an array. The method according to claim 1,
Wherein the conductive material comprises any one of a conductive metal and a conductive organic material. 9. The method of claim 8,
The conductive metal includes any one selected from the group consisting of gold (Au), silver (Ag), copper (Cu), aluminum (Al), titanium (Ti)
Wherein the conductive organic material comprises PEDOT: PSS. A plurality of N type thin film transistors (TFTs) arranged in an array;
A plurality of P-type thin film transistors (TFTs) arranged in an array;
Resistors arranged in an array in a first region;
Capacitors arranged in an array in a second region; And
And an insulation layer formed on the plurality of N-type TFTs and the plurality of P-type TFTs, the resistors arranged in the array, and the capacitors arranged in the array,
Wherein the first region and the second region are spaced apart from each other,
Type TFT, the plurality of P-type TFTs, the resistors arranged in the array, and the capacitors arranged in the array include electronic elements printed and wired with a conductive material in the field to perform required functions in the field An electronic device. 11. The method of claim 10,
Wherein the electronic device is a wearable device.

KR1020150128019A 2015-09-10 2015-09-10 Field Print-wirable Device KR101915834B1 (en)

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5085098B2 (en) * 2005-12-07 2012-11-28 コヴィオ インコーポレイテッド Diode resistant to process variations, standard cell having the diode, tag and sensor including the diode, and method of manufacturing the diode
JP2014003597A (en) * 2012-05-25 2014-01-09 Semiconductor Energy Lab Co Ltd Lookup table and programmable logic device having lookup table

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5085098B2 (en) * 2005-12-07 2012-11-28 コヴィオ インコーポレイテッド Diode resistant to process variations, standard cell having the diode, tag and sensor including the diode, and method of manufacturing the diode
JP2014003597A (en) * 2012-05-25 2014-01-09 Semiconductor Energy Lab Co Ltd Lookup table and programmable logic device having lookup table

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