KR101902972B1 - Analog digital converter using delta sigma modulation - Google Patents

Abstract

According to the present invention, an analog-to-digital converter using delta sigma modulation comprises: a coarse analog-to-digital conversion unit for generating a most significant bit (MSB) of N bits from an input signal (V_IN) using a success approximation register (SAR) logic; an incremental delta sigma modulation unit for generating an output 1 of M bits through a comparison with a reference voltage after performing multi-stage integration of the input signal using a delta sigma loop; an extended counting unit for receiving a secondary integration output of the incremental delta sigma modulation unit, performing tertiary integration, and generating an output 2 of L bits through a comparison with the reference voltage; and a decimation filter and register for generating a final digital output by receiving the MSB, the output 1, and the output 2.

Description

[0001] The present invention relates to an analog digital converter using a delta sigma modulation method,

The present invention relates to an analog-to-digital converter (ADC), and more particularly, to an analog-to-digital converter using a delta-sigma modulation method capable of realizing analog-to-digital conversion using a delta sigma modulation method.

Generally, there is a demand for an analog-to-digital converter capable of satisfying functions such as high-resolution and low-power, in electronic instruments used in a field of a communication network, an instrument field of an automatic analyzer, a sensor field,

Conventional zoom analog-to-digital converters (ADCs) use a sampling frequency that is much higher than the input frequency and therefore can implement relatively higher bits than other ADCs, It is mainly used to convert DC signal to digital.

In the case of a conventional zoom ADC, a success approximation register (SAR) structure is used for the most significant bit (MSB), and an incremental operation is used for the least significant bit (LSB) Has a problem in that it requires a relatively large number of cycles in order to obtain a target bit, and this problem causes a disadvantage that a relatively long conversion time is required.

That is, conventional zoom ADCs have the problem that the required cycles increase exponentially (e.g., conventional zoom ADC cycles = 1024) as N increases in N-bits / cycle.

In addition, in the case of the conventional zoom ADC, there is a problem that a cycle required when implementing a very high bit, such as 20 bits, becomes very large by using one OP amp.

Korean Patent Publication No. 2013-0026627 (Disclosure Date: Mar. 14, 2013)

The present invention proposes an analog-to-digital converter using a delta-sigma modulation method that can realize high linearity and relatively high stability by using a third-order mesh (MASH) structure.

In addition, the present invention proposes an analog-to-digital converter using a delta-sigma modulation method capable of implementing the same bit with fewer cycles than a conventional zoom ADC by designing the incremental operation and the expansion counting as separate operations.

Furthermore, the present invention proposes an analog-to-digital converter using a delta-sigma modulation method capable of driving power by dividing the mesh structure into four operations, thereby reducing power consumption by adaptively adjusting a necessary number of bits according to purposes.

The problems to be solved by the present invention are not limited to those mentioned above, and another problem to be solved by the present invention can be clearly understood by those skilled in the art from the following description will be.

The present invention provides a coarse analog-to-digital converter (ADC) that generates N bits of MSB (most significant bit) from an input signal (V _IN ) using success approximation register An incremental delta sigma modulator for multi-stage integration of the input signal using a delta sigma loop and then generating an output 1 of M bits through comparison with a reference voltage; An expansion type counting unit for receiving the integrated output and performing a third integration and then generating an L-bit output 2 through comparison with a reference voltage; and an adder for receiving the MSB, the output 1 and the output 2 and generating a final digital output It is possible to provide an analog-to-digital converter using a delta-sigma modulation method including a decimation filter and a register.

The course ADC of the present invention includes a first digital-to-analog converter (DAC1) for converting a digital signal into an analog signal to divide the input signal into a positive number, a comparator for comparing the output of the DAC1 with the input signal, A second comparator for comparing the bit information of the register with the first comparator, an SAR logic unit for generating the MSB based on the bit information provided from the first comparator, a register for storing the generated MSB, And provides the DAC1 with the first data weighted average unit DWA1.

The SAR logic part of the present invention can generate a 6-bit MSB.

The DWA 1 of the present invention can reduce the noise of the frequency band of the input signal through the primary noise shaping effect.

The adder delta-sigma modulator of the present invention may further include a first integrator for first integrating the input signal, a second integrator for second-order integrating the output of the first integrator, and a second integrator for multiplying the output of the second integrator by a coefficient A second comparator for generating the output 1 by comparing the output of the first comparator with a reference voltage, and a second comparator for converting the output of the second comparator by adding or subtracting a digital value to convert the output to analog, To the input of the first integrator.

The circuit means comprises an adder / subtractor for adding or subtracting a digital value to the output 1 according to the output level of the second comparator, a second data weighted averager DWA2 for weighted-averaging the output of the adder / And a second digital-analog converter (DAC2) converting the digital output of the second weighted averaging unit to an analog signal and providing the digital output of the second weighted averaging unit as an input of the first integrator for subtraction with the input signal.

The adding / subtracting unit of the present invention adds the digital value to K + 2 when the output value of the second comparator is "1 ", and subtracts the digital value to K-2 when the output value is" 0 & have.

The extended type counting unit of the present invention includes a third integrator for receiving and integrating the second-order integrator output of the incremental delta-sigma modulator and a third integrator for generating the output 2 by comparing the output of the third integrator with the reference voltage A third comparator and a third digital-to-analog converter (DAC3) for converting the digital output of the third comparator to analog and providing the input to the third integrator for addition to the second integral output.

The present invention can perform a high-resolution mode using three OTAs through the entire driving of the course ADC, the incremental delta-sigma modulator, and the extended-type counting unit.

The present invention can perform an intermediate resolution mode using two OTAs through selective driving of the course ADC and the incremental delta-sigma modulator.

The present invention can perform a low power mode using one OTA through selective driving of the course ADC and the expansion type counting unit.

According to the embodiment of the present invention, high linearity can be realized with a relatively high stability by using the third order mesh (MASH) structure.

According to an embodiment of the present invention, the same bit can be implemented with fewer cycles than conventional zoom ADCs by designing the incremental operation and expansion counting to be possible in separate operations.

According to the embodiment of the present invention, it is possible to divide the mesh structure into four operations and to drive the mesh structure, so that the power consumption can be reduced by adaptively adjusting the necessary number of bits according to the purpose.

1 is a block diagram of an analog-to-digital converter using a delta-sigma modulation method according to an embodiment of the present invention.
Figure 2 shows the respective outputs of a multistage noise shaping scalable analog to digital converter according to an embodiment of the present invention.
FIG. 3 shows an example of three modes of an analog-to-digital converter using a delta-sigma modulation method according to an embodiment of the present invention.

First, the advantages and features of the present invention, and how to accomplish them, will be clarified with reference to the embodiments to be described in detail with reference to the accompanying drawings. While the present invention has been described with reference to exemplary embodiments, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, but, on the contrary, It will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.

In the following description of the present invention, detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear. It is to be understood that the following terms are defined in consideration of the functions of the present invention, and may be changed according to intentions or customs of a user, an operator, and the like. Therefore, the definition should be based on the technical idea described throughout this specification.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram of an analog-to-digital converter using a delta-sigma modulation method according to an embodiment of the present invention.

1, the analog-to-digital converter of the present embodiment includes a coarse analog-digital converter (ADC) 110, an incremental delta-sigma modulator 120, an expandable counting unit 130, Filters and resistors 140, and the like.

First, the course ADC 110, which can be configured based on, for example, a SAR ADC structure, lowers the input and reference voltages used in the incremental delta sigma modulation section 120, and uses the SAR (success approximation register) logic the input signal (V _iN) may provide such functions as generating the MSB (most significant bit) of the first six bits from, for this course ADC (110) includes a first digital analog converter (DAC1) (111) A first comparator 112, a success approximation register (SAR) logic portion 113, a register 114 and a first data weighted averaging (DWA1) 115, have.

Here, DAC1 111 may be, for example, a 6-bit DAC, and may provide functions such as converting a digital signal to an analog signal for positive division of the input signal V _IN , 113 may be, for example, a 6-bit SAR logic, and may provide functions such as generating an n-bit MSB based on bit information provided from the first comparator 112.

First, when the input signal V _IN is input to the course ADC 110, the course ADC 110 constructed based on the SAR ADC structure generates (outputs) 6-bit MSB information.

The course ADC 110 first uses the DAC1 111 which converts the digital information into an analog signal in order to distinguish whether the input signal V _IN is positive or not. The first comparator 112 compares the output of the DAC 111 with the input signal to determine a difference between the difference and the input signal V _IN , (Outputs) the value to the SAR logic unit 113 as bit information.

The SAR logic unit 113 performs logic to obtain the next bit based on the bit information provided from the first comparator 112, that is, performs a sequence approximation operation to generate an N-bit MSB based on the first comparator 112 (Output) the image data. The bit information generated here can be stored in a register 114 of 6 bits.

The bit information stored in the register 114 passes through the DWA1 115 which performs a weighted average of the bit information of the register 114 in order to compensate for the mismatching of the capacitors used in the DAC 111. In this DWA1 115, Has a primary noise shaping effect, it is possible to lower the noise of the frequency band of the input signal (V _IN ).

The information stored in the register 114 is converted into an analog signal from the DAC 111 via the DWA1 115 and then compared with the input signal V _IN again through the first comparator 112. [

The SAR logic unit 113 sequentially compares the input signal V _IN with the input signal V _{IN in the} order of 900 mV, 450 mV, 225 mV, 112.5 mV, and 56.25 mV, , And the 6-bit MSB information generated here is stored in the register 114. At this time, the value stored in the register 114 may be referred to as K.

The incremental delta-sigma modulator 120 multiplies the input signal (V _IN ) by a multi-stage integration (first and second integrations) using a delta sigma loop, The incremental delta-sigma modulator 120 may include an adder / subtracter 121, a second data weighted averaging (DWA2) 122, a second digital An analog converter DAC2 123, a first integrator 124, a second integrator 125 and a second comparator 126, and the like.

At this time, the voltage Vin actually input to the incremental delta-sigma modulator 120 is set to the DWA2 122 and the 6-bit DAC2 123 based on the previously obtained 6-bit information (the output of the adder- Is a value obtained by subtracting the analog signal generated from the input signal V _IN . Therefore, an input much smaller than the actual input signal V _IN is input to the incremental delta sigma modulation unit 120.

The input Vin is passed through a loop filter having a second feedforward structure composed of first and second integrators 124 and 125. The final value of the loop filter is multiplied by a coefficient, The output 1 of the incremental delta-sigma modulator 120 can be obtained.

That is, the output of the second integrator 125 is multiplied by the coefficient and provided to the input of the second comparator 126 and is provided to the input of the expandable counting unit 130, which will be described later. In the comparator 126, Quot; 1 "or" 0 "through comparison of the output of the second integrator 125 with the reference voltage.

Here, the adder / subtracter 121, DWA2 122 and DAC2 123 feed back the output 1 of the second comparator 126 to add or subtract digital values and convert them to analog signals, May be defined as circuit means providing the input to the first integrator (124).

That is, when the value of the output 1 of the second comparator 126 is' 1 ', the addition / subtraction unit 121 sets the digital value to K + 2 and sets the digital value to K-2 if the value of the output 1 is' Which are used to compensate for errors that may occur in the course ADC 110.

The DAC2 123 converts the digital output of the DWA2 122 into an analog signal and subtracts the digital output of the DWA2 122 from the input signal And provides it as an input to the first integrator 124.

That is, when the incremental delta-sigma modulator 120 calls one cycle of the entire operation described above, it can operate at 256 cycles to obtain a relatively high resolution. In addition, since the course ADC 110 operates in 8 cycles, the operation of 264 cycles is finally performed for one input.

Based on the 6-bit information obtained from the first course ADC 110 according to the embodiment of the present invention, the magnitudes of the input and reference voltages used in the incremental delta-sigma modulator 120 are compared with the original input and the original reference voltage 1/16 and 1/16 times, respectively. This makes the output values of the two integrators 124 and 125 used in the incremental delta-sigma modulator 120 very small, It is possible to prevent various types of nonlinearity.

Also, since the conventional incremental delta-sigma modulator 120 can not completely use the output of the integrator up to the reference voltage, the signal-to-noise ratio (SNR) According to the embodiment of the present invention, since the input signal Vin used in the incremental delta-sigma modulator 120 and the reference voltage become very small, it is possible to use the reference voltage sufficiently, so that the coefficient of the most suitable integrator can be used Thereby obtaining a relatively high SNR.

The use of the course ADC 110 as in the embodiment of the present invention can increase the linearity of the final output of the incremental delta sigma modulator 120 used later.

That is, in the conventional incremental delta-sigma modulator, since the sign of the input signal V _IN is not known at first, the value of the output 1 to be fed back for the first time is fixed, overload phenomenon can be induced.

However, in the embodiment of the present invention, since the sign of the input signal V _IN can be known through the course ADC 110 for the first time, the value of the output 1 to be fed back for the first time can be appropriately selected, Type ADC can be prevented (mitigated).

When the operation is completed in the incremental delta-sigma modulator 120 according to the embodiment of the present invention, the extended-type counting unit 130 outputs the second-order cumulative output of the incremental delta-sigma modulator 120 2 integrator 125), and performs an extended-type counting operation for generating an L-bit output 2 through comparison with a reference voltage after the third-order integration, wherein the extended- It is possible to operate with only one input.

The extended type counting unit 130 may include a third integrator 131, a third comparator 132, and a third digital-to-analog converter (DAC 3) 133.

First, the extended type counting unit 130 receives as input the output value of the second integrator 125 in the incremental delta sigma modulation unit 120, which contains significant information for obtaining additional bits, and stores it in the third integrator 131 And the third integrator 131 receives and integrates a secondary integration output of the second integrator 125 and provides it as an input to the third comparator 132.

In this manner, the third comparator 132 generates the L-bit output 2 by comparing the output of the third integrator 131 with the reference voltage based on the information stored in the third integrator 131, The output 2 is transferred (output) to the DAC 3 133 and a decimation filter and a register 140 to be described later.

The DAC3 133 converts the output 2 provided from the third comparator 132 into an analog signal and the converted analog value is converted by the third integrator 131 in the expandable counting unit 130 into a second integrator (125). Here, the DAC3 133 may be implemented with a precise DAC, and a technique called a T network may be used for the implementation of such a precise DAC.

At this time, the scalable counting unit 130 can reconstruct the course ADC 110 and use it, so that the chip area can be relatively reduced. That is, since the SAR logic unit 113, DWA1 115, DAC1 111, and first comparator 112 used in the course ADC 110 are no longer used after performing the course ADC process. This can be reused as a necessary component in the scalable counting unit 130, and the chip area can be relatively reduced.

Since the scalable counting unit 130 is completely separated from the incremental delta sigma modulating unit 120 in the circuit, it is possible to have an interleaved ADC type that operates separately for different inputs. The number of cycles required can be greatly reduced.

Finally, in the decimation filter and register 140 using, for example, an integrator, 6 bits (MSBs) previously provided from the register 114 and an incremental delta sigma modulation section And outputs the final digital output (Do) by receiving the output 1 generated by the expanding unit 120 and the output 2 generated by the expandable counting unit 130 as inputs.

Figure 2 shows the respective outputs of a multistage noise shaping scalable analog to digital converter according to an embodiment of the present invention.

Referring to FIG. 2, a relatively small input value 210 is input to the incremental delta-sigma modulator 120 by a coarse ADC 110 operating in the form of a SAR ADC at each step output.

After the modulation operation in the incremental delta-sigma modulation unit 120 is completed, the value (output value) remaining in the second integrator 123 is provided to the extended-type counting unit 130 so that an additional bit is obtained through the extended- .

FIG. 3 shows an example of three modes of an analog-to-digital converter using a delta-sigma modulation method according to an embodiment of the present invention.

3, since the course ADC 110, the incremental delta-sigma modulator 120, and the extended-type counting unit 130 can be separately driven in the embodiment of the present invention, Each with different resolution and power consumption.

For example, in the high-resolution mode 310 in which both the course ADC 110, the incremental delta-sigma modulator 120 and the expandable counting unit 130 are driven, three OTAs (operational transconductance amplifiers) are all used, relatively high resolution can be realized. Here, the OTA may be a folded cascode OTA.

Also, according to the present embodiment, in the case of the medium-resolution mode 320 in which the course ADC 110 and the incremental delta-sigma modulator 120 are driven, two OTAs are used, And power consumption can be realized.

According to the present embodiment, in the low-power mode 330 in which the course ADC 110 and the expandable counting unit 130 are driven, low power can be realized by using only one OTA.

As described above, the individually driven type can be defined as a mesh (MASH) structure, which, unlike the conventional ADC, can generate a dynamic bit by changing the driving structure . For example, assuming that the sensor is the case, it can operate at low power at the monitoring time and can be adjusted to obtain a high resolution at a specific point in time.

According to this embodiment, by driving the mesh structure by dividing it into four modes (mode 0 ?? mode 3), it is possible to reduce power consumption by adaptively adjusting the number of bits required according to the purpose.

For example, in "mode 0", 20 bits can be generated by SAR operation and second order incremental ADC and expansion counting operation, In 17-bit mode, power consumption can be reduced by using "mode 1" to obtain SAR operation and second-order incremental ADC operation, ie, using only two operational amplifiers.

Also, 12 ?? For 13 bits, "Mode 2" requires SAR operation and 256 cycles of extended count operation. In this case, only one operational amplifier is required, further reducing power consumption.

Moreover, 8 ?? 9-bit mode requires SAR operation and 16-cycle extended counting operation through "Mode 3". In this case, only one OP amplifier is required, which can reduce power consumption and reduce conversion time. have.

It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present invention as defined by the following claims. It is easy to see that this is possible. That is, the embodiments disclosed in the present invention are not intended to limit the scope of the present invention but to limit the scope of the present invention.

Therefore, the scope of protection of the present invention should be construed in accordance with the following claims, and all technical ideas within the scope of equivalents should be interpreted as being included in the scope of the present invention.

110: Course analog digital conversion section
111: a first digital-analog converter (DAC1)
112: first comparator
113: SAR logic section
114: Register
115: first data weighted average part (DWA1)
120: Incremental delta sigma modulation section
121:
122: second data weighted average part (DWA2)
123: a second digital-analog converter (DAC2)
124: first integrator
125: second integrator
126: second comparator
130:
131: third integrator
132: third comparator
133: Third digital-analog converter (DAC3)
140: Decimation filter and register

Claims (11)

A coarse analog-to-digital converter (ADC) for generating an MSB (most significant bit) of N bits from the input signal (V _IN ) using success approximation register (SAR) logic,
An incremental delta sigma modulator that multi-stages integrally integrates the input signal using a delta sigma loop and generates an output 1 of M bits through comparison with a reference voltage;
An exponential counting unit for performing a third-order integration of the incremental delta-sigma modulation unit and generating a L-bit output 2 through comparison with a reference voltage,
A decimation filter that receives the MSB, the output 1 and the output 2 to generate a final digital output,
An analog-to-digital converter using a delta-sigma modulation scheme. The method according to claim 1,
In the course ADC,
A first digital-analog converter (DAC1) for converting a digital signal into an analog signal to divide the input signal into a positive number,
A first comparator for comparing the output of the DAC 1 with the input signal and outputting the difference value as bit information;
An SAR logic unit for generating the MSB based on the bit information provided from the first comparator,
A register for storing the generated MSB; and
A first data weighted average unit DWA1 for weighting a bit information of the register and providing the result to the DAC1,
An analog-to-digital converter using a delta-sigma modulation scheme. 3. The method of claim 2,
The SAR logic unit,
To generate a 6-bit MSB
Analog to Digital Converter Using Delta Sigma Modulation. 3. The method of claim 2,
In the DWA1,
The noise of the frequency band of the input signal is lowered through the primary noise shaping effect
Analog to Digital Converter Using Delta Sigma Modulation. 3. The method of claim 2,
Wherein the incremental delta-sigma modulator comprises:
A first integrator for first integrating the input signal,
A second integrator for secondarily integrating the output of the first integrator,
A second comparator for generating the output 1 by comparing a value obtained by multiplying an output of the second integrator by a coefficient and a reference voltage;
Circuit means for feeding back the output 1 of the second comparator to add or subtract digital values to convert the digital value to analog and then provide the input to the first integrator for subtraction with the input signal;
To-digital converter using a delta-sigma modulation scheme. 6. The method of claim 5,
The circuit means comprising:
An adder / subtracter for adding or subtracting a digital value to the output 1 according to an output level of the second comparator,
A second data weighted average unit (DWA2) for weighted-averaging the output of the adder /
A second digital-analog converter (DAC2) for converting the digital output of the second data weighted average part into an analog signal and providing the input digital signal as an input of the first integrator for subtraction with the input signal,
An analog-to-digital converter using a delta-sigma modulation scheme. The method according to claim 6,
The acceleration /
A digital value is added to K + 2 when the output value of the second comparator is "1 ", and a digital value is subtracted to K-2 when the output value is" 0 &
(K is the MSB information stored in the register)
Analog to Digital Converter Using Delta Sigma Modulation. The method according to claim 1,
The expandable-
A third integrator for receiving and integrating the second-order integral output of the incremental delta-sigma modulator;
A third comparator for generating the output 2 by comparing the output of the third integrator with a reference voltage,
A third digital-to-analog converter (DAC3) for converting the digital output of the third comparator to an analog and providing the input to the third integrator for addition with the second integrator output,
An analog-to-digital converter using a delta-sigma modulation scheme. The method according to claim 1,
A high-resolution mode using three operational transconductance amplifiers (OTAs) through the entire driving of the course ADC, the incremental delta-sigma modulator and the scalable counting unit
Analog to Digital Converter Using Delta Sigma Modulation. The method according to claim 1,
And an intermediate resolution mode using two operational transconductance amplifiers (OTA) through selective driving of the course ADC and the incremental delta-sigma modulator
Analog to Digital Converter Using Delta Sigma Modulation. The method according to claim 1,
And can perform a low power mode using one operational transconductance amplifier (OTA) through the selective driving of the course ADC and the expansion type counting unit
Analog to Digital Converter Using Delta Sigma Modulation.

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