KR101898715B1 - Transmitter and shortening method thereof - Google Patents

Abstract

The transmitting apparatus is started. The transmitting apparatus includes an outer encoder for encoding input bits to generate parity bits, a zero padding unit for configuring LDPC information bits including input bits, outer encoded bits including the parity bits, and zero bits, Lt; RTI ID = 0.0 > LDPC < / RTI > encoder.

Description

[0001] TRANSMITTER AND SHORTENING METHOD THEREOF [0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transmitting apparatus and a shortening method thereof, and more particularly, to a transmitting apparatus for performing shortening by padding zero bits and a shortening method thereof.

In the information society of the 21st century, broadcasting and communication services are in the era of full-scale digitalization, multi-channelization, broadband and high-quality. Particularly, as the spread of high-definition digital TVs and mobile broadcast devices has recently expanded, demands for supporting various receiving methods of digital broadcasting services are also increasing.

In response to these demands, the standard group sets various standards and provides various services that satisfy the needs of the users. Accordingly, there is a need to search for ways to provide better services to users through better performance.

It is an object of the present invention to provide a transmitting apparatus that performs shortening based on a preset shortening pattern and a method of shortening the same.

According to another aspect of the present invention, there is provided a transmission apparatus including an outer encoder for generating parity bits by encoding input bits, outer-encoded bits including the input bits and the parity bits, Comprising: a zero padding unit for constructing LDPC information bits comprising bits, and an LDPC encoder for encoding the LDPC information bits, the zero padding including a plurality of bits constituting the LDPC information bits, And padding the zero bits to at least a portion of the group.

Here, the zero padding unit may calculate the number N _pads of the bit groups in which all bits among the plurality of bit groups are padded with zero bits, based on Equation (2) or (3).

The zero padding unit is configured to divide the group of? _S (0) th bit group,? _S (1) th bit group,? _S (N _pad -1) Lt; RTI ID = 0.0 > bits. ≪ / RTI >

Also, the zero padding unit may additionally _pad zero bits to K _ldpc -N _outer -360 x N _pad bits from the first bit of the group of ( _s ) (n _pad ) bits.

Meanwhile, a shortening method of a transmitting apparatus according to an embodiment of the present invention includes generating input parity bits by encoding input bits, including outer bits and zero bits including the input bits and the parity bits, Comprising the steps of: constructing LDPC information bits and encoding the LDPC information word bits, the step of constructing the LDPC information word bits comprises: forming a plurality of LDPC information word groups And padding the zero bits at least in part.

Here, the step of constructing the LDPC information bits may calculate the number N _pads of bits in which all bits of the plurality of bit groups are padded with zero bits, based on Equation (3) or (4).

In addition, the LDPC information bits comprising: configuring the Table 1 to one of the plurality of groups of bits based on _s π (0) th bit group, _s π (1) th group of bits, ..., π _s (N _pad -1) < th > bit group.

Then, the step of configuring said LDPC information bits may further padding the zero bit from the first bit of π _s (N _pad) th bit group K _ldpc -N _{outer pad} -360 × N bits.

According to various embodiments of the present invention as described above, it is possible to position LDPC information bits at a specific position in performing shortening based on a preset shortening pattern, so that bit error rate (BER) and frame error rate ) Performance can be improved.

1 is a block diagram illustrating a configuration of a transmitting apparatus according to an embodiment of the present invention;
FIG. 2 is a view for explaining a shortening procedure according to an embodiment of the present invention; FIG.
3 and 4 are views for explaining a parity check matrix according to an embodiment of the present invention,
FIG. 5 illustrates a parity check matrix having a quasi-cyclic structure according to an embodiment of the present invention. FIG.
6 is a view for explaining a frame structure according to an embodiment of the present invention;
7 and 8 are block diagrams illustrating a detailed configuration of a transmitting apparatus according to an embodiment of the present invention,
9 to 22 are diagrams for explaining a method of processing signaling according to an embodiment of the present invention,
23 and 24 are block diagrams illustrating a configuration of a receiving apparatus according to an embodiment of the present invention,
25 and 26 are views for explaining an example of combining an LLR value of a receiving apparatus according to an embodiment of the present invention,
27 is a diagram illustrating an example in which information on the length of an L1 signal is provided according to an embodiment of the present invention, and
28 shows a flowchart for illustrating a shortening method according to an embodiment of the present invention.

Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.

1 is a block diagram illustrating a configuration of a transmitting apparatus according to an embodiment of the present invention.

Referring to FIG. 1, a transmitting apparatus 100 includes an outer encoder 110, a zero padding unit 120, and an LDPC encoder 130.

The outer encoder 110 encodes the input bits to generate parity bits (or parity check bits).

Herein, the input bits may be information bits. For example, the information bits may be signaling to include information required for the receiving device 200 to receive and process data (e.g., broadcast data) transmitted by the transmitting device 100 have.

The outer code is a code that is performed before the inner code in the concatenated code. The outer code uses various encoding methods such as BCH (Bose, Chaudhuri, Hocquenghem) and CRC (cyclic redundancy check) . In this case, the inner code can be an LDPC code.

For example, the outer encoder 110 encodes the input K _sig bits to generate M _outer parity bits, adds parity bits to the input bits, and outputs N _outer (= K _sig + M _outer ) And output outer-encoded bits composed of bits. In this case, the outer encoded bits may include input bits and parity bits.

In the following description, it is assumed that the outer encoding is performed by the BCH code for convenience of explanation.

That is, the BCH encoder 110 encodes input bits, that is, BCH (Bose, Chaudhuri, Hocquenghem), and outputs parity check bits, that is, BCH parity-check bits (or BCH parity bits) .

For example, the BCH encoder 110 systematically BCH-encodes the input K _sig bits to generate M _outer parity-check bits, adds BCH parity-check bits to the input bits, and outputs N BCH encoded bits comprising _outer (= K _sig + M _outer ) bits, i.e., BCH encoded bits including input bits and BCH parity check bits. In this case, M _outer = 168.

The zero padding unit 120 constitutes LDPC information bits including outer encoded bits and zero bits (i.e., bits having a value of 0) including input bits and parity bits. The zero padding unit 120 may output LDPC information bits to the LDPC encoder 130. [

Specifically, in the case of an LPDC code, a certain number of LDPC information word bits are required according to a code rate and a code length. Accordingly, if the number of BCH encoded bits is less than the number of LDPC required information bits, the zero padding unit 120 may pad the appropriate number of zero bits to match the number of required LDPC information word bits. Thus, the BCH encoded bits and the padded zero bits can constitute as many LDPC information word bits as the number of bits required for LDPC encoding.

On the other hand, since the padded zero bits are bits necessary for matching a specific number of bits for LDPC encoding, they are not transmitted to the receiving apparatus 200 after being LDPC encoded. As described above, a procedure of padding the zero bits or a procedure of padding the zero bits and not transmitting them to the receiving apparatus 200 after LDPC encoding can be referred to as shortening. In this case, the padded zero bits may be referred to as shortening bits (or shortened bits).

For example, if the number of BCH encoded bits, N _outer, is less than the number of LDPC information bits in the LDPC code, K _ldpc , then the transmitting apparatus 100 sends _Kldpc -N _outer zero bits to some of the LDPC information bits Padding to generate LDPC information bits consisting of K _ldpc bits. Accordingly, K _sig + M of _outer BCH encoded bits K _sig + M bits to the _outer zeros have been added, can be _sig K + M + K _{outer ldpc} -N _outer one LDPC information bits are configured.

To this end, the zero padding unit 120 may divide the LDPC information bits into a plurality of bit groups.

Specifically, the zero padding unit 120 may divide the LDPC information word bits into a plurality of bit groups so that the number of bits included in each bit group is 360.

)을 N_{info _group}(=K_ldpc/360) 개의 비트 그룹으로 나눌 수 있다. For example, the zero padding unit 120 generates K _LDPC LDPC information word bits (i ₀ , i ₁ , ..., i 2) based on Equation (1) or Equation

) It can be divided into _{N info _group (= K ldpc /} 360) of bit groups.

는 x보다 크지 않은 최대 정수를 의미한다.Here, Z _j represents the j-th bit group. And,

Means the largest integer not greater than x.

FIG. 2 illustrates an example in which LDPC information bits are divided into a plurality of bit groups according to an embodiment of the present invention. However, in FIG. 2, LDPC parity bits (i.e., LDPC FEC) generated by LDPC encoding of LDPC information bits are also shown.

Referring to Figure 2, of K _ldpc LDPC information word bits are divided into N _{info _group} of bit groups, and may be composed of each bit group Z _j is 360 bits.

For example, assume that the number K _LDPC of LDPC information bits is 3240. In this case, if LDPC information bits are divided into a plurality of groups so that the number of bits included in each bit group is 360, the LDPC information bits can be divided into 9 (= 3240/360) bit groups.

Hereinafter, the shortening procedure performed by the zero padding unit 120 will be described in more detail.

The zero padding unit 120 may calculate the number of zero bits to be padded. That is, the zero padding unit 120 may calculate the number of zero bits to be padded in order to match the number of bits required for LDPC encoding.

Specifically, the zero padding unit 120 may calculate the number of bits equal to the difference between the number of LDPC information bits and the number of BCH encoded bits as the number of zero bits to be padded. That is, when N _outer (= K _sig + M _outer ) is smaller than K _ldpc , the zero padding unit 120 can calculate the number of zero bits to be padded to (K _ldpc -N _outer ).

Then, the zero padding unit 120 may calculate the number N _pads of the bit groups in which all bits among the plurality of bit groups are padded with zero bits, based on Equation (3) or (4) below. That is, the zero padding unit 120 may calculate the number N _pads of bits in which all the bits in the bit group are padded with zero bits, based on Equation (3) or (4) below.

Then, the zero padding unit 120 pads zero bits to at least a part of the plurality of bit groups constituting the LDPC information bits based on the shortening pattern.

Specifically, the zero padding unit 120 determines a bit group to which zero bits are padded among a plurality of groups constituting the LDPC information bits based on the shortening pattern, and determines all the bits in some of the determined bit groups and And may pad some bits in the remaining bit groups with zero bits.

Here, the shortening pattern can be defined as shown in Table 1 below. In this case, Table 1 shows a shortening pattern applied when the LDPC encoder 130 LDPC-encodes 3240 LDPC information bits at a code rate of 3/15 to generate 12960 LDPC parity bits.

Meanwhile, the remaining LDPC codeword bits excluding the padded zero bits in the LDPC codeword composed of the LDPC information bits and the LDPC parity bits can be transmitted to the receiving apparatus 200. In this case, the shortened LDPC codeword (i.e., the remaining LDPC codeword bits excluding the shortened bits, which may be referred to as the LDPC codeword after the shortening) is modulated by QPSK (Quadrature Phase Shift Keying) Lt; / RTI >

Here,? _S (j) represents the shortening pattern order of the j-th bit group. N _{info_group} is the number of the plurality of bit groups constituting the LDPC information bits.

Specifically, the zero padding unit 120 may determine a group of bits where all the bits in the bit group are padded with zero bits based on the shortening pattern, and may pad the zero bits to all the bits of the determined group of bits.

,

,...,

을 비트 그룹 내의 모든 비트들이 제로 비트들로 패딩되는 비트 그룹인 것으로 판단하고, 해당 비트 그룹의 모든 비트들에 제로 비트들을 패딩할 수 있다. 즉, 제로 패딩부(120)는 쇼트닝 패턴에 기초하여 복수의 비트 그룹 중 π_s(0) 번째 비트 그룹, π_s(1) 번째 비트 그룹,..., π_s(N_pad-1) 번째 비트 그룹의 모든 비트들에 제로 비트들을 패딩할 수 있다.That is, the zero padding unit 120 determines, based on the shortening pattern

,

, ...,

Is determined to be a group of bits in which all the bits in the bit group are padded with zero bits and padding the zero bits to all the bits of the corresponding bit group. That is, the zero-padding section 120 of the plurality of groups of bits on the basis of the shortening pattern _s π (0) th bit group, _s π (1) th group of bits, ..., π _s (N _pad -1) th It is possible to pad zero bits to all the bits of the bit group.

,

,...,

을 판단하고, 판단된 비트 그룹 내의 모든 LDPC 정보어 비트들에 제로 비트들을 패딩할 수 있다.As described above, the zero padding unit 120 generates N _pad groups of bits, that is,

,

, ...,

And padding the zero bits to all the LDPC information bits in the determined bit group.

On the other hand, in the case where the number of all zero bits to be padded (K _ldpc -N _outer ) and the number of bit groups in which all bits in a bit group are padded with zero bits are N _pads , the zero padding unit 120 calculates (K _ldpc -N _outer -360 x N _pad ) zeroth bits can be additionally padded.

In this case, the zero padding unit 120 may determine a bit group to which the zero bits are additionally padded based on the shortening pattern, and may additionally pad the zero bits from the beginning of the determined bit group.

를 제로 비트들이 추가적으로 패딩되는 비트 그룹인 것으로 판단하고,

의 앞 부분에 위치하는 (K_ldpc-N_outer-360×N_pad) 개의 비트들에 제로 비트들을 추가적으로 패딩할 수 있다. 즉, 제로 패딩부(120)는 π_s(N_pad) 번째 비트 그룹의 첫 번째 비트부터 (K_ldpc-N_bch-360×N_pad) 개의 비트들에 제로 비트들을 추가적으로 패딩할 수 있다. Specifically, the zero padding unit 120 is configured to generate, based on the shortening pattern,

Lt; RTI ID = 0.0 > 0 < / RTI > bits are additionally padded,

(K _ldpc -N _outer -360 x N _pad ) bits located in the front portion of the bitstream. That is, the zero padding unit 120 can additionally pad zero bits from (K _ldpc -N _bch -360 x N _pad ) bits from the first bit of the group of ( _s ) (n _pad ).

는 일부에만 제로 비트들이 패딩되며, 구체적으로는,

의 첫 번째 LDPC 정보어 비트부터 (K_ldpc-N_outer-360×N_pad) 개의 제로 비트들이 패딩될 수 있다. Accordingly,

Only zero bits are padded in part,

(K _ldpc -N _outer -360 x N _pad ) zero bits can be padded from the first LDPC information bit of

Thereafter, the zero padding unit 120 may configure the LDPC information bits by mapping the BCH encoded bits to bit positions where zero bits are not padded among LDPC information word bits.

)에서 제로 비트들이 패딩되지 않은 비트 위치에 순차적으로 맵핑될 수 있다.Accordingly, N _outer BCH encoded bits are divided into K _ldpc LDPC information word bits (i ₀ , i ₁ ,

), Zero bits may be mapped sequentially to non-padded bit positions.

Hereinafter, a method of padding the zero bits will be described in detail as an example where K _ldpc = 3240 and N _outer = 568. In this case, the LDPC information bits may be divided into 9 (= 3240/360) bit groups

First, the zero padding unit 120 can calculate the number of zero bits to be padded. The number of this case, the bit to be zero padding is _{2672 (= K ldpc -N outer =} 3240-568).

를 산출할 수 있다. Then, the zero padding unit 120 determines the number of bit groups in which all bits are padded with zero bits

Can be calculated.

,

,...,

,

을 비트 그룹 내의 모든 비트들이 제로 비트들로 패딩되는 비트 그룹인 것으로 판단하고,

,

,...,

,

의 모든 비트들에 제로 비트들을 패딩할 수 있다. Then, the zero padding unit 120 determines, based on the shortening pattern

,

, ...,

,

Is a bit group in which all the bits in the bit group are padded with zero bits,

,

, ...,

,

Lt; RTI ID = 0.0 > bits. ≪ / RTI >

Accordingly, all bits of the sixth bit group, the first bit group, ..., the second bit group, and the fourth bit group can be padded with zero bits.

을 제로 비트들이 추가적으로 패딩되는 비트 그룹인 것으로 판단하고,

의 앞 부분에 152(=K_ldpc-N_outer-360×N_pad=3240-568-360×7) 개의 제로 비트들을 추가적으로 패딩할 수 있다. Then, the zero padding unit 120 determines, based on the shortening pattern

Lt; RTI ID = 0.0 > 0 < / RTI > bits are additionally padded,

(= K _ldpc- N _outer -360 x N _pad = 3240-568-360 x 7) of zero bits may be additionally padded in the front part of the frame.

Accordingly, zero bits can be padded from the first bit to the 152th bit in the third bit group.

As a result, among the nine bit groups constituting the LDPC information bits, that is, the 6th bit group, the 1 st bit group, the 7 th bit group, the 8 th bit group, the 0 th bit group Zero bits are padded to all the LDPC information bits of the second group, the second bit group, and the fourth bit group, and zero bits are padded from the first LDPC information word bits to the 152nd LDPC information word bits of the third bit group have.

Thereafter, the zero padding unit 120 can sequentially map the BCH encoded bits to the bit positions where the zero bits are not padded in the LDPC information bits.

For example, when the number of BCH encoded bits N _outer is 568 and the BCH encoded bits are (s ₀ , s ₁ , ..., s ₅₆₇ ), the zero padding unit 120 outputs the third from 153rd LDPC information bits of the bit group to 360th LDPC information bits in the _{(s 0, s 1, ...} , s 207) for mapping, all LDPC information bits of the fifth group of control bits ₍₂₀₈ s , s ₂₀₉ , ..., s ₅₆₇ ).

As described above, the zero padding unit 120 can construct the LDPC information bits by padding the zero bits at appropriate positions to match the number of bits required for LDPC encoding.

In the above example, the information bits are outer-encoded, but this is merely an example. That is, the information bits are not outer-encoded, and LDPC information bits can be configured with zero bits padded according to the number of information bits.

Also, in the above example, zero bits are padded for shortening, but this is merely an example. That is, when shortening is performed such that some of the bits of the LDPC information bits are filled with bits (i.e., information word bits) containing information to be actually transmitted to the receiving apparatus 200, the remaining bits do not transmit substantial information Bits having a predetermined value (for example, 1) in the transceiver may be padded in addition to the zero bit for shortening in that the remaining bits are to fill predetermined bit values between the transmitting and receiving devices.

The LDPC encoder 130 encodes the LDPC information bits, i.e. LDPC encoding.

Specifically, the LDPC encoder 130 systematically LDPC-encodes the LDPC information bits to generate LDPC parity bits, and generates LDPC codewords (or LDPC encoded bits) composed of LDPC information bits and LDPC parity bits Can be output. That is, since the LDPC code is a systematic code, the LDPC codeword can be composed of LDPC information bits before encoding and LDPC parity bits generated by encoding.

)을 LDPC 인코딩하여 N_{ldpc _parity} 개의 LDPC 패리티 비트들 (p₀,p₁,...,)을 생성하고, N_inner(=K_ldpc+N_{ldpc _parity}) 개의 비트들로 구성된 LDPC 코드워드 Λ=(c_o,c₁,...,

)=(i₀,i₁,...,

,p₀,p₁,...,

)를 출력할 수 있다. For example, the LDPC encoder 130 generates K _LDPC LDPC information word bits I = (i ₀ , i ₁ , ...,

) For LDPC encoding the N _{ldpc _parity} of the LDPC parity bits _{(p 0, p 1, ...} , ) And the generation, _inner N (= K + N _{ldpc ldpc _parity)} consisting of one bit LDPC codeword _{Λ = (c o, c 1} , ...,

) = (i ₀ , i ₁ , ...,

, p ₀ , p ₁ , ...,

Can be output.

In this case, the LDPC encoder 130 may LDPC encode the input bits at various code rates to generate an LDPC codeword with a particular length

For example, the LDPC encoder 130 may LDPC encode 3240 input bits at a code rate of 3/15 to generate an LDPC codeword composed of 16200 bits. As another example, the LDPC encoder 130 may LDPC encode 6480 input bits at a code rate of 6/15 to generate an LDPC codeword composed of 16200 bits.

On the other hand, the process for performing LDPC encoding is in terms of generating a LDPC code words to satisfy the H and C ^T = 0, LDPC encoder 130 performs LDPC encoding using the parity check matrix (parity check matrix) can do. Here, H denotes a parity check matrix, and C denotes an LDPC code word.

Hereinafter, a structure of a parity check matrix according to various embodiments of the present invention will be described with reference to the accompanying drawings. The elements of the parity check matrix except for 1 are 0.

For example, the parity check matrix according to an exemplary embodiment of the present invention may have a structure as shown in FIG.

Referring to FIG. 3, the parity check matrix 30 may be composed of five matrices A, B, C, Z, and D. In order to describe the structure of the parity check matrix 30, Will be described.

The matrix A consists of K columns and g rows, and the matrix C consists of K + g columns and NKg rows. Where K (or K _ldpc ) is the length of the LDPC information bits and N (or N _inner ) is the length of the LDPC codeword.

The indexes of the rows in which the 1 in the 0th column of the i-th column group in the matrix A and the column C in the matrix C are 16200 when the length of the LDPC code word is 1600 and the code rate is 3/15, . ≪ / RTI > On the other hand, the number of columns belonging to the same column group can be 360.

Hereinafter, the positions of the rows in which the matrix A and the matrix C have 1s will be described in detail with reference to Table 2 as an example.

On the other hand, when the length of the LDPC codeword is 16200 and the code rate is 3/15, the coding parameters M ₁ , M ₂ , Q ₁ , and Q ₂ based on the parity check matrix 30 are 1080, 11880, to be.

Here, Q ₁ is the size by which the columns belonging to the same column group in the matrix A are cyclic-shifted, and Q ₂ is the size by which the columns belonging to the same column group in the matrix C are cyclically shifted.

_{And, Q 1 = M 1 / L} , and _{Q 2 = M 2 / L,} M 1 = g, M 2 = NKg, L is the interval at which the heat pattern repeat in the matrix A, C respectively, that is, belonging to the same column group The number of columns can be 360, for example.

On the other hand, the index of a row in which 1 is located in each of the matrices A and C can be determined based on the value of M ₁ .

For example, in the case of Table 2, M ₁ = in that it is 1080, the position of the line 1 are present in the 0 th column in i th column groups in the matrix A is determined based on the smaller values than 1080 in index values in Table 2 And the position of a row in which there is 1 in the 0th column of the i-th column group in the matrix C can be determined based on values of 1080 or more among the index values in Table 2. [

Specifically, the sequence corresponding to the 0th column group in Table 2 is " 8 372 841 4522 5253 7430 8542 9822 10550 11896 11988 ". Therefore, in the case of the 0th column of the 0th column group of the matrix A, 1 can be located in the 8th row, 372nd row, and 841st row, and in the 0th column of the 0th column group of the matrix C, , 5253th row, 7430th row, 8542th row, 9822th row, 10550th row, 11896th row, and 11988th row.

On the other hand, in the case of the matrix A, if the position of 1 in the 0th column of each column group is defined, the position of the row in which 1 exists in the other columns of each column group can be defined by Q ₁ , , If the position of 1 in the 0th column of each column group is defined, it can be cyclically shifted by Q ₂ to define the position of the row in which 1 exists in the other columns of each column group.

In the above example, in the 0th column of the 0th column group of the matrix A, 1 exists in the 8th row, the 372nd row, and the 841st row. In this case, since Q ₁ = 3, the index of the row where 1 is located in the first column of the 0th column group is 11 (= 8 + 3), 375 (= 372 + 3), and 844 (= 841 + 3) The index of the row in which the 1 is located in the second column of the 0th column group may be 14 (= 11 + 3), 378 (= 375 + 3), and 847 (= 844 + 3).

On the other hand, in the 0th column of the 0th column group of the matrix C, 1 exists in the 4522th row, 5253th row, 7430th row, 8542th row, 9822th row, 10550th row, 11896th row and 11988th row do. In this case, since Q ₂ = 33, the index of the row in which 1 is located in the first column of the 0th column group is 4555 (= 4522 + 33), 5286 (= 5253 + 33), 7463 (= 8542 + 33), 9855 (= 9822 + 33) 10583 (= 10550 + 33), 11929 The index of the row where the row is located is 4588 (= 4555 + 33), 5319 (= 5286 + 33), 7496 (= 7463 + 33), 8608 (= 8575 + 33), 9888 33), 11962 (= 11929 + 33), and 12054 (= 12021 + 33).

According to this method, the positions of the rows in which 1 exists in all the column groups of the matrix A and the matrix C can be defined.

On the other hand, the matrix B is a dual diagonal matrix, the matrix D is an identity matrix, and the matrix Z is a zero matrix.

As a result, the structure of the parity check matrix 30 as shown in FIG. 3 can be defined by the matrices A, B, C, D, and Z having the above-described structure.

Hereinafter, a method of performing LDPC encoding on the basis of the parity check matrix 30 as shown in FIG. 3 will be described.

)이 시스테메틱하게 인코딩될 수 있다.The LDPC code can be used to encode the information word block S = (s ₀ , s ₁ , ..., s _K-1 ). In this case, in order to generate LDPC codewords Λ = (λ ₀ , λ ₁ , ..., λ _N-1 ) having a length of N = K + M ₁ + M ₂ , parity bits P = (p ₀ , p ₁ , ...,

) Can be systematically encoded.

)가 될 수 있다.Accordingly, the LDPC codeword is expressed as? = (S ₀ , s ₁ , ..., s _K-1 , p ₀ , p ₁ ,

).

Here, each of M ₁ and M ₂ represents the size of the parity matrix corresponding to each of the diagonal diagonal matrix B and the identity matrix D, and M ₁ = g and M ₂ = NKg.

Meanwhile, the process of calculating the parity bit can be expressed as follows. Hereinafter, for convenience of description, a case where the parity check matrix 30 is defined as shown in Table 2 will be described as an example.

Is initialized to the step _{1) λ i = s i (} i = 0,1, ..., K-1), p j = 0 (j = 0,1, ..., M 1 + M 2 -1) .

Step 2) The first information bit? ₀ is accumulated in the parity bit address defined in the first row of Table 1.

Step 3) For the next L-1 information bits? _M (m = 1,2, ..., L-1),? _M is accumulated in the parity bit address calculated on the basis of Equation do.

Here, x is the address of the parity bit accumulator corresponding to the first information bit? ₀ .

Q ₁ = M ₁ / L and Q ₂ = M ₂ / L. In this case, M ₁ = 1080, M ₂ = 11880, Q ₁ = 3, Q ₂ = 33, and L = 360 can be obtained because the length of the LDPC codeword is 16200 and the code rate is 3/15.

Step 4) Similar to the above-described method, in order to give the address of the same parity bit as the second row of Table 2 for the _Lth information bit? _L , the following L-1 information bits? _M (m = L + 1, L + 2, ..., 2L-1) is calculated using the method described in step 3. [ In this case, x is the address of the parity bit accumulator corresponding to the information bit? _L , and can be obtained based on the second row of Table 2.

Step 5) For the L new information bits of each group, the above procedure is repeated with the new rows of Table 2 as the address of the parity bit accumulator.

Step 6) After the above _- described process is repeated from the code word bits? ₀ to? _K-1 , the value for the following Equation 6 is sequentially calculated from i = 1.

까지를 하기의 수학식 7에 기초하여 산출한다. Step 7) from λ _K parity bits corresponding to the dual-diagonal matrix B

Is calculated on the basis of the following expression (7).

까지에 대한 패리티 비트 누적기의 어드레스는 표 2의 새로운 행 및 수학식 5에 기초하여 산출한다. Step 8) from L a new code word bits of each group _K λ

The address of the parity bit accumulator is calculated based on the new row and Equation 5 in Table 2. < tb >< TABLE >

까지 적용된 이후, 대각 행렬 D에 대응되는 패리티 비트

부터

까지를 하기의 수학식 8에 기초하여 산출한다. Step 9) from the code word bits _K λ

, The parity bit corresponding to the diagonal matrix D

from

Is calculated based on the following expression (8).

As a result, the parity bits can be calculated according to this method. However, this is merely an example, and it is needless to say that the method of calculating the parity bits based on the parity check matrix shown in FIG. 3 may be variously defined.

As such, LDPC encoder 130 may perform LDPC encoding based on Table 2 to generate LDPC codewords.

Specifically, the LDPC encoder 130 LDPC-encodes 3240 input bits, i.e., LDPC information bits, at a code rate of 3/15 based on Table 2 to generate 12960 LDPC parity bits, and outputs LDPC parity bits and It is possible to output an LDPC codeword composed of LDPC parity bits. In this case, the LDPC codeword can be composed of 16200 bits.

As another example, the parity check matrix according to an embodiment of the present invention may have a structure as shown in FIG.

4, the parity check matrix 40 includes an information word partial matrix 41, which is a partial matrix corresponding to information word bits (i.e., LDPC information words), and parity bits (i.e., LDPC parity bits And a parity partial matrix 42, which is a partial matrix corresponding to the parity part matrix.

Information word sub-matrix 41 is the parity matrix part 42, and comprises a K _ldpc columns includes N _{ldpc _parity} = N -K _{ldpc inner} columns. On the other hand, the number of rows in the parity check matrix (40) is equal to the number of columns of the parity matrix part (42) N = N _{ldpc _parity inner} -K _ldpc.

In addition, N is the length of the _inner LDPC codeword, K _ldpc is the length of the information bits, N = N _{ldpc _parity inner} -K _ldpc parity check matrix in (40) indicates the length of the parity bits.

Hereinafter, the structure of the information word partial matrix 41 and the parity partial matrix 42 will be described.

The information word partial matrix 41 is a matrix including K _ldpc columns (i.e., the 0th column to the K _ldpc -1 th column), and follows the following rules.

First, the K _ldpc columns constituting the information word submatrix 41 belong to the same group of M and are divided into a total of K _ldpc / M column groups. The columns belonging to the same column group have a cyclic shifted relationship with each other by Q _ldpc . That is, Q _ldpc can be regarded as a cyclic shift parameter value for the columns in the column group of the information word partial matrix constituting the parity check matrix 40.

Here, M is the interval at which the column pattern is repeated in the information word partial matrix 41 (for example, M = 360), and Q _ldpc is the size in which each column is _cyclically shifted in the information word partial matrix 41. M is a common divisor of N _inner and K _ldpc , and Q _ldpc = (N _inner- K _ldpc ) / M is determined. Here, M and Q _ldpc are integers, and K _ldpc / M is an integer. On the other hand, M and Q _ldpc can have various values depending on the length of the LDPC codeword and the code rate.

For example, if M = 360 and the length N _inner of the LDPC codeword is 16200 and the code rate is 6/15, Q _ldpc may be 27.

이라 하면, i 번째 열 그룹 내의 j 번째 열에서 k 번째 1이 위치한 행의 인덱스

는 하기의 수학식 9와 같이 결정된다.Second, the degree of the 0th column of the i-th (i = 0,1, .., K _ldpc / M-1) column group (where the degree is the number of 1 values existing in the column, (Or the index of all the rows belonging to is the same) is _denoted by D _i , and the position (or index) of each row having 1 in the 0th column of the i-th column group is

, The index of the row where the kth 1 is located in the jth column in the ith column group

Is determined according to the following equation (9).

Here, k = 0,1,2, ..., D _i -1, i = 0,1, ..., K _ldpc / M-1, j = 1,2, ..., M-1.

Equation (9) can be expressed equally as Equation (10) below.

Here, k = 0,1,2, ..., D _i -1, i = 0,1, ..., K _ldpc / M-1, j = 1,2, ..., M-1. Here, since (j = 1, 2, ..., M-1), (j mod M) can be viewed as j.

는 i 번째 열 그룹 내의 j 번째 열에서 k 번째 1이 위치한 행의 인덱스, N_inner는 LDPC 부호어의 길이, K_ldpc는 정보어 비트들의 길이, D_i는 i 번째 열 그룹에 속하는 열들의 차수, M은 하나의 열 그룹에 속하는 열의 개수, Q_ldpc는 각 열이 시클릭 쉬프트되는 크기를 의미한다.In these equations,

Where N _inner is the length of the LDPC codeword, K _ldpc is the length of the information bits, D _i is the order of the columns belonging to the ith column group, M is the number of columns belonging to one column group, and Q _ldpc is the size by which each column is _cyclically shifted.

값만을 알면 i 번째 열 그룹 내의 j 번째 열에서 k 번째 1이 있는 행의 인덱스

를 알 수 있게 된다. 그러므로, 각각의 열 그룹 내의 0 번째 열에서 k 번째 1이 있는 행의 인덱스 값을 저장하면, 도 4의 구조를 갖는 패리티 검사 행렬(40)(즉, 패리티 검사 행렬(40)의 정보어 부분 행렬(41))에서 1이 있는 열과 행의 위치가 파악될 수 있다.As a result, referring to these equations

If the value is known only, the index of the row having the kth 1 in the jth column in the ith column group

. Therefore, if the index value of the row having the kth 1 in the 0th column in each column group is stored, the parity check matrix 40 having the structure of FIG. 4 (i.e., the information word partial matrix of the parity check matrix 40) (41), the positions of columns and rows in which 1 is found can be grasped.

According to the above rules, the orders of the columns belonging to the ith column group are all the same as D _i . Accordingly, an LDPC code storing information on a parity check matrix according to the above rules can be briefly expressed as follows.

For example, when N _inner is 30, K _ldpc is 15, and Q _ldpc is 3, the position information of the row in which 1 is located in the 0th column of the 3 column groups is represented by the following mathematical formulas , Which may be referred to as a " weight-1 position sequence ".

는 i 번째 열 그룹 내의 j 번째 열에서 k 번째 1이 있는 행의 인덱스를 의미한다.From here,

Denotes an index of a row having a kth 1 in the jth column in the ith column group.

The weight-1 position sequences such as Equation (11) representing the index of the row where 1 is located in the 0th column of each column group can be expressed more simply as shown in Table 3 below.

Table 3 shows the position of an element having a value of 1 in the parity check matrix. The i-th weight-1 position sequence is represented by indexes of a row having a 1 in the 0-th column belonging to the i-th column group.

Based on the above description, the information word partial matrix 41 of the parity check matrix according to an embodiment of the present invention can be defined by the following Table 4.

Here, Table 4 shows the indexes of the row where 1 is located in the 0th column of the i-th column group of the information word partial matrix 41. [ That is, the information word partial matrix 41 is composed of a plurality of column groups each including M columns, and the position of 1 in the 0th column of each of the plurality of column groups can be defined by Table 4. [

For example, when the length N _inner of the LDPC codeword is 16200, the coding rate is 6/15, and M is 360, the indexes of the row where 1 is located in the 0th column of the i-th column group of the information word submatrix 41 As shown in Table 4 below.

In Table 4, even if the order of the numbers in the sequence corresponding to each i-th column group is changed, the order in the sequence corresponding to each i-th column group in Table 4 is changed And may be one example of codes considered in the present invention.

In addition, even if the order of the sequences corresponding to each column group is changed in Table 4, since the algebraic characteristics such as the cycle characteristic and the order distribution on the graph of the sign do not change, the order of the sequences shown in Table 4 may be changed It can be an example.

In addition, since the algebraic properties such as the cycle characteristic and the order distribution on the graph of the sign do not change as a result of addition of a multiple of Q _ldpc for all the sequences corresponding to arbitrary column groups in Table 4, The result of adding a multiple of Q _ldpc to all of them is an example. The caveat here is if deohaeteul to the multiple Q _ldpc a given sequence if this value out over the value (N -K _{inner ldpc)} has a module for the value _{(N inner -K ldpc) (modulo} ) operation To the value applied.

On the other hand, if the position of the row in which the 1 exists in the 0th column of the i-th column group of the information word partial matrix 41 is defined as shown in Table 4, it is _cyclically shifted by Q _ldpc , The position of the existing row can be defined.

For example, in Table 4, the sequence corresponding to the 0th column of the 0th column group of the information word partial matrix 41 is "27 430 519 828 1897 1943 2513 2600 2640 3310 3415 4266 5044 5100 5328 5483 5928 6204 6392 6416 6602 7019 7415 7623 8112 8485 8724 8994 9445 9667 "Therefore, in the 0th column of the 0th column group of the information word partial matrix 41, 1 exists in the 27th row, the 430th row, the 519th row, do.

In this case, the index of the row in which 1 is located in the first column of the 0th column group is 54 (= 27 + 27), because Q _ldpc = (N _inner - _Kldpc ) / M = (16200-6480) , 457 (= 430 + 27), 546 (= 519 + 27), ..., 81 (= 54 + 27), 484 (= 457 + 27), 573 .

By such a method, an index of a row in which 1 is located in every row of each column group can be defined.

Hereinafter, a method of performing LDPC encoding based on the parity check matrix 40 as shown in FIG. 4 will be described.

이라 한다. First, the information bits to be encoded are denoted by i ₀ , i ₁ , ..., And the calculated code bits are c ₀ , c ₁ , ...,

Quot;

로 설정한다.And, in that the LDPC code that systematic systematic, for _{k (0≤k <K ldpc -1)} , sets a c _k i to _k. On the other hand, in the case of the remaining code bits,

.

Hereinafter, a method of calculating the parity bits p _k will be described.

Hereinafter, q (i, j, 0) represents the jth entry of the ith row in the index list as shown in Table 4, and q (i, j, (i, j, l) = q (i, j, 0) + Q _{ldpc xl} (mod N _inner - _Kldpc ). On the other hand, all accumulation can be realized by additions in the GF (Galois Field) 2. In Table 4, since the length of the LDPC codeword is 16200 and the code rate is 6/15, Q _ldpc is 27.

On the other hand, when q (i, j, 0) and q (i, j, l) are defined as above, a process of calculating a parity bit is as follows.

Step 1) Initialize parity bits to '0'. In other _{words, p k = 0 for 0≤k <} N inner -K ldpc

, l:=k (mod 360)로 설정한다. 여기에서,

는 x 보다 크지 않는 최대 정수이다. Step 2) For all k values of 0 ≤ k <K _ldpc , i and l

, and l: = k (mod 360). From here,

Is the largest integer not greater than x.

Then, for all l, i _k is accumulated in p _{q (i, j, l)} . That _{is, p q (i, 0,} l) = p q (i, 0, l) + i k, p q (i, 1, l) = p q (i, 1, l) + i k, p q _{(i, 2, l) =} p q (i, 2, l) + i k, ..., p q (i, w (i) -1, l) = p q (i, w (i) - _{1, l)} + i _k .

Here, w (i) denotes the number of elements of the i-th row in the index list as shown in Table 4, and the number of 1s in the column corresponding to i _k in the parity check matrix. In Table 4, q (i, j, 0), which is the jth entry of the i-th row, is an index of a parity bit and indicates the position of a row in which 1 exists in the column corresponding to i _k in the parity check matrix.

Specifically, the j-th entry q (i, j, 0) in the i-th row in Table 4 is a row in which 1 exists in the first (i.e., 0th) column in the i-th column group in the LDPC code parity check matrix .

the parity to be generated by the LDPC encoding according to the method of realizing the method of accumulating i _k at _q q (i, j, 0) May be regarded as an index of a bit, or may be regarded as another type of index when another encoding method is implemented. However, this is only one example. Even if any encoding scheme is applied, the LDPC encoding result obtained from the parity check matrix of the LDPC code that can be generated based on the values of q (i, j, 0) It is obvious that it is necessary to obtain an equivalent result.

Step 3) For every k satisfying 0 <k <N _inner- K _ldpc , the parity bit p _k is calculated by calculating p _k = p _k + p _{k- 1} .

이 얻어질 수 있다.Thus, all the code bits c ₀ , c ₁ , ...,

Can be obtained.

As a result, the parity bits can be calculated according to this method. However, this is merely an example, and a method of calculating parity bits based on the parity check matrix as shown in FIG. 4 may be variously defined.

As such, the LDPC encoder 130 may perform LDPC encoding based on Table 4 to generate an LDPC codeword.

Specifically, the LDPC encoder 130 LDPC-encodes 6480 input bits, i.e., LDPC information bits, at a code rate of 6/15 based on Table 4 to generate 9720 LDPC parity bits, and outputs LDPC parity bits and It is possible to output an LDPC codeword composed of LDPC parity bits. In this case, the LDPC codeword can be composed of 16200 bits.

As described above, the LDPC encoder 130 may encode LDPC information word bits at various code rates to generate an LDPC code word.

Here, when the zero padding unit 120 paddes zero bits based on Table 1, the LDPC encoder 130 can LDPC encode LDPC information bits with zero bits padded at a code rate of 3/15 . In this case, the LDPC information bits consist of 3240 bits, and the LDPC parity bits generated by LDPC encoding can be composed of 12960 bits.

Meanwhile, the transmitting apparatus 100 may transmit the LDPC codeword to the receiving apparatus 200.

Specifically, the transmitting apparatus 100 maps the LDPC codeword bits after shortening to constellation symbols using QPSK, maps them to a frame, and transmits the constellation symbols to the receiving apparatus 200.

In the meantime, the transmitting apparatus 100 may transmit the data to the receiving apparatus 200 by mapping the data to the frame together with the signaling for processing the data, in that the information bits are signaling including the signaling information for the data.

Specifically, the transmitting apparatus 100 can process data in a specific manner to generate constellation symbols and map them to data symbols in each frame. Then, the transmitting apparatus 100 can map the signaling for the data mapped to each data to the preamble of the corresponding frame. For example, the transmitting apparatus 100 may map the signaling including the signaling information on the data mapped to the i &lt; th &gt; frame to the i &lt; th &gt;

Accordingly, the receiving apparatus 200 can acquire and process data from the frame using the signaling obtained from the frame.

Hereinafter, a process of deriving a shortening pattern for zero padding will be described as an example.

Specifically, the LDPC encoder 130 encodes 3240 LDPC information bits at a code rate of 3/15 to generate 12960 LDPC parity bits, and the LDPC codeword generated by the LDPC encoding is modulated into QPSK, The procedure for deriving the shortening pattern for zero padding is as follows.

The parity check matrix (for example, FIG. 3) of the LDPC code with the code rate of 3/15 (for example, FIG. 3) is divided into the blocks having the size of 360x360 (i.e., the size of MxM) To a parity check matrix of a quasi-cyclic structure. Here, the row permutation process is a widely used method for the theoretical analysis of LDPC codes since it does not change the algebraic characteristics of LDPC codes. In addition, since a parity check matrix having a quasi-cyclic structure is already known, a detailed description thereof will be omitted.

Obtaining the shortening pattern for zero padding can be regarded as a matter of assigning importance to the column blocks of nine information words existing in the LDPC code with a code rate of 3/15. That is, shortening or zero padding of specific information word bits is equivalent to shortening or eliminating columns corresponding to the information word bits in the parity check matrix. Therefore, when it is assumed that the n bits of the information word should be shortened by the length of the input signaling, it is necessary to find out which n columns are removed from the parity check matrix in terms of BER or FER performance.

In the present invention, the characteristics of the structured LDPC code that the columns in one column block (i.e., a set of 360 consecutive columns) have the same algebraic characteristic and that the number of all information word groups is only nine And a shorting pattern for zero padding is derived in the following manner.

In the first step, the following nine conditions are assumed in the entire parity check matrix and the actual BER and FER performance are measured.

1) If only the bits belonging to the 0th bit group are transmitted and the remaining bits are zero padded

2) If only the bits belonging to the first bit group are transmitted and the remaining bits are zero padded

3) If only the bits belonging to the second bit group are transmitted and the remaining bits are zero padded

4) If only the bits belonging to the third bit group are transmitted and the remaining bits are zero padded

5) If only the bits belonging to the 4th bit group are transmitted and the remaining bits are zero padded

6) If only the bits belonging to the 5th bit group are transmitted and the remaining bits are zero padded

7) If only the bits belonging to the 6th bit group are transmitted and the remaining bits are zero padded

8) If only the bits belonging to the 7th bit group are transmitted and the remaining bits are zero padded

9) If only the bits belonging to the 8th bit group are transmitted and the remaining bits are zero padded

The BER and FER performances obtained in these nine situations are observed, and the bit groups in the case where the best performance is shown and the case where the performance difference is less than a predetermined value (for example, within 0.1 dB) Set as the candidate group of the group. In order to select the group of bits to be shortened last among the bit group candidate groups, a cycle characteristic such as an approximate cycle extrinsic message degree (ACE) value may be additionally considered. The ACE value of a cycle of length 2n is defined as the sum of the values of n variable nodes connected to the cycle minus 2. In the parity check matrix, the column group corresponding to one bit group of the bit group candidate groups is shortened in the remaining matrix and the length is 8 And the number of cycles with an ACE value of 10 or less is checked to select the case where the number of cycles is the smallest. If there are a plurality of such cases, the case in which the actual FER performance is best among the cases is selected. If an excessively large number of selections occur depending on the cycle characteristic based on the ACE value in some cases, an ensemble of LDPC codes having the same distribution of 1 after row deletion, row merging, and row deletion for each case Theoretical predictions for the minimum signal-to-noise (SNR) enabling error free communication are derived through density evolution analysis and the number of choices based on the theoretical minimum SNR values And the FER performance is verified by computer simulation. Accordingly, the fifth bit group can be selected.

The second step for obtaining the shortening pattern is to measure the actual BER and FER performance considering the following eight situations.

1) If only the bits belonging to the 0th bit group and the 5th bit group are carried and the remaining bits are zero padded

2) If only the bits belonging to the 1st bit group and the 5th bit group are loaded and the remaining bits are zero padded

3) If only the bits belonging to the 2nd bit group and the 5th bit group are loaded and the remaining bits are zero padded

4) If only the bits belonging to the 3rd bit group and the 5th bit group are carried and the remaining bits are zero padded

5) If only the bits belonging to the 4th bit group and the 5th bit group are carried and the remaining bits are zero padded

6) If only the bits belonging to the 5th bit group and the 6th bit group are carried and the remaining bits are zero padded

7) If only the bits belonging to the 5th bit group and the 7th bit group are transmitted and the remaining bits are zero padded

8) If only the bits belonging to the 5th bit group and the 8th bit group are carried and the remaining bits are zero padded

These eight situations are about which bit group should be selected when it is necessary to carry out additional information besides the fifth bit group already selected in the first step. The BER and FER performance obtained in these situations are observed, and the bit group of the best performance is selected as the candidate group of the bit group to be shortened immediately before the fifth bit group. The column group corresponding to the 5th bit group in the parity check matrix is shortened and the column group corresponding to one bit group of the bit group candidate groups to be shortened immediately before is further shortened and the length is 8 or less in the remaining matrix The number of cycles with an ACE value of 3 or less can be checked to select the case with the smallest number of cycles. For example, the third bit group can be selected.

As a result, it is possible to obtain a shortening pattern for zero padding as shown in Table 1 by repeating the above procedure until nine bit groups of the entire information word portion are selected. Accordingly, when zero bits are padded based on the shortening pattern shown in Table 1, excellent BER and FER performance can be obtained.

Meanwhile, according to an embodiment of the present invention, the information bits may be implemented by L1 detail signaling (L1-detail signaling). Accordingly, the transmitting apparatus 100 may perform the shortening procedure for the L1 detail signaling using the above-described method and transmit it to the receiving apparatus 200. [

Here, the L1 detail signaling may be the signaling defined in the ATSC (Advanced Television System Committee) 3.0 standard.

In detail, the mode for processing the L1 detail signaling is divided into seven modes. When the transmitter 100 according to the embodiment of the present invention processes L1 detail signaling in the L1 detail mode 2 among the 7 modes, Shortening can be performed.

Meanwhile, in the ATSC 3.0 standard, L1 basic signaling is defined in addition to L1 detail signaling, and the transmitting apparatus 100 processes L1 basic signaling and L1 detail signaling in a specific manner and transmits the L1 basic signaling and the L1 detail signaling to the receiving apparatus 200 . In this case, there are seven modes for processing L1 basic signaling.

A specific method for processing the L1 basic signaling and the L1 detail signaling will be described later.

The transmitting apparatus 100 may map the L1 basic signaling and the L1 detail signaling to the preamble of the frame, and may transmit the data to the receiving apparatus 200 by mapping the data to the data symbol of the frame.

Referring to FIG. 6, a frame may be composed of three parts: a bootstrap part, a preamble part, and a data part.

The bootstrap part is used for initial synchronization and the receiving device 200 provides the basic parameters for decoding the L1 signaling. In addition, the bootstrap part may include information on a mode in which the transmitting apparatus 100 has processed the L1 basic signaling, i.e., information on the mode in which the transmitting apparatus 100 has processed L1 basic signaling.

The preamble part includes L1 signaling and can be composed of two parts: L1 basic signaling and L1 detail signaling.

Herein, the L1 basic signaling includes information on L1 detail signaling, and the L1 detail signaling includes data (here, data is broadcast data for providing a broadcast service, one or more Physical Layer Pipes (PLPs) Which may be transmitted over a wireless network.

Specifically, the L1 basic signaling is a signal that indicates that the receiving apparatus 200 has received the information necessary for processing the L1 detail signaling (for example, information on the mode in which the transmitting apparatus 100 processed the L1 detail signal reel (i.e., Information on the length of the L1 detail signaling, information on the additional parity mode (i.e., L1B_L1_Detail_additional_parity_mode), to generate additional parity bits in the transmitting apparatus 100 Information about the used K value (here, K = 0 when L1B_L1_Detail_additional_parity_mode is set to '00', additional parity bits are not used), and information on the length of total cells). Further, the L1 basic signaling Includes basic signaling information of the system such as FFT (Fast Fourier Transform) size, guard interval and pilot pattern, There is also.

The L1 detail signaling includes information necessary for the receiving apparatus 200 to decode the PLPs (for example, the start position of the cells mapped to the data symbols, the PLP ID, the size of the PLP, the modulation scheme and the coding rate, etc.) .

Accordingly, the receiving apparatus 200 can obtain the synchronization of the frame, obtain the L1 basic signaling and the L1 detail signaling from the preamble, and receive the broadcast data required by the user from the data symbol using the L1 detail signaling.

Hereinafter, a method for processing L1 basic signaling and L1 detail signaling will be described in more detail with reference to the accompanying drawings.

7 and 8 are block diagrams illustrating a detailed configuration of a transmitting apparatus according to an embodiment of the present invention.

7, the transmitting apparatus 100 includes a scrambler 211, a BCH encoder 212, a zero padding unit 213, an LDPC encoder 214, a parity permutation unit 214, A demultiplexer 215, a repetition unit 216, a puncturing unit 217, a zero elimination unit 218, a bit demux 219, and a constellation mapper 221.

8, the transmission apparatus 100 includes a segmentation unit 311, a scrambler 312, a BCH encoder 313, a zero padding unit 314, an LDPC encoder 315, and an LDPC encoder 315 for processing L1 detail signaling. A parity permutation unit 316, a repetition unit 317, a puncturing unit 318, an additional parity generation unit 319, a zero elimination unit 321, a bit demux 322, 324, 325).

7 and 8 are components for performing encoding and modulation for L1 basic signaling and L1 detail signaling, which is only an example, and in some cases, Some of the components shown in Fig. 8 may be omitted or changed, and other components may be further added.

The LDPC encoder 315, the parity permutation unit 316 and the puncturing unit 318 shown in FIG. 8 correspond to the LDPC encoder 110, the parity permutation unit 120 and the puncturing unit 130 Can perform the operations performed by the user.

7 and 8, components for performing a common function will be described for the sake of convenience.

The L1 basic signaling and the L1 detail signaling can be protected by concatenation of the BCH outer code and the LDPC inner code. However, this is merely an example, and other code such as a CRC other than the BCH may be used as the outer code performed before the inner code in the concatenated code. In addition, L1 basic signaling and L1 detail signaling may be protected with only LDPC code without outer code.

First, the L1 basic signaling and the L1 detail signaling can be scrambled. Then, the L1 basic signaling and the L1 detail signaling are BCH encoded, and the BCH parity-check bits of L1 basic signaling and L1 detail signaling generated according to the BCH encoding can be added to L1 basic signaling and L1 detail signaling, respectively. The concatenated signaling and BCH parity check bits can be further protected by shortening and punctured 16K LDPC codes.

On the other hand, in order to provide various robustness levels suitable for a wide SNR range, the protection level of L1 basic signaling and L1 detail signaling can be divided into seven modes. That is, the protection levels of the L1 basic signaling and the L1 detail signal are determined by the LDPC code, the modulation order, the shortening / puncturing parameter (i.e., the ratio of the number of punctured bits to the number of bits to be shortened) and the number of basic puncturing bits (I.e., the number of bits that are basically punctured when the number of bits to be shortened is zero). In each mode, different combinations of at least one of an LDPC code, modulation order, constellation, and a shortening / puncturing pattern may be used.

On the other hand, the mode in which the transmitting apparatus 100 processes the signaling may be preset according to the system. Accordingly, the transmitting apparatus 100 transmits a parameter for processing signaling according to the set mode (for example, a modulation and code rate for each mode, a parameter for BCH encoding, a parameter for zero padding, a shortening pattern, an LDPC Code-rate / code length of code, group-wise interleaving pattern, parameters for repetition, parameters for puncturing, and modulation scheme, etc.), processes the signaling based on the determined parameters, Lt; / RTI &gt; To this end, the transmitting apparatus 100 may store parameters for processing signaling according to a mode.

The ModCod configuration (modulation and code rate configurations) for seven modes for processing L1 basic signaling and seven modes for processing L1 detail signaling are shown in Table 5 below. The transmitting device 100 may encode and modulate signaling based on the ModCod configuration defined in Table 5, depending on the mode. That is, the transmitting apparatus 100 can determine the encoding and modulation scheme for the signaling in each mode based on Table 5, and can encode and modulate the signaling according to the determined scheme. In this case, the transmission apparatus 100 may use different constellations even when L1 signaling is modulated by the same modulation scheme.

In Table 5, K _sig denotes the number of information bits for a coded block. That is, the L1 signaling bits are encoded with a length of K _sig in that the coded block produced, the length of the L1 signaling in a coded block is of the K _sig. Thus, the L1 signaling bits with a size of K _sig can be seen to correspond to one LDPC coded block.

Referring to Table 5, the K _sig value for L1 basic signaling is fixed at 200. However, since the amount of L1 detail signaling bits is variable, the K _sig value for L1 detail signaling is variable.

Specifically, in the case of L1 detail signaling, if the number of L1 detail signaling bits is variable, the number of L1 detail signaling bits is variable, then the L1 detail signaling can be segmented to have a length less than a predetermined value.

In this case, the size of each of the segmented L1 detail signaling blocks (i.e., the segments of the L1 detail signaling) may have a K _sig value defined in Table 5. [ Then, the segments L1 signaling block detail each having a size of K _sig may correspond to a single LDPC coded blocks.

However, if the number of L1 detail signaling bits is less than or equal to a preset value, the L1 detail signaling is not segmented. In this case, the size of the L1 detail signaling may have a K _sig value defined in Table 5. [ And, the L1 detail signaling having the size of K _sig can correspond to one LDPC coded block.

Hereinafter, a method of segmenting the L1 detail signaling will be described in detail.

The segmentation section 311 segments the L1 detail signaling. Specifically, the length of the L1 detail signaling is variable, and when the length of the L1 detail signaling is longer than a predetermined value, the segmentation unit 311 segments the L1 detail signaling so as to have bits of a predetermined value or less, And outputs the L1 detail signaling to the scrambler 312.

However, if the length of the L1 detail signaling is less than or equal to a preset value, the segmenting unit 311 does not perform a separate segmentation operation.

On the other hand, a method of segmenting L1 detail signaling by the segmentation unit 311 is as follows.

The amount of L1 detail signaling bits is variable and is primarily dependent on the number of PLPs. Accordingly, at least one forward error correction (FEC) frames are required to transmit the entire L1 detail signaling. Here, the FEC frame may be a form in which L1 detail signaling is encoded, and parity bits according to encoding are added to L1 detail signaling.

Specifically, if L1 detail signaling is not segmented, one FEC frame is required for L1 detail signaling transmission because L1 detail signaling is BCH encoded and LDPC encoded to generate one FEC frame. On the other hand, if the L1 detail signaling is segmented into at least two segments, at least two segmented L1 detail signaling are BCH encoded and LDPC encoded, respectively, so that at least two FEC frames are generated, so that at least two FEC frames for L1 detail signaling transmission Is required.

Therefore, the segmentation unit 311 can calculate the number _{NLDD_FECFRAME} of FEC frames for L1 detail signaling based on Equation (12) below. That is, the number of FEC frames N _{L1D_FECFRAME} for L1 detail signaling can be determined based on Equation (12) below.

은 x보다 크거나 같은 최소 정수를 의미한다.From here,

Means a minimum integer greater than or equal to x.

9, K _{L1D_ex_pad} indicates the length of the L1 detail signaling excluding the L1 padding bits, and may be determined by the value of the L1B_L1_Detail_size_bits field included in the L1 basic signaling.

Also, K _seg is a threshold number for the segmentation which is defined based on the number of information bits input to the LDPC encoder 315, i.e., the number K _LDPC of the LDPC information bits. Also, K _seg can be defined based on the number of BCH parity-check bits of the BCH code and a multiple of 360.

On the other hand, K _seg is such that less than or equal to the number of after segmentation, information bits from the coded block K _sig (K -M _{outer ldpc).} Specifically, K If the segmentation for L1 detail the signaling based on _seg, the length of the segment L1 detail signaling if, in that do not exceed the K _seg, set as shown in Table 6 to the K _seg, the segments L1 The length of the detail signaling is less than or equal to (K _{ldpc -} M _outer ).

Here, M _outer and K _ldpc are shown in Tables 7 and 8. On the other hand, for sufficient robustness, the K _seg value for L1 detail mode 1 may be set to (K _ldpc -M _outer- 720).

Meanwhile, K _seg for each mode of L1 detail signaling can be defined as shown in Table 6 below. In this case, the segmentation unit 311 can determine K _seg according to the mode based on Table 6. [

On the other hand, as shown in FIG. 9, the entire L1 detail signaling may be composed of L1 detail signaling and L1 padding bits.

In this case, the segmentation unit 311 can calculate the length of the L1_PADDING field for L1 detail signaling, that is, the number of L1 padding bits K _{L1D_PAD} based on Equation (13) below.

However, calculating K _{L1D_PAD} based on Equation (13) is only an example. That is, the segmentation unit 311 may calculate the length of the L1_PADDING field for the L1 detail signaling, that is, the number of L1 padding bits K _{L1D_PAD} based on the K _{L1D_ex_pad} and N _{L1D_FECFRAME} values. As an example, the K _{L1D_PAD} value can be obtained based on the following equation (13). That is, Equation (13) is an example of a method of obtaining the K _{L1D_PAD} value, and may be applied through other methods based on the values of K _{L1D_ex_pad} and N _{L1D_FECFRAME} so that the same result is obtained.

Then, the segmentation unit 311 can fill the L1_PADDING part with K _{L1D_PAD} zero bits (i.e., bits having a value of 0). Accordingly, as shown in FIG. 9, zero bits of K _{L1D_PAD} can be filled in the L1_PADDING part.

In this manner, when segmenting the L1 detail signaling by calculating the length of the L1_PADDING field and padding the zero bits of the calculated length to the L1_PADDING part, the L1 detail signaling is segmented into a plurality of blocks each composed of the same number of bits .

Thereafter, the segmenting unit 311 may calculate the final length K _L1D of the entire L1 detail signaling including zero padding bits based on Equation (14) below.

Then, the segmentation unit 311 to the number of information bits in each of the N _{L1D_FECFRAME} blocks based on equation (15) can calculate the K _sig.

Thereafter, the segmentation unit 311 can segment the entire L1 detail signaling by the number of K _sig bits.

Specifically, as shown in FIG. 9, when the N _{L1D_FECFRAME} is greater than 1, the segmentation unit 311 _{segments the} entire L1 detail signaling by K _sig bits, and _{segments the} entire L1 detail signaling into N _{L1D_FECFRAME} blocks have.

Accordingly, details L1 signaling is _{L1D_FECFRAME} segmentation into N blocks, each block in N _{L1D_FECFRAME} of the number of L1 signaling bits detail may be a K _sig. Also, in the segment L1 detail signaling each is encoded, that is, the coded block as the encoding result, in that they form an FEC frame, in the end, N _{L1D_FECFRAME} of coding blocks each number of L1 detail the signaling bits can be K _sig have.

However, if L1 detail signaling is not segmented, K _sig = K _{L1D_ex_pad} .

On the other hand, the segmented L1 detail signaling block can be encoded by the following procedure.

Specifically, L1 signaling detail all the bits in the block information word, each having a size of K _sig it can be scrambled. Each of the scrambled L1 detail signaling blocks may then be encoded by concatenation of the BCH outer code and the LDPC inner code.

Specifically, each of the L1 detail signaling blocks is BCH encoded so that M _outer (= 168) BCH parity-check bits are added to the K _sig L1 detail signaling bits of each block, and then the L1 detail signaling bits of each block The concatenation of the BCH parity-check bits may be encoded by shortening and punctured 16K LDPC codes. Concrete contents related to the BCH code and the LDPC code will be described later. However, in the present invention, only M _outer = 168 is explained, but it is obvious that it can be changed to an appropriate value according to the requirements of the system.

Scramblers 211 and 312 scramble L1 basic signaling and L1 detail signaling. Specifically, the scramblers 211 and 312 may randomize the L1 basic signaling and the L1 detail signaling, and output the randomized L1 basic signaling and the L1 detail signaling to the BCH encoders 212 and 313, respectively.

In this case, the scramblers 211 and 312 can scramble every K _sig information words.

That is, the scrambler 211 can scramble every K _sig (= 200) L1 basic signaling bits in that the number of L1 basic signaling bits transmitted to the receiving apparatus 200 through each frame is 200. [

Meanwhile, the L1 detail signaling may be segmented by the segmentation unit 311 in some cases, since the number of L1 detail signaling bits transmitted to the reception apparatus 200 through each frame is variable. The segmentation unit 311 may output L1 detail signaling composed of K _sig bits or segmented L1 detail signaling to the scrambler 312. Accordingly, the scrambler 312 can scramble every K _sig L1 detail signaling bits output from the segmentation unit 311. [

BCH encoders 212 and 313 BCH encode L1 basic signaling and L1 detail signaling to generate BCH parity-check bits.

Specifically, the BCH encoders 212 and 313 perform BCH encoding on L1 basic signaling and L1 detail signaling output from the scramblers 211 and 313 to generate BCH parity check bits, and perform BCH parity (LCH) on each of L1 basic signaling and L1 detail signaling, The BCH encoded bits to which the check bits are added can be output to the zero padding units 213 and 314.

For example, the BCH encoders 212 and 313 perform BCH encoding of the K _sig bits input thereto (i.e., K _sig = K _payload ) to generate M _outer BCH parity check bits, and N _outer (= K _sig + M _outer ) bits of the BCH encoded bits to the zero padding units 213 and 314.

On the other hand, the parameters for the BCH encoding can be defined as shown in Table 7 below.

7 and 8, it can be seen that the LDPC encoders 214 and 315 are arranged after the BCH encoders 212 and 313.

Accordingly, the L1 basic signaling and the L1 detail signaling can be protected by the concatenation of the BCH outer code and the LDPC inner code.

Specifically, the L1 basic signaling and the L1 detail signaling are BCH encoded so that the BCH parity-check bits for the L1 basic signaling are added to the L1 basic signaling and the BCH parity-check bits for the L1 detail signaling are added to the L1 detail signaling. The concatenated L1 basic signaling and BCH parity check bits are additionally protected by the LDPC code, and the concatenated L1 detail signaling and BCH parity check bits can be further protected by the LDPC code.

Here, in the BCH encoders 212 and 313, N _inner = 16200 (i.e., the code length of the 16K LDPC code is 16200, and the LDPC code words generated by the LDPC encoding are 16200 Bits) may be used for outer encoding of L1 basic signaling and L1 detail signaling.

The zero padding units 213 and 314 padding the zero bits. Specifically, in the case of an LDPC code, the zero padding units 213 and 314 are arranged such that the number of BCH encoded bits is the number of LDPC information bits , It can padd the zero bits for LDPC encoding, generate a certain number of LDPC information bits composed of BCH encoded bits and zero bits, and output it to the LDPC encoders 214 and 315. On the other hand, if the number of BCH encoded bits is equal to the number of LDPC information bits, the zero bits are not padded.

Here, since the zero bits padded by the zero padding units 213 and 314 are padded for LDPC encoding, zero bits padded according to the shortening are not transmitted to the receiving apparatus 200. [

For example, if the number of LDPC information bits in the 16K LDPC code is K _ldpc , some of the LDPC information word bits may be padded with zero bits to fill the K _ldpc LDPC information word bits.

Specifically, when the number of BCH encoded bits is N _outer , the number of LDPC information word bits of a 16K LDPC code is K _ldpc , and N _outer &lt; K _ldpc , the zero padding units 213 and 314 are part of LDPC information word bits It is possible to generate LDPC information bits consisting of K _ldpc bits by padding K _ldpc -N _outer bits with zero and using N _outer BCH encoded bits as the remainder of the LDPC information bits. However, when N _outer = K _ldpc , the zero bits are not padded.

To this end, the zero padding units 213 and 314 may divide the LDPC information bits into a plurality of bit groups.

)을 N_{info_group}(=K_ldpc/360) 개의 비트 그룹으로 나눌 수 있다. 즉, 제로 패딩부(213, 314)는 각 비트 그룹에 포함된 비트들의 수가 360이 되도록, LDPC 정보어 비트들을 복수의 비트 그룹으로 나눌 수 있다. For example, the zero padding units 213 and 314 generate K _ldpc LDPC information word bits (i ₀ , i ₁ , ..., k) based on the following Equation (16) or (17)

) It can be divided into two groups of bits _{N info_group (= K ldpc / 360} ). That is, the zero padding units 213 and 314 may divide the LDPC information word bits into a plurality of bit groups so that the number of bits included in each bit group is 360.

Here, Z _j represents the j-th bit group.

On the other hand, L1 parameters for zero padding for basic signaling and the L1 signaling detail _{(N outer, K ldpc, N} info_group) can be defined is as shown in Table 8 below. In this case, the zero padding units 213 and 314 can determine the parameters for zero padding according to the mode based on Table 8. &lt; tb &gt;&lt; TABLE &gt;

Also, for 0? _J <N _{info_group} , each bit group Z _j may be composed of 360 bits as shown in FIG.

Specifically, FIG. 10 shows the data format after each of the L1 basic signaling and the L1 detail signaling is LDPC-encoded. The LDPC FEC added to the K _ldpc LDPC information bits in FIG. 10 represents LDPC parity bits generated by LDPC encoding.

Referring to Figure 10, K _ldpc of LDPC information word bits are divided into N groups _{info_group} bits, each bit group can be made up of 360 bits.

On the other hand, when the number of BCH encoded bits N _outer (= K _sig + M _outer ) for L1 basic signaling and L1 detail signaling is smaller than K _ldpc , i.e., N _outer (= K _sig + M _outer ) &lt; K _ldpc For LDPC encoding, K _LDPC LDPC information bits may be filled with N _outer BCH encoded bits and (K _ldpc -N _outer ) zero-padded bits. In this case, the padded zero bits are not transmitted to the receiving apparatus 200.

Hereinafter, the shortening procedure performed by the zero padding units 213 and 314 will be described in more detail.

The zero padding units 213 and 314 can calculate the number of zero bits to be padded. That is, the zero padding units 213 and 314 may calculate the number of zero bits to be padded in order to match the number of bits required for LDPC encoding.

Specifically, the zero padding units 213 and 314 may calculate the number of bits equal to the difference between the number of LDPC information bits and the number of BCH encoded bits as the number of zero bits to be padded. That is, the zero padding units 213 and 314 can calculate the number of zero padding bits (K _ldpc -N _outer ) for a given N _outer .

The zero padding units 213 and 314 can calculate the number of bit groups in which all bits are padded. That is, the zero padding units 213 and 314 can calculate the number of bit groups in which all the bits in the bit group are padded with zero bits.

Specifically, the zero padding units 213 and 314 can calculate the number N _pads of groups in which all the bits are padded based on Equation (18) or (19) below.

Then, the zero padding units 213 and 314 judge a bit group to which the zero bits of the plurality of groups are padded, based on the shortening pattern, and determine whether all the bits in some of the determined bit groups and a part Bits can be padded with zero bits.

In this case, the shortening pattern of the bit group to be padded can be defined as shown in Table 9 below. In this case, the zero padding units 213 and 314 can determine the shortening pattern according to the mode based on Table 9. [

Here,? _S (j) is an index of a jth padded bit group. That is, π _s (j) represents the shortening pattern order of the j-th bit group. N _{info_group} is the number of a plurality of bit groups constituting LDPC information bits.

,

,...,

을 비트 그룹 내의 모든 비트들이 제로 비트들로 패딩되는 비트 그룹으로 판단하고, 해당 비트 그룹의 모든 비트들에 제로 비트들을 패딩할 수 있다. 즉, 제로 패딩부(213, 314)는 쇼트닝 패턴에 기초하여 복수의 비트 그룹 중 π_s(0) 번째 비트 그룹, π_s(1) 번째 비트 그룹,..., π_s(N_pad-1) 번째 비트 그룹의 모든 비트들에 제로 비트들을 패딩할 수 있다.Specifically, the zero padding units 213 and 314 are configured to generate, based on the shortening pattern,

,

, ...,

May be determined as a group of bits in which all the bits in the bit group are padded with zero bits and all bits in the group of bits may be padded with zero bits. In other words, the zero padding units 213 and 314 select a group of π _s (0) th bit group, π _s (1) th bit group, ..., π _s (N _pad -1 ) &Lt; / RTI &gt; th bit group.

,

,...,

을 판단하고, 판단된 비트 그룹 내의 모든 LDPC 정보어 비트들에 제로들을 패딩할 수 있다In this way, when N _pad is not 0, the zero padding units 213 and 314 _compute a list of N _pad group of bits, that is,

,

, ...,

And padding zeros to all LDPC information bits in the determined bit group

However, when N _pad is 0, the above procedure can be omitted.

On the other hand, the number of zero bits padded (K _ldpc -N _outer ) and the number of zero bits padded to N _pad groups of bits is (360 x N _pad ), the zero padding units 213 and 314 K _ldpc- N _outer -360 x N _pad ) LDPC information bits can be additionally padded with zero bits.

In this case, the zero padding units 213 and 314 may determine a bit group to which the zero bits are additionally padded based on the shortening pattern, and may additionally pad the zero bits from the beginning of the determined bit group.

를 제로 비트들이 추가적으로 패딩되는 비트 그룹인 것으로 판단하고,

의 앞 부분에 위치하는 (K_ldpc-N_outer-360×N_pad) 개의 비트들에 제로 비트들을 추가적으로 패딩할 수 있다. 이에 따라, π_s(N_pad) 번째 비트 그룹의 첫 번째 비트부터 (K_ldpc-N_outer-360×N_pad) 개의 제로 비트들이 패딩될 수 있다. Specifically, the zero padding units 213 and 314 are configured to generate, based on the shortening pattern,

Lt; RTI ID = 0.0 &gt; 0 &lt; / RTI &gt; bits are additionally padded,

(K _ldpc -N _outer -360 x N _pad ) bits located in the front portion of the bitstream. Accordingly, zero bits (K _ldpc -N _outer -360 x N _pad ) can be padded from the first bit of the group of bits of n _s (N _pad ).

의 경우,

의 처음 부분에 위치한 (K_ldpc-N_bch-360×N_pad) 개의 LDPC 정보어 비트들에 제로들이 추가적으로 패딩될 수 있다.finally,

In the case of,

Zeros may be additionally padded to the ( _LDPC - _Nbch -360 x N _pad ) LDPC information bits located at the beginning of the LDPC information bits.

의 첫 번째 비트부터 (K_ldpc-N_outer-360×N_pad) 개의 제로 비트들이 패딩되는 것으로 설명하였으나 이는 일 예에 불과하며,

에서 제로 비트들이 패딩되는 위치는 변경될 수 있다. 예를 들어, (K_ldpc-N_outer-360×N_pad) 개의 제로 비트들은

의 중간 부분 또는 마지막 부분에 패딩되거나,

의 임의 위치에 패딩될 수도 있다.On the other hand, in the above example

(K _ldpc -N _outer -360 x N _pad ) _zeroth bits are padded from the first bit of the first bit, but this is merely an example,

The positions where the zeroth bits are padded may be changed. For example, (K _ldpc -N _outer -360 x N _pad ) zeros bits

Lt; / RTI &gt; is padded at the middle or last portion of the &lt;

As shown in FIG.

Thereafter, the zero padding units 213 and 314 may configure the LDPC information bits by mapping the BCH encoded bits to non-padded bit positions in the LDPC information bits.

)에서 제로 비트들이 패딩되지 않은 비트 위치에 순차적으로 맵핑되어, N_outer 개의 BCH 인코딩된 비트들 및 (K_ldpc-N_outer) 개의 정보어 비트들에 의해 K_ldpc 개의 LDPC 정보어 비트들이 구성될 수 있다.Accordingly, N _outer BCH encoded bits are divided into K _ldpc LDPC information word bits (i ₀ , i ₁ ,

, Zero bits are sequentially mapped to non-padded bit positions so that K _ldpc LDPC information bits can be constructed by N _outer BCH encoded bits and (K _ldpc -N _outer ) have.

On the other hand, the padded zero bits are not transmitted to the receiving apparatus 200. The procedure of padding the zero bits or the procedure of padding the zero bits and not transmitting the zero bits to the receiving apparatus 200 after LDPC encoding can be referred to as shortening.

LDPC encoders 214 and 315 LDPC encode L1 basic signaling and L1 detail signaling.

Specifically, the LDPC encoders 214 and 315 perform LDPC encoding on the LDPC information bits output from the zero padding units 213 and 314 to generate LDPC parity bits, and generate LDPC parity bits and LDPC information bits composed of LDPC information bits and LDPC parity bits. The codeword can be output to the parity permutation units 215 and 316.

)을 구성할 수 있다. That is, the K _ldpc bits output from the zero padding unit 213 include K _sig L1 basic signaling bits, M _outer (= N _outer- K _sig ) BCH parity check bits, and (K _ldpc -N _outer ) And may include zero padding bits, which may include K _ldpc LDPC information bits I = (i ₀ , i ₁ , ...,

).

)을 구성할 수 있다. The K _ldpc bits output from the zero padding unit 314 include K _sig L1 detail signaling bits, M _outer (= N _outer- K _sig ) BCH parity check bits, and (K _ldpc -N _outer ) And may include zero padding bits, which may include K _ldpc LDPC information bits I = (i ₀ , i ₁ , ...,

).

)=(i₀,i₁,...,

,p₀,p₁,...,

)를 생성할 수 있다.In this case, LDPC encoder (214, 315) of K _ldpc LDPC information bits in the systematic LDPC encoding by the schematic, N _inner bits of the LDPC codeword Λ = consisting of _{(c 0, c 1, ...} ,

) = (i ₀ , i ₁ , ...,

, p ₀ , p ₁ , ...,

Can be generated.

Meanwhile, the LDPC encoders 214 and 315 encode L1 basic signaling and L1 detail signaling at a code rate of 3/15 in the case of L1 basic modes and L1 detail modes 1 and 2 to generate 16,200 LDPC code word bits . In this case, the LDPC encoders 214 and 315 can perform encoding based on Table 2.

In addition, the LDPC encoder 315 may encode the L1 detail signaling at a code rate of 6/15 to generate 16,200 LDPC codeword bits for L1 detail modes 3, 4, 5, 6 and 7. In this case, the LDPC encoder 315 can perform encoding based on Table 4.

Table 5 shows the code rate and code length for L1 basic signaling and L1 detail signaling, and Table 8 shows the number of LDPC information word bits.

The parity permutation units 215 and 316 perform parity permutation. That is, the parity permutation units 215 and 316 may perform permutation only for the LDPC parity bits except the LDPC information bits.

Specifically, the parity permutation units 215 and 316 perform permutation only for the LDPC parity bits among the LDPC codewords output from the LDPC encoders 214 and 315, and output the parity- (216, 317). The parity permutation unit 316 may output the parity-permutated LDPC codeword to the additional parity generation unit 319. In this case, the additional parity generation unit 319 may generate additional parity bits using the parity-permuted LDPC codeword output from the parity permutation unit 316. [

To this end, the parity permutation units 215 and 316 may include a parity interleaver (not shown) and a group-wise interleaver (not shown).

First, a parity interleaver (not shown) can interleave only LDPC parity bits among LDPC information bits and LDPC parity bits constituting an LDPC codeword. However, the parity interleaver (not shown) can perform parity interleaving only in the L1 detail modes 3, 4, 5, 6, and 7. That is, in the case of L1 basic modes and L1 detail modes 1 and 2, parity interleaving is included as part of the LDPC encoding process. In the case of L1 basic modes and L1 detail modes 1 and 2, May not perform parity interleaving.

Meanwhile, in a mode for performing parity interleaving, a parity interleaver (not shown) may interleave LDPC parity bits based on Equation (20) below.

)는 패리티 인터리버(미도시)에 의해 패리티 인터리빙되며, 패리티 인터리버(미도시)의 출력은 U=(u₀,u₁,...,

)로 나타내어질 수 있다. Specifically, according to Equation 20, LDPC codeword _{(c 0, c 1, ...} ,

) Is parity interleaved by a parity interleaver (not shown), and the output of the parity interleaver (not shown) is U = (u ₀ , u ₁ , ...,

). &Lt; / RTI &gt;

)은 하기의 수학식 21과 같이 나타내어질 수 있다.On the other hand, in the case of the L1 basic modes and the L1 detail modes 1 and 2, the output U = (u ₀ , u ₁ , ..., u ₀ ) of the parity interleaver (not shown)

) Can be expressed by the following equation (21).

Meanwhile, a group-wise interleaver (not shown) can group-wise interleave the output of a parity interleaver (not shown).

Here, as described above, the output of the parity interleaver (not shown) is an LDPC codeword parity-interleaved by a parity interleaver (not shown) or an LDPC codeword that is not parity interleaved by a parity interleaver .

Accordingly, when the parity interleaving is performed, the group-wise interleaver (not shown) performs group-wise interleaving of the parity-interleaved LDPC codewords, and when the parity interleaving is not performed, Code words can be group-wise interleaved.

Specifically, the group-wise interleaver (not shown) can interleave the output of the parity interleaver (not shown) in units of bit groups.

To this end, the group-wise interleaver (not shown) may divide the LDPC codeword output from the parity interleaver (not shown) into a plurality of bit groups. Accordingly, the LDPC parity bits output from the parity interleaver (not shown) can be divided into a plurality of bit groups.

)을 N_group(=N_inner/360) 개의 비트 그룹으로 나눌 수 있다. Specifically, the group-wise interleaver (not shown) converts the LDPC-encoded bits u ₀ , u ₁ , ..., u ₂ output from the parity interleaver (not shown)

) Can be divided into N _groups (= N _inner / 360) bit groups.

Here, X _j represents the j-th bit group.

11 shows an example of dividing an LDPC code word output from a parity interleaver (not shown) into a plurality of bit groups.

Referring to FIG. 11, the LDPC code word is divided into N _groups (= N _inner / 360) bit groups, and each bit group X _j consists of 360 bits for 0? _J <N _group .

Accordingly, LDPC information bits consisting of K _ldpc bits are (K _ldpc / 360) is divided into two bit groups, N -K _{inner ldpc} bits of LDPC parity bits are comprised of (N _inner -K _ldpc) / It can be divided into 360 bit groups.

The group-wise interleaver (not shown) performs group-wise interleaving of the LDPC code words output from the parity interleaver (not shown).

In this case, the group-wise interleaver (not shown) interleaves only the LDPC parity bits without interleaving the LDPC information bits, thereby changing the order of the plurality of bit groups constituting the LDPC parity bits have.

Accordingly, the LDPC information bits of the LDPC bits are not interleaved by the group-wise interleaver (not shown), but the LDPC parity bits of the LDPC bits can be interleaved by the group-wise interleaver (not shown). In this case, the LDPC parity bits may be interleaved on a group basis.

Specifically, the group-wise interleaver (not shown) can group-wise interleave the LDPC codewords output from the parity interleaver (not shown) based on Equation (23) below.

Here, Y _j denotes a group-wise interleaved j-th bit group, and X _j denotes a j-th bit group among a plurality of bit groups constituting the LDPC codeword, that is, the j-th bit group before group-wise interleaving. And? _P (j) represents a permutation order for group-wise interleaving.

On the other hand, the permutation order can be defined based on Tables 10 and 11 below. Table 10 shows the group-wise interleaving pattern of the parity parts for the L1 basic modes and the L1 detail modes 1 and 2, and Table 11 shows the group-wise interleaving patterns of the parity part for the L1 detail modes 3, 5, Group-wise interleaving pattern.

In this case, the group-wise interleaver (not shown) can determine the group-wise interleaving pattern according to the mode based on Table 10 and Table 11. [

Hereinafter, the operation of the group-wise interleaver (not shown) will be described as an example of the group-wise interleaving pattern for the L1 detail mode 2.

In the L1 detail mode 2, the LDPC encoder 315 LDPC encodes 3240 LDPC information bits at a code rate of 3/15 to generate 12960 LDPC parity bits. In this case, the LDPC codeword can be composed of 16200 bits.

Since each bit group is composed of 360 bits, an LDPC codeword composed of 16200 bits is divided into 45 bit groups.

Here, since the LDPC information bits are 3240 and the LDPC parity bits are 12960, the 0th to 8th bit groups correspond to LDPC information bits, the 9th to 44th bit groups correspond to LDPC parity Bits.

In this case, the parity interleaver (not shown) does not perform the parity interleaving, and the group-wise interleaver (not shown) calculates the bit group constituting the LDPC information bits The 8th bit group is not interleaved and the bit groups constituting the LDPC parity bits are interleaved for the 44th bit group from the 9th bit group to the 9th bit group to the 44th bit group, Can be changed.

Specifically, if the L1 detail mode 2, the table 10, the equation (23) is _{Y 0 = X 0, Y 1} = X 1, ..., Y 7 = X 7, Y 8 = X 8, Y 9 = _{X πp (9) = X 9} , Y 10 = X πp (10) = X 31, _{Y 11 = X πp (11)} = X 23, ..., Y 42 = X πp (42) = X 28, Y 43 = X πp (43) = X 39, Y 44 = X πp (44) = X ₄₂ , respectively.

Accordingly, the group-wise interleaver (not shown) does not change the order of the 0-th bit group to the 8-th bit group including the LDPC information bits, but the ninth bit group including the LDPC parity bits, Can be changed.

Specifically, in the group-wise interleaver (not shown), the ninth bit group is ninth, the 31st bit group is 10th, the 23rd bit group is 11th, ..., the 28th bit group is 42th, The order of the bit groups from the ninth bit group to the 44th bit group can be changed so that the bit group is the 43rd bit and the 42nd bit group is the 44th bit.

Meanwhile, as described later, since the puncturing units 217 and 318 puncture from the last parity bit, the parity bit groups can be arranged in the reverse order of the puncturing pattern by the parity permutation. That is, the first bit group to be punctured is located in the last bit group.

In the above example, only the parity bits are interleaved, but this is merely an example. That is, the parity permutation units 215 and 316 may interleave the LDPC information bits. In this case, the parity permutation units 215 and 316 may interleave the LDPC information bits with the identity and output the LDPC information word bits having the same order as before the interleaving so that the order of the LDPC information bits is not changed.

The repetition units 216 and 317 repetitively repeat at least some bits of the parity-permuted LDPC codeword to the positions following the LDPC codewords, and store the repaired LDPC codewords (i.e., And may be referred to as an LDPC code word after repetition) to the puncturing units 217 and 318. The puncturing units 217 and 318, On the other hand, the repetition unit 317 may output the LDPC code word after repetition to the additional parity generation unit 319. [ In this case, the additional parity generation unit 319 can generate additional parity bits using the LDPC codeword after the repetition.

Specifically, the repetition units 216 and 317 can repetitively a certain number of LDPC parity bits after the LDPC information bits. That is, the repetition units 216 and 317 may add a predetermined number of LDPC parity bits after LDPC information word bits. Accordingly, the repetition bits are located between the LDPC information bits and the LDPC parity bits in the LDPC codeword.

Accordingly, the above-described operation can be referred to as repetition in that a certain number of bits in the LDPC code word after repetition are repeated and can be further transmitted to the receiving apparatus 200. [ The bits added after the LDPC information bits according to the repetition bits in the LDPC codeword after the repetition are used as repetition bits (or repetition bits) Quot; repeated bits &quot;).

On the other hand, addition means adding repetition bits between LDPC information bits and LDPC parity bits so that the bits are repeated.

Repetition may be performed only for L1 basic mode 1 and L1 detail mode 1, but not for other modes. In this case, the repetition units 216 and 317 can output the parity-permuted LDPC codeword to the puncturing units 217 and 318 without performing repetition.

Hereinafter, a method of performing repetition will be described in more detail.

The repetition units 216 and 317 can calculate the number N _repeat of additional transmitted bits per LDPC codeword based on Equation (24) below.

Here, C has a fixed number, and D can be even integer. Referring to Equation 24, it can be seen that the number of repetition bits is calculated as C is multiplied and D is added for a given N _outer .

On the other hand, the parameters C and D for repetition can be selected in accordance with Table 12 below. That is, the repetition units 216 and 317 can determine C and D in accordance with the mode, based on Table 12.

The repetition units 216 and 317 can repetitively _repeat N LDPC parity bits.

Specifically, when the repetition units 216 and 317 are N _repeat? N _{ldpc_parity} , the first N _repeat bits of the parity- _permuted LDPC parity bits may be added to the LDPC information bits as shown in FIG. That is, the repetition units 216 and 317 may add N _repeat LDPC parity bits from the first LDPC parity bit among parity-permuted LDPC parity bits after LDPC information bits.

In the case of N _repeat > N _{ldpc_parity} , the repetition units 216 and 317 _add N _{ldpc_parity} LDPC parity bits, which are parity-permutated, to the LDPC information bits as shown in FIG. 13, and add parity- _permuted LDPC parity bits The first N _repeat N _{ldpc_parity} bits of the LDPC parity bits may be added to the N _{LDPC_parity} LDPC parity bits added first. That is, the repetition units 216 and 317 add the entire parity-permutated LDPC parity bits after the LDPC information bits, and _repeat the first LDPC parity bit among the parity-permuted LDPC parity bits N _repeat -N _{the ldpc_parity} LDPC parity bit may be additionally added after the LDPC parity bits added first.

Thus, for L1 basic mode 1 and L1 detail mode 1, additional N _repeat bits may be selected and transmitted within the LDPC codeword.

The puncturing units 217 and 318 puncture some bits in the LDPC parity bits included in the LDPC codeword output from the repetition units 216 and 317 and output punctured LDPC code words The LDPC codeword bits may be referred to as LDPC codewords after puncturing) to the zero eliminators 218 and 321, respectively. Meanwhile, the puncturing unit 318 may provide information on the LDPC parity bits to be punctured (e.g., the number and position of the punctured bits and the like) to the additional parity generating unit 319. [ In this case, the additional parity generation section 319 can generate additional parity bits based on this.

Thus, after parity permutation, some LDPC parity bits may be punctured.

In this case, the punctured LDPC parity bits are not transmitted in the frame transmitting the L1 signaling bits. Specifically, the punctured LDPC parity bits are not transmitted in the current frame that transmits the L1 signaling bits, and may be transmitted in the frame before the current frame, as the case may be, .

For this purpose, the puncturing units 217 and 318 can determine the number of LDPC parity bits punctured per LDPC code word and the size of one coded block.

Specifically, the puncturing units 217 and 318 can calculate the temporary number N _{punc_temp} of LDPC parity bits punctured based on Equation (25) below. That is, the puncturing units 217 and 318 can calculate a temporary number N _{punc_temp} of the LDPC parity bits to be punctured based on the following equation (25) for a given N _outer .

Referring to Equation 25, depending on the mode, the temporary size of the puncturing bits may be determined by multiplying an integer obtained by multiplying the shortening length (i.e., K _ldpc -N _outer ) by a predetermined constant A, constant integer). In the present invention, the value of the constant A is set as a ratio of the number of bits to be punctured to the number of bits to be shortened, but it is obvious that the value can be variously set according to the requirements of the system.

The B value is a value indicating the length of puncturing even if the shortening length is 0 and represents the minimum value of the puncturing bits. Also, the A and B values control the code rate to be actually transmitted. That is, the A and B values control the rate of the actual information bits to be lowered in comparison with the length of the information bits, that is, when the length of the L1 signaling is short or when the length of the L1 signaling is long.

On the other hand, K _ldpc , A and B are shown in Table 13 below. Table 13 shows parameters for puncturing. Accordingly, the puncturing units 217 and 318 can determine the parameters for puncturing according to the mode, based on Table 13.

On the other hand, the puncturing units 217 and 318 can calculate the temporary size N _{FEC_temp} of one coded block based on Equation (26) below. Table 13 shows the number of LDPC parity bits N _{ldpc_parity} according to the mode.

Then, the puncturing units 217 and 318 can calculate the size N _FEC of one coded block based on Equation (27) below.

Here, η _MOD is the modulation order. For example, if the L1 basic signaling and the L1 detail signaling are modulated to QPSK, 16-QAM, 64-QAM and 256-QAM depending on the mode, the eta _MOD can be 2, 4, . On the other hand, according to Equation (27), N _FEC can be an integral multiple of the modulation order.

The puncturing units 217 and 318 can calculate the number N _punc of the LDPC parity bits to be punctured based on Equation (28).

Here, N _punc is 0 or a positive integer. N _FEC is the number of bits excluding Npunc punctured bits among the N _outer + N _{ldpc_parity} bits obtained after each information word block, that is, K _sig information bits are encoded by BCH and LDPC. That is, the N _FEC is the number of the remaining bits transmitted actually, excluding the repetition bits, and the number of the LDPC codeword bits to which shortening and puncturing are applied.

The puncturing units 217 and 318 calculate the temporary number N _{punc_temp} of the punctured LDPC parity bits by multiplying the number of zero bits padded by the shortening length by A and adding B to the result do.

Then, the puncturing _units 217 and 318 calculate the temporary number N _{FEC_temp} of LDPC codeword bits after puncturing and shortening based on N _{punc_temp} .

Specifically, the LDPC information bits are LDPC encoded and the LDPC parity bits generated by the LDPC encoding are added to the LDPC information bits to construct an LDPC codeword. Here, the LDPC information bits include BCH encoded BCH encoded bits for L1 basic signaling and L1 detail signaling, and may further include padded zero bits, as the case may be.

In this case, the LDPC codeword (i.e., the LDPC codeword after shortening) excluding the shortened LDPC codeword, i.e., the padded zero bits, in the sense that the padded zero bits are not transmitted to the receiving apparatus 200 after the LDPC encoding BCH encoded bits and LDPC parity bits.

Accordingly, the puncturing units 217 and 318 subtract the temporary number of LDPC parity bits punctured to the sum of the number of BCH encoded bits and the number of LDPC parity bits, thereby calculating N _{FEC_temp} .

On the other hand, puncturing and shortened LDPC codewords (i.e., the remaining LDPC codeword bits, excluding punctured bits and shortened bits, may be referred to as LDPC codewords after puncturing and shortening) QPSK, 16-QAM, 64-QAM, and 256-QAM, and the constellation symbols can be transmitted to the receiving apparatus 200 through the frame.

Accordingly, the puncture ring portion (217, 318) are N Pow on the basis of the _{FEC_temp} that is an integral multiple of the modulation order puncturing and the number of shortening after the LDPC codeword bits determine the N _FEC and, N _FEC LDPC code after shortening, to be a The number N _punc of bits to be punctured in the word bits is determined.

On the other hand, when the zero bits are not padded, the LDPC codeword is composed of BCH encoded bits and LDPC parity bits, and shortening may be omitted.

Also, for L1 basic mode 1 and L1 detail mode 1, repetition is performed, and the number of LDPC codeword bits after shortening and puncturing is equal to N _FEC + N _repeat .

Meanwhile, the puncturing units 217 and 318 can puncture the calculated number of LDPC parity bits.

In this case, the puncturing units 217 and 318 can puncture the last N _punc bits of the entire LDPC code word. That is, the puncturing units 217 and 318 can puncture N _punc bits from the last LDPC parity bit.

Specifically, if repetition is not performed, the parity-permutated LDPC codeword will contain only the LDPC parity bits generated by the encoding.

In this case, the puncturing units 217 and 318 can puncture the last N _punc bits of the parity-permutated whole LDPC code word. Accordingly, N _punc bits from the last LDPC parity bit among the LDPC parity bits generated by encoding can be punctured.

On the other hand, when repetition is performed, the LDPC codeword after the parity permutation and repetition includes the repaired LDPC parity bits and the LDPC parity bits generated by the encoding.

In this case, the puncturing units 217 and 318 can puncture the last N _punc bits of the entire LDPC codeword in which parity permutation and repetition are performed, as shown in FIGS. 14 and 15. FIG.

Specifically, since the repaired LDPC parity bits are located between the LDPC information bits and the LDPC parity bits generated by the encoding, the puncturing units 217 and 318 detect the end of the LDPC parity bits generated by the encoding It is possible to puncture N _punc bits from the LDPC parity bit.

In this manner, the puncturing units 217 and 318 can puncture N _punc bits from the last LDPC parity bits.

On the other hand, N _punc is 0 or a positive integer, and the repetition can be applied only to the L1 basic mode 1 and the L1 detail mode 1.

In the above example, puncturing is performed after repetition is performed, but this is merely an example. In some cases, repetition may be performed after puncturing is performed.

The additional parity generation unit 319 generates additional parity (AP) bits by selecting bits in the LDPC parity bits.

In this case, the additional parity bits may be selected from the LDPC parity bits generated based on the L1 detail signaling transmitted in the current frame, and transmitted to the receiving apparatus 200 through the previous frame, i.e., the previous frame.

Specifically, the L1 detail signaling is LDPC encoded and the LDPC parity bits generated by the LDPC encoding are added to the L1 detail signaling to construct the LDPC codeword.

Then, puncturing and shortening are performed on the LDPC codeword, and LDPC codewords after puncturing and shortening are mapped to the frame and transmitted to the receiving apparatus 200. Here, if repetition is performed according to the mode, the LDPC codewords after puncturing and shortening may include repeated LDPC parity bits.

In this case, the L1 detail signaling corresponding to each frame may be transmitted to the reception apparatus 200 through each frame together with the LDPC parity bits. For example, the puncturing and shortening LDPC codewords including L1 detail signaling corresponding to the (i-1) th frame are mapped to the (i-1) th frame and transmitted to the receiving apparatus 200, The puncturing and shortening LDPC codewords including the L1 detail signaling may be mapped to the i &lt; th &gt; frame and transmitted to the receiving device 200. [

Meanwhile, the additional parity generation unit 319 may generate additional parity bits by selecting at least some bits in the LDPC parity bits generated based on the L1 detail signaling transmitted in the i-th frame.

Specifically, in the LDPC parity bits generated by the L1 detail signaling being LDPC-encoded, some bits are punctured and not transmitted to the receiving apparatus 200. [ In this case, the additional parity generation unit 319 generates at least some bits in the LDPC parity bits to be punctured among LDPC parity bits generated by LDPC-encoding the L1 detail signaling transmitted in the i &lt; th &gt; can do.

The additional parity generation unit 319 may generate additional parity bits by selecting at least some bits from the LDPC parity bits transmitted to the reception apparatus 200 through the i-th frame.

Specifically, the LDPC parity bits included in the LDPC codeword after the puncturing and shortening mapped to the i-th frame are configured only by the LDPC parity bits generated by encoding according to the mode, or by the LDPC parity bits generated by the encoding and And may be composed of repeated LDPC parity bits.

In this case, the additional parity generation unit 319 may generate additional parity bits by selecting at least some bits in the LDPC parity bits included in the LDPC codeword after the puncturing and shortening mapped to the i &lt; th &gt; frame.

On the other hand, the additional parity bits may be transmitted to the receiving apparatus 200 through the frame before the i-th frame, i.e., the (i-1) th frame.

That is, the transmitting apparatus 100 transmits not only LDPC code words after puncturing and shortening that include L1 detail signaling corresponding to the (i-1) th frame, but also additional parity information generated based on L1 detail signaling transmitted in the i- Bits to the receiving apparatus 200 through the (i-1) th frame.

In this case, the frame to which the additional parity bits are transmitted may be the closest temporally previous frame among the frames before the current frame.

For example, the additional parity bits may have the same bootstrap major / minor version as the current frame of the frames before the current frame, and may be transmitted in the closest previous frame in time.

In some cases, the additional parity generation unit 319 may not generate additional parity bits.

In this case, the transmitting apparatus 100 transmits information on whether additional parity bits for the L1-detail signaling of the next frame are transmitted through the current frame to the receiving apparatus 200 using L1 basic signaling transmitted through the current frame .

For example, the use of additional parity bits for the L1 detail signaling of the next frame with the same bootstrap major / minor version as the current frame can be serialized through the field L1B_L1_Detail_additional_parity_mode of the L1 basic parameter of the current frame. Specifically, when L1B_L1_Detail_additional_parity_mode is set to '00' in the L1 basic parameter of the current frame, the additional parity bits for the L1 detail signaling of the next frame are not transmitted in the current frame.

Thus, in order to increase the additional robustness of the L1 detail signaling, the additional parity bits may be transmitted in the frame before the current frame transmitting the L1 detail signaling of the current frame.

16 shows an example in which additional parity bits for L1 detail signaling of an i-th frame are transmitted in a preamble of an (i-1) th frame.

16, the L1 detail signaling transmitted through the i-th frame is segmented into M blocks by segmentation, and each segmented block is FEC-encoded.

Thus, an LDPC codeword comprising M LDPC codewords, i.e. LDPC information bits L1-D (i) _1 and parity bits for it (parity for L1-D (i) _1), ... , LDPC codewords including LDPC information bits L1-D (i) _M and parity bits for them (L1-D (i) _M) are mapped to the i-th frame and transmitted to the receiving apparatus 200 do.

In this case, the additional parity bits generated based on the L1 detail signaling transmitted in the i-th frame may be transmitted to the receiving apparatus 200 through the (i-1) th frame.

.., AP for L1-D (i) _M are generated in the (i-1) -th frame, based on the L1 detail signaling transmitted in the i- Mapped to the preamble of the frame and can be transmitted to the receiving apparatus 200. As a result of using such additional parity bits, a diversity gain for L1 signaling can be obtained.

Hereinafter, a method of generating additional parity bits will be described.

The additional parity generation unit 319 calculates a temporary number N _{AP_temp} of the additional parity bits based on Equation (29) below.

이다.From here,

to be.

And K is the total number of bits of the coded L1 detail signaling block to be transmitted (i. E., Bits constituting the L1 detail signaling block after repetition, puncturing and zero bits have been removed Represents the ratio of the number of additional parity bits to half the number.

In this case, K corresponds to the field L1B_L1_Detail_additional_parity_mode field of L1 basic signaling. Here, the value of L1B_L1_Detail_additional_parity_mode associated with the L1 detail signaling of the i-th frame (i.e., frame (#i)) may be transmitted in the (i-1) th frame (i.e., frame (#i-1)).

On the other hand, as described above, in the case of the L1 detail modes 2, 3, 4, 5, 6 and 7, N _repeat in the equation (29) is 0 in that repetition is not performed.

The additional parity generation unit 319 calculates the number N _AP of additional parity bits based on Equation (30). Accordingly, the number N _AP of additional parity bits can be an integer multiple of the modulation order.

는 x 보다 작거나 같은 최대 정수이다. 그리고, η_MOD는 변조 차수이다. 일 예로, 모드에 따라 L1 디테일 시그널링이 QPSK, 16-QAM, 64-QAM 및 256-QAM으로 변조되는 경우, η_MOD는 2,4,6,8이 될 수 있다. From here,

Is the largest integer less than or equal to x. And, η _MOD is the modulation order. For example, if the L1 detail signaling is modulated to QPSK, 16-QAM, 64-QAM, and 256-QAM depending on the mode, the eta _MOD can be 2, 4,

As such, the number of additional parity bits may be determined based on the total number of bits transmitted in the current frame.

Then, the additional parity generation unit 319 may generate additional parity bits by selecting as many as the number of bits calculated from the LDPC parity bits.

Specifically, when the number of punctured LDPC parity bits is equal to or greater than the number of additional parity bits, the additional parity generating unit 319 adds the number of bits calculated from the first LDPC parity bit among the punctured LDPC parity bits To generate additional parity bits.

If the number of punctured LDPC parity bits is smaller than the number of additional parity bits, the supplementary parity generation unit 319 first selects all the punctured LDPC parity bits, and selects one of the LDPC parity bits included in the LDPC codeword Additional parity bits can be generated by additionally selecting as many bits as the number obtained by subtracting the number of punctured LDPC parity bits from the number of bits calculated from the first LDPC parity bit.

Specifically, when repetition is not performed, the LDPC parity bits included in the LDPC codeword after repetition are LDPC parity bits generated by encoding.

In this case, the additional parity generation unit 319 first selects all of the punctured LDPC parity bits, and adds the punctured LDPC parity bits from the number of bits calculated from the first LDPC parity bits among the LDPC parity bits generated by the encoding The additional parity bits can be generated by additionally selecting as many bits as the number obtained by subtracting the number of bits.

Here, the LDPC parity bits generated by the encoding are divided into non-punctured LDPC parity bits and punctured LDPC parity bits. Accordingly, when bits are selected from the first bit among the LDPC parity bits generated by encoding, they can be selected in the order of non-punctured LDPC parity bits and punctured LDPC parity bits.

On the other hand, if repetition is performed, the LDPC parity bits included in the LDPC codeword after the repetition are the repeated LDPC parity bits and the LDPC parity bits generated by the encoding. Here, the repaired LDPC parity bits are located between the LDPC information bits and the LDPC parity bits generated by the encoding.

In this case, the additional parity generation unit 319 first selects all the punctured LDPC parity bits, and calculates the number of punctured LDPC parity bits from the number of bits calculated from the first LDPC parity bit among the repeated LDPC parity bits The additional parity bits may be generated by additionally selecting as many bits as the number of bits.

Here, when bits are selected from the first bit of the repeated LDPC parity bits, they can be selected in order of repetition bits and LDPC parity bits generated by encoding. Also, within the LDPC parity bits generated by encoding, bits can be selected in the order of non-punctured LDPC parity bits and punctured LDPC parity bits.

Hereinafter, a method of generating additional parity bits according to an embodiment of the present invention will be described in more detail with reference to FIG. 17 through FIG.

)는 도 17과 같이 나타낼 수 있다.17 to 19 are diagrams for explaining a method of generating additional parity bits when repetition is performed according to an embodiment of the present invention. In this case, the LDPC code word V = (v ₀ , v ₁ , ...,

) Can be represented as shown in Fig.

First, when N _AP? N _punc , the additional parity generation unit 319 selects N _AP bits from the first LDPC parity bit among the punctured LDPC parity bits to generate additional parity bits, as shown in FIG. 18 .

,

,...,

)이 선택될 수 있다. 즉, 부가 패리티 생성부(319)는펑처링된 LDPC 패리티 비트들 중 첫 번째 LDPC 패리티 비트부터 N_AP 개의 비트들을 선택하여 부가 패리티 비트들을 생성할 수 있다. Thus, for the additional parity bits, the punctured LDPC parity bits (

,

, ...,

) Can be selected. That is, the additional parity generation unit 319 can generate additional parity bits by selecting N _AP bits from the first LDPC parity bit among the punctured LDPC parity bits.

On the other hand if, N _AP> N _punc, as shown in Figure 19, an additional parity generating unit 319 selects all the punctured LDPC parity bit.

,

,...,

)이 선택될 수 있다.Thus, for the additional parity bits, all punctured LDPC parity bits (

,

, ...,

) Can be selected.

The additional parity generation unit 319 can additionally select the first (N _AP -N _punc ) bits in the LDPC parity bits including the _repeated LDPC parity bits and the LDPC parity bits generated by the encoding .

That is, since the repeated LDPC parity bits and the LDPC parity bits generated by the encoding are sequentially arranged, the additional parity generating unit 319 adds the first LDPC parity bits among the LDPC parity bits added by the retransmission, Parity bits from the parity bit (N _AP - _punc ) can be additionally selected.

,

,...,

)이 추가적으로 선택될 수 있다.Thus, for additional parity bits, LDPC parity bits (

,

, ...,

) Can be additionally selected.

In this case, the additional parity generation unit 319 may additionally add selected bits to previously selected bits to generate additional parity bits. That is, as shown in FIG. 19, the additional parity generation unit 319 may additionally add selected LDPC parity bits to the punctured LDPC parity bits to generate additional parity bits.

,

,...,

,

,

,...,

)가 선택될 수 있다.As a result, for the additional parity bits, (

,

, ...,

,

,

, ...,

) May be selected.

As such, if the number of punctured bits is greater than or equal to the number of additional parity bits, the additional parity bits may be generated by selecting bits from the punctured bits based on the puncturing order. Otherwise, the additional parity bits may be generated by selecting all of the punctured bits and (N _AP -N _punc ) parity bits.

On the other hand, in the case where repetition is not performed, the method of generating additional parity bits in the case where N _repeat = 0 is not performed is the same as the case of N _repeat = 0 in FIGS. 17 to 19 .

On the other hand, the additional parity bits are bit interleaved and can be mapped to constellation. In this case, the constellation for the additional parity bits may be generated in the same manner as the constellation for L1 detail signaling bits after the repetition, puncturing and zero bits transmitted in the current frame are removed. And, after being mapped to the constellation, as shown in Fig. 16, the additional parity bits can be added to the L1 detail signaling block later in the frame before the current frame transmitting the L1 detail signaling of the current frame.

Meanwhile, the additional parity generation unit 319 may output the additional parity bits to the bit demux 323.

On the other hand, the group-wise interleaving pattern defining the permutation order may be composed of the first pattern and the second pattern.

개의 비트 그룹은 항상 펑처링된다.Specifically, the B value of Equation (25) represents the minimum value of the LDPC parity bits to be punctured. Depending on the value of B, a certain number of bits can always be punctured irrespective of the length of the input signaling. For example, in the L1 detail mode 2, B = 6036, and the bit group is composed of 360 bits, even if the shortening length is 0,

Bit group is always punctured.

In this case, since the puncturing is performed from the last LDPC parity bit, after the group-wise interleaving, a certain number of bit groups from the last bit group among the plurality of bit groups constituting the LDPC parity bits are always set to be the same regardless of the shortening length, .

For example, in the L1 detail mode 2, after group-wise interleaving, the last 16 bit groups out of the 36 bit groups constituting the LDPC parity bits can always be punctured.

Accordingly, in the group-wise interleaving pattern defining the permutation order, some patterns always represent bit groups that are punctured, so that the group-wise interleaving pattern can be divided into two patterns. Specifically, a pattern that defines the remaining bit groups excluding the bit group that is always punctured in the group-interleaving pattern is referred to as a first pattern, and a pattern that defines a bit group that is always punctured may be referred to as a second pattern.

For example, in the L1 detail mode 2, the group-wise interleaving pattern is defined as shown in Table 10, so that the index of the group before the group-wise interleaving which is located in the ninth bit group to the 28th bit group after the group- It represents a pattern that _{is, Y 9 = X πp (9} ) = X 9, Y 10 = X πp (10) = X 31, Y 11 = X πp (11) = X 23, ..., Y 26 = Xπ p ₍₂₆₎ = X ₁₇ , Y ₂₇ = X p ₍₂₇₎ = X ₃₅ , Y ₂₈ = X p ₍₂₈₎ = X ₂₁ becomes the first pattern, is located at the group, the group-pattern, which is the index of the bit group before wise interleaving that _{is, Y 29 = X πp (29} ) = X 20, Y 30 = X πp (30) = X 24, Y 31 = X πp (31 _{) = X 44, ..., Y} 42 = X πp (42) = X 28, Y 43 = X πp (43) = X 39, Y 44 = X πp (44) = X 42 may be the second pattern .

Meanwhile, as described above, the second pattern defines a bit group that is always punctured regardless of the shortening length in the current frame, and the first pattern defines a bit group that is additionally punctured as the shortening length becomes longer, , The first pattern may be used to determine the LDPC parity bits transmitted in the current frame after puncturing.

Specifically, depending on the number of LDPC parity bits being punctured, more LDPC parity bits may be punctured in addition to the always punctured LDPC parity bits.

For example, in the L1 detail mode 2, if the number of LDPC parity bits to be punctured is 7200, 20 bit groups must be punctured, so that there are always 16 punctured bit groups plus 4 bit groups It must be punctured.

In this case, the four further punctured bit groups correspond to the 25th to 28th bit groups after the group-wise interleaving, and these bit groups are determined according to the first pattern, that is, , The first pattern can be used to determine the group of bits to be punctured.

That is, when LDPC parity bits are punctured beyond the minimum value of the LDPC parity bits to be punctured, what bit group is additionally punctured is always determined by which bit group is located after the punctured bit group. Accordingly, it can be seen that, based on the direction of puncturing, a first pattern defining a bit group positioned after the bit group always punctured is determined to determine the bit group to be punctured.

That is, in the above example, when the number of LDPC parity bits to be punctured is 7200, 16 bits groups that are always punctured, and four groups of bits, that is, 28th, 27th, And the 25th bit group are further punctured. Here, the bit group located from the 25th to the 28th position after the group-Wise interleaving is determined according to the first pattern.

Consequently, it can be seen that the first pattern is used to determine the bit group to be punctured. In addition, since the remaining LDPC parity bits except the punctured LDPC parity bits are transmitted through the current frame, the first pattern is used to determine a bit group transmitted in the current frame.

On the other hand, the second pattern can be used only to determine the additional parity bits transmitted in the previous frame.

Specifically, since a bit group determined to be always punctured is always punctured and not transmitted in the current frame, it is only required to be group-wise interleaved to the position of the bit group always punctured, It does not matter where you are located in.

For example, in the L1 detail mode 2, the bit groups located at the 20th, 24th, 44th, ..., 28th, 39th and 42nd positions before group-wise interleaving are the 29th It only needs to be located in the bit group to the 44th bit group, and it does not matter where it is located in the corresponding bit groups.

Thus, in terms of puncturing, the second pattern, which always defines the groups of bits to be punctured, is only used to identify the group of bits to be punctured. As a result, the definition of the order between bit groups in the second pattern is meaningless in terms of puncturing, and consequently, it can be seen that the second pattern defining the bit group always punctured is not used for puncturing.

However, in terms of additional parity bits, it is important where the bit groups always determined to be punctured are located within the bit groups that are always punctured.

Specifically, the additional parity bits are always generated by selecting a predetermined number of bits from the first bit of the LDPC parity bits to be punctured. Therefore, the additional parity bits are always generated according to the number of LDPC parity bits and the number of additional parity bits to be punctured. Bits included in at least some bit groups among the bit groups to be processed can be selected as additional parity bits.

That is, in the case where the additional parity bits are selected in excess of the bit group defined according to the first pattern, the order of the bit groups belonging to the second pattern is the order This is important in terms of parity selection. Accordingly, it can be seen that the second pattern that defines the bit group that is always punctured is used to determine the additional parity bits.

For example, in L1 detail mode 2, the total number of LDPC parity bits is 12960, and the number of bit groups always punctured is 16.

In this case, the second pattern may be used for additional parity generation depending on whether the sum of the number of LDPC parity bits that are punctured in all the LDPC parity bits and the sum of the number of additional parity bits exceeds 7200. Here, 7200 is the number of LDPC parity bits included in the remaining bit groups excluding the bit groups always punctured among the bit groups constituting the LDPC parity bits. That is, 7200 = (36-16) x 360.

Specifically, if the total number of LDPC parity bits minus the number of LDPC parity bits to be punctured in all the LDPC parity bits and the sum of the number of additional parity bits is 7200 or less, that is, 12960-N _punc + N _AP? 7200, May be generated based on the first pattern.

However, if the value subtracts the number of LDPC parity bit popping in full LDPC parity bit puncturing plus the number of additional parity bits exceeds 7200, i.e., 12960-N _punc + N _AP> If the 7200, the additional parity bits May be generated based on the first pattern and the second pattern.

Specifically, in the case of 12960-N _punc + N _AP &gt; 7200, LDPC parity bits included in the bit group located at the 28th from the first LDPC parity bit among the punctured LDPC parity bits for the additional parity bits are selected And the bits included in the bit group located at a specific position from the 29th bit can be selected.

Here, the bit group to which the first LDPC parity bit belongs and the bit group of the specific position among the punctured LDPC parity bits (that is, the last one when sequentially selected from the first LDPC parity bit among the punctured LDPC parity bits) The bit group to which the selected LDPC parity bits belong) can be determined according to the number of LDPC parity bits and the number of additional parity bits to be punctured.

In this case, the bit group located at the 28th position from the first LDPC parity bit among the punctured LDPC parity bits is determined according to the first pattern, and the bit group located at the specific position from the 29th position is determined according to the second pattern do.

Accordingly, the additional parity bits are determined according to the first pattern and the second pattern.

As such, the first pattern is used to determine additional parity bits as well as LDPC parity bits to be punctured, but the second pattern can only be used to determine additional parity bits.

In the above example, the group-wise interleaving pattern includes the first pattern and the second pattern. However, this is merely for convenience of description in terms of puncturing and additional parity. That is, the group-wise interleaving pattern may be regarded as one pattern without discrimination between the first pattern and the second pattern. In this case, group-wise interleaving is performed in one pattern for both puncturing and additional parity. .

On the other hand, in the above-described example, the exemplified values as the number of LDPC parity bits to be punctured are merely illustrative examples.

The zero elimination units 218 and 321 remove the zero bits padded by the zero padding units 213 and 314 in the LDPC code word output from the puncturing units 217 and 318 and output the remaining bits to the bit demuxs 219 and & 322, respectively.

Here, the elimination may include not only removing padded zero bits, but also removing the padded zero bits, but outputting the remaining bits except for padded zero bits in the LDPC codeword.

Specifically, the zero eliminators 218 and 321 can remove the _nulls of K _ldpc -N _outer padded by the zero padding units 213 and 314. Accordingly, the zero padding bits of K _ldpc -N _outer are removed and may not be transmitted to the receiving apparatus 200.

For example, as shown in FIG. 20, all the bits of the first bit group, the fourth bit group, the fifth bit group, the seventh bit group, and the eighth bit group of the plurality of bit groups constituting the LDPC code word are zero bits , And some bits of the second bit group are padded with zero bits.

In this case, the zero elimination units 218 and 321 can remove the zero bits padded to the first bit group, the second bit group, the fourth bit group, the fifth bit group, the seventh bit group and the eighth bit group have.

When the zero bits are removed, K _sig information word bits (i.e., K _sig L1 basic signaling bits and K _sig L1 detail signaling bits), 168 BCH parity check bits (i.e., , it may be left in the BCH FEC) and (N -K _{inner ldpc} -N _punc) or (N -K _{inner ldpc} -N _{punc pereat} + N) of the parity-bit word (word) composed of.

That is, when repetition is performed, the length of the entire LDPC code word is (N _FEC + N _repeat ). Here, N _FEC = N _outer + N _{ldpc_parity} -N _punc . However, in the case where the repetition is not performed, the length of the entire LDPC codeword is N _FEC .

The bit demuxs 219 and 322 can interleave the bits output from the zero elimination units 218 and 321 and demultiplex the interleaved bits and output the demultiplexed bits to the constellation mapper 221 and 324.

To this end, the bit demuxs 219 and 322 may include a block interleaver (not shown) and a demultiplexer (not shown).

First, a block interleaving scheme performed in a block interleaver (not shown) is as shown in FIG.

Specifically, the N _FEC or N _FEC + N _repeat length bits after the zero bits are removed can be serially written to the block interleaver (not shown) in a column-wise manner. Here, the number of columns of the block interleaver (not shown) is equal to the modulation order, and the number of rows is N _FEC /? _MOD or (N _FEC + N _repeat ) /? _MOD .

In the read operation, bits for one constellation symbol may be sequentially read out in a row and input to a demultiplexer (not shown). This action can continue to the last row of the column.

That is, N _FEC or (N _FEC + N _repeat ) bits are written to a plurality of columns in the column direction from the first row of the first column, and the bits written to the plurality of columns are shifted from the first row to the And can be sequentially led to the row in the row direction. At this time, the bits read in the same row can constitute one modulation symbol.

Meanwhile, the demultiplexer (not shown) may demultiplex the bits output from the block interleaver (not shown).

Specifically, the demultiplexer (not shown) converts the bits that are read out in the same row of the block interleaved block, that is, the block interleaver (not shown), into a bit-by- by-bit. &lt; / RTI &gt;

In this case, there are two mapping rules depending on the modulation order.

Specifically, in the case of QPSK, the demultiplexer (not shown) does not perform a demultiplexing operation on the bit group, in that the reliability of the bits in the constellation symbol is the same. Accordingly, the bit groups read out from the block interleaver (not shown) can be mapped to QPSK symbols without a demultiplexing operation.

However, in the case of high order modulation, the demultiplexer (not shown) may perform demultiplexing on the bit groups read out from the block interleaver (not shown) based on Equation 31 below. That is, the bit group may be mapped to a QAM symbol according to Equation 31 below.

Where% is a modulo operation and η _MOD is a modulation order.

And i is a bit group index corresponding to the row index of the block interleaver (not shown). That is, the output bit group S _{demux_out} (i) mapped to each of the QAM symbols may be _cyclically shifted in S _{demux_in} (i) according to the bit group index i.

Meanwhile, FIG. 22 shows an example of bit demultiplexing for 16-NUC (non-uniform constellation), that is, NUC 16-QAM. This operation can be continued until all the bit groups are read in the block interleaver (not shown).

Meanwhile, the bit demux 323 performs the same operation as that performed by the bit demuxs 219 and 322 on the additional parity bits output from the add parity generation unit 319, and performs block interleaving and demultiplexing And outputs the generated bits to the constellation mapper 325.

The constellation mapers 221, 324, and 325 can map the bits output from the bit demuxs 219, 322, and 323 to constellation symbols.

That is, the constellation mapper 221, 324, and 325 may _map S _{demux_out} (i) to a cell word using the constellation according to the mode. Here, S _{demux_out} (i) may be composed of the same number of bits as the modulation order.

Specifically, the constellation mapper 221, 324, and 325 convert the bits output from the bit demuxs 219, 322, and 323 into a modulation scheme such as QPSK, 16-QAM, 64-QAM, and 256- Can be used to map to constellation symbols.

In this case, the constellation mapers 221, 324, and 325 can use NUC. That is, the constellation mapers 221, 324, and 325 can use NUC 16-QAM, NUC 64-QAM, and NUC 256-QAM. Table 5 shows modulation schemes applied to L1 basic signaling and L1 detail signaling according to the mode.

Meanwhile, the transmitting apparatus 100 may map the constellation symbols to a frame and transmit the mapped constellation symbols to the receiving apparatus 200.

Specifically, the transmitting apparatus 100 transmits the constellation symbols corresponding to the L1 basic signaling and the L1 detail signaling output from the constellation mapers 221 and 324 and the constellation symbols corresponding to the additional parity bits output from the constellation mapper 325 The corresponding constellation symbols can be mapped to the preamble symbols of the frame.

In this case, the transmitting apparatus 100 may map the additional parity bits generated based on the L1 detail signaling transmitted in the current frame to a frame preceding the corresponding frame.

That is, the transmitting apparatus 100 maps the LDPC codeword bits including the L1 basic signaling corresponding to the (i-1) th frame to the (i-1) th frame, and includes the L1 detail signaling corresponding to the Mapping the LDPC codeword bits to the (i-1) -th frame, adding the additional parity bits selected and generated from the LDPC parity bits generated based on the L1-detail signaling corresponding to the i-th frame, To the receiving apparatus 200. [

In addition, the transmitting apparatus 100 may map data to a data symbol of a frame in addition to L1 signaling, and may transmit a frame including L1 signaling and data to the receiving apparatus 200. [

In this case, the signaling for the data mapped to each data may be mapped to the preamble of the frame in that the L1 signaling includes signaling information for the data. For example, the transmitting apparatus 100 may map the L1 signaling including the signaling information on the data mapped to the i-th frame to the i-th frame.

Accordingly, the receiving apparatus 200 can acquire and process data from the frame using the signaling obtained from the frame.

23 and 24 are block diagrams illustrating a configuration of a receiving apparatus according to an embodiment of the present invention.

23, the receiving apparatus 200 includes a constellation demapper 2210, a multiplexer 2220, an LLR inserter 2230, an LLR combiner 2240, and an LLR combiner 2230 to process L1 basic signaling. A parity defer mutation unit 2250, an LDPC decoder 2260, a zero elimination unit 2270, a BCH decoder 2280, and a descrambler 2290.

24, the reception apparatus 200 includes constellation demappers 2311 and 2312, muxes 2321 and 2322, an LLR inserter 2330, and an LLR combiner (not shown) to process L1 detail signaling A parity demultiplexer 2340, an LDPC decoder 2360, a zero elimination block 2370, a BCH decoder 2380, a descrambler 2390, and a demagnetization block 2395.

Here, the components shown in Figs. 23 and 24 are components that perform the functions corresponding to the components shown in Figs. 7 and 8, which are merely examples, and in some cases, some of them may be omitted or changed And other components may be added.

The receiving apparatus 200 can use the bootstrap of the frame to acquire the synchronization of the frame and receive the L1 basic signaling from the preamble of the frame using the information for processing the L1 basic signaling included in the bootstrap.

The receiving apparatus 200 receives the L1 detail signaling from the preamble using the information for processing the L1 detail signaling included in the L1 basic signaling and outputs the L1 detail signaling to the receiver 200 using the L1 detail signaling It is possible to receive broadcast data.

Accordingly, the reception apparatus 200 determines a mode in which the L1 basic signaling and the L1 detail signaling are processed in the transmission apparatus 100, processes the signal received from the transmission apparatus 100 according to the determined mode, and outputs L1 basic signaling And L1 detail signaling. To this end, the receiving apparatus 200 may store information on parameters used by the transmitting apparatus 100 to process the signaling according to the mode.

In this manner, the L1 basic signaling and the L1 detail signaling are sequentially acquired from the preamble. In the description of FIG. 23 and FIG. 24, components for performing common functions will be described together for convenience of explanation.

The constellation demapper 2210, 2311, and 2312 demodulate the signal received from the transmission apparatus 100.

Specifically, the constellation demapper 2210, 2311, 2312 is a component corresponding to the constellation mapper 221, 324, 325 of the transmission apparatus 100, demodulates the signal received from the transmission apparatus 100 , And generate values corresponding to the bits transmitted from the transmission apparatus 100. [

That is, as described above, the transmitting apparatus 100 maps an LDPC codeword including L1 basic signaling and an LDPC codeword including L1 detail signaling to a preamble of a frame, and transmits the LDPC codeword to the receiving apparatus 200. [ Alternatively, the transmitting apparatus 100 may map the additional parity bits to the preamble of the frame and transmit the mapped additional parity bits to the receiving apparatus 200, as the case may be.

Accordingly, constellation demapper 2210, 2311 can generate LDPC code word bits including L1 basic signaling and values corresponding to LDPC code word bits including L1 detail signaling. The constellation demapper 2312 can then generate values corresponding to the additional parity bits.

To this end, the receiving apparatus 200 may store information on a modulation scheme in which L1 basic signaling, L1 detail signaling, and additional parity bits are modulated in the transmitting apparatus 100 according to a mode. Accordingly, the constellation demapper 2210, 2311, and 2312 can demodulate the signal received from the transmitting apparatus 100 according to the mode to generate values corresponding to LDPC code word bits and additional parity bits .

On the other hand, the value corresponding to the bits transmitted from the transmitting apparatus 100 is a value calculated on the basis of the probability that the received bit is 0 and the probability of 1, and uses each probability itself as a value corresponding to each bit Alternatively, the value may be a Likelihood Ratio (LR) value or a log likelihood ratio (LLR) value.

Specifically, the LR value is a ratio of a probability that a bit transmitted from the transmitting apparatus 100 is 0 and a probability of a day, and an LLR value indicates a probability that a bit transmitted from the transmitting apparatus 100 is 0, The ratio can be expressed as a value obtained by taking Log.

In the above example, the LR value or the LLR value is used. However, this is an example, and the received signal itself may be used.

The muxes 2220, 2321, and 2322 perform multiplexing on the LLR values output from the constellation demapper 2210, 2311, and 2312.

Specifically, the muxes 2220, 2321, and 2322 are elements corresponding to the bit demuxes 219, 322, and 323 of the transmission apparatus 100 and correspond to the bit demuxes 219, 322, and 323 Can be performed.

To this end, the receiving apparatus 200 may be storing information on parameters that the transmitting apparatus 100 has used for demultiplexing and block interleaving. Accordingly, the muxes 2220, 2321, and 2322 inversely perform the demultiplexing and block interleaving operations performed on the bit demuxs 219, 322, and 323 with respect to the LLR values corresponding to the cell word, Lt; RTI ID = 0.0 &gt; LLR &lt; / RTI &gt;

LLR inserters 2230 and 2330 may insert LLR values for puncturing and shortening bits into the LLR values output from muxes 2220 and 2321. [ In this case, the LLR inserters 2230 and 2330 may insert predetermined LLR values between or before or after the LLR values output from the muxes 2220 and 2321.

Specifically, the LLR inserters 2230 and 2330 are elements corresponding to the zero elimination units 218 and 321 and the puncturing units 217 and 318 of the transmission apparatus 100, respectively. The zero elimination units 218 and 321, The operation corresponding to the puncturing units 217 and 318 can be performed.

First, the LLR inserters 2230 and 2330 may insert an LLR value corresponding to zero bits at a position where zero bits have been padded in the LDPC codeword. In this case, the LLR value corresponding to the padded zero bits, that is, the shortened zero bits, may be ∞ or -∞. However, ∞ or -∞ is the theoretical value, which may be substantially the maximum or minimum value of the LLR value used in the receiving apparatus 200.

To this end, the receiving apparatus 200 may store information on parameters and / or patterns that the transmitting apparatus 100 has used to pad the zero bits according to the mode. Accordingly, the LLR inserters 2230 and 2330 can determine the position where the zero bits are padded in the LDPC code word according to the mode, and insert the LLR value corresponding to the shortened zero bits at the corresponding position.

In addition, the LLR inserters 2230 and 2330 may insert an LLR value corresponding to the punctured bits at the location of the punctured bits in the LDPC codeword. In this case, the LLR value corresponding to the punctured bits may be zero.

To this end, the receiving apparatus 200 may store information on parameters and / or patterns used for puncturing in the transmitting apparatus 100 according to a mode. Accordingly, the LLR inserters 2230 and 2330 can determine the length of the punctured LDPC parity bits according to the mode, and insert the corresponding LLR value at the punctured position of the LDPC parity bits.

Meanwhile, in the case of the additional parity bits selected in the puncturing bits among the additional parity bits, the LLR inserter 2330 receives the LLR value &quot; 0 &quot; for the punctured bit, Lt; RTI ID = 0.0 &gt; punctured &lt; / RTI &gt;

The LLR combiners 2240 and 2340 may combine or sum the LLR values output from the LLR inserters 2230 and 2330 and the mux 2322. However, the LLR combiners 2540 and 2640 update the LLR values for specific bits, but it is possible to decode the received LLR values without the LLR combiners 2540 and 2640 In some cases, it is possible to omit it.

The LLR combiner 2240 is a component corresponding to the repetition unit 216 of the transmission apparatus 100 and may perform an operation corresponding to the repetition unit 216. [ The LLR combiner 2340 is a component corresponding to the repetition unit 317 and the additional parity generation unit 319 of the transmission apparatus 100 and includes a repetition unit 317 and an additional parity generation unit 319 ) Can be performed.

First, the LLR combiner 2240, 2340 may combine the LLR value corresponding to the repeated bits with another LLR value. Here, another LLR value may be an LLR value for the bits based on generation of repeated bits in the transmitting apparatus 100, that is, the LDPC parity bits selected for repetition.

That is, as described above, the transmitting apparatus 100 selects the bits from the LDPC parity bits, and repeats them between the LDPC information bits and the LDPC parity bits to transmit to the receiving apparatus 200.

Accordingly, the LLR value for the LDPC parity bits is the LLR value for the repaired LDPC parity bits and the LLR value for the unreputed LDPC parity bits, i.e., the LDPC parity bits generated by the encoding Lt; / RTI &gt; Thus, the LLR combiners 2240 and 2340 may combine the LLR values with the same LDPC parity bits.

To this end, the receiving apparatus 200 may store information on parameters used for repetition in the transmitting apparatus 100 according to the mode. Accordingly, the LLR combiners 2240 and 2340 determine the length of the repeated LDPC parity bits, determine the positions of the bits based on the repetition, The LLR value may be combined with the LLR value for the LDPC parity bits on which the repetition is based.

For example, as shown in FIGS. 25 and 26, the LLR combiners 2240 and 2340 may calculate the LLR value for the repaired LDPC parity bits from the LLR value for the LDPC parity bits based on the repetition . &Lt; / RTI &gt;

Meanwhile, the LLR combiners 2240 and 2340 can combine the LLR values for the bits in the same position n times or less when the LDPC parity bits are n-numbered.

For example, FIG. 25 shows a case where a part of the LDPC parity bits except for the punctured bits is repetition-1. In this case, the LLR combiners 2240 and 2340 may combine and output the LLR value for the repaired LDPC parity bits to the LLR value for the LDPC parity bits, or output the received repaired The LLR value for the LDPC parity bits or the LLR value for the received LDPC parity bits.

In another example, FIG. 26 shows a case where some of the LDPC parity bits transmitted without being punctured are repetition-2, the remaining part is repetition-1, and the punctured LDPC parity bits are repetition-1 to be.

In this case, the LLR combiners 2240 and 2340 can process in the same manner as described above in the case of the 1-time repetition. However, the LLR combiners 2240 and 2340 can process the second repetition portion as follows. In this case, one of the 2-repetition LDPC parity bits is referred to as first rep- resented LDPC parity bits, and the other is referred to as first rep- resented LDPC parity bits.

Specifically, the LLR combiners 2240 and 2340 compute an LLR value for each of the first repeated LDPC parity bits and the second repeated LDPC parity bits with an LLR value for the LDPC parity bits, And output it. Alternatively, the LLR combiners 2240 and 2340 may combine and output the LLR values for the first repeated LDPC parity bits with the LLR values for the LDPC parity bits, or output the second repeated LDPC parity bits And outputs the LLR value for the first repeated LDPC parity bits to the LLR value for the second repeated LDPC parity bits. Can be combined and output. Alternatively, the LLR combiners 2240 and 2340 may output the LLR values for the first repeated LDPC parity bits, the second repeated LDPC parity bits, or the LDPC parity bits without a separate combine have.

The LLR combiner 2340 may also combine the LLR values corresponding to the additional parity bits with another LLR value. Here, the different LLR values may be the LLR values for the LDPC parity bits based on the generation of additional parity bits in the transmitting apparatus 100, i.e., the LDPC parity bits that have been selected for generation of the additional parity bits.

That is, as described above, the transmitting apparatus 100 can map the additional parity bits for the L1-detail signaling transmitted in the current frame to a previous frame and transmit the mapped additional parity bits to the receiving apparatus 200. [

In this case, the additional parity bits may be punctured to include LDPC parity bits that are not transmitted in the current frame, and may further include LDPC parity bits transmitted in the current frame, as the case may be.

Accordingly, the LLR combiner 2340 adds the LLR value for the additional parity bits received through the current frame to the LLR value inserted at the position of the punctured LDPC parity bits in the LDPC codeword received through the next frame, It can be combined with the LLR value for the LDPC parity bits received via the next frame.

To this end, the receiving apparatus 200 may store information on parameters and / or patterns used for generating additional parity bits in the transmitting apparatus 100 according to a mode. Accordingly, the LLR combiner 2340 determines the length of the additional parity bits, determines the position of the LDPC parity bits based on generation of the additional parity bits, adds the LLR value of the additional parity bits to the additional parity bits Lt; RTI ID = 0.0 &gt; LDPC &lt; / RTI &gt; parity bits based on the generation of the LDPC parity bits.

The parity defer mutation units 2250 and 2350 can demultiplex the LLR values output from the LLR combiners 2240 and 2340.

Specifically, the parity defer mutation units 2250 and 2350 are elements corresponding to the parity permutation units 215 and 316 of the transmission apparatus 100 and correspond to the parity permutation units 215 and 316 Can be performed.

To this end, the receiving apparatus 200 may be storing information on parameters and / or patterns that the transmitting apparatus 100 has used for group-wise interleaving and parity interleaving according to a mode. Accordingly, the parity deriver mutators 2250 and 2350 perform the group-wise interleaving and the parity interleaving performed in the parity permutation units 215 and 316 inversely with respect to the LLR values corresponding to the LDPC codeword bits I.e., group-wise deinterleaving and parity deinterleaving operations, to parity-dip-mutate the LLR values corresponding to the LDPC codeword bits.

The LDPC decoders 2260 and 2360 can perform LDPC decoding based on the LLR values output from the parity deriver muting units 2250 and 2350.

Specifically, the LDPC decoders 2260 and 2360 are components corresponding to the LDPC encoders 214 and 315 of the transmission apparatus 100, and can perform operations corresponding to the LDPC encoders 214 and 315.

To this end, the receiving apparatus 200 may store information on parameters used for performing LDPC encoding according to a mode in the transmitting apparatus 100. [ Accordingly, the LDPC decoders 2260 and 2360 can perform the LDPC decoding based on the LLR values output from the parity deriving mutators 2250 and 2350 according to the mode.

For example, the LDPC decoders 2260 and 2260 may generate an LDPC code based on an LLR value output from the parity derive mutators 2250 and 2350 based on iterative decoding based on a sum-product algorithm Perform LDPC decoding, and output error corrected bits according to LDPC decoding.

The zero eliminators 2270 and 2370 may remove the zero bits from the bits output from the LDPC decoders 2260 and 2360.

Specifically, the zero elimination units 2270 and 2370 are elements corresponding to the zero padding units 213 and 314 of the transmission apparatus 100 and can perform operations corresponding to the zero padding units 213 and 314 .

To this end, the receiving apparatus 200 may store information on parameters and / or patterns used for padding the zero bits according to a mode in the transmitting apparatus 100. [ Accordingly, the zero elimination units 2270 and 2370 can remove the zero bits padded in the zero padding units 213 and 314 from the bits output from the LDPC decoders 2260 and 2360.

The BCH decoders 2280 and 2380 can BCH decode the bits output from the zero eliminators 2270 and 2370.

Specifically, the BCH decoders 2280 and 2380 correspond to the BCH encoders 212 and 313 of the transmitting apparatus 100, and can perform operations corresponding to the BCH encoders 212 and 313.

To this end, the receiving apparatus 200 may store information on parameters used to perform BCH encoding. Accordingly, the BCH decoders 2280 and 2380 can BCH decode the bits output from the zero eliminators 2270 and 2370, correct the error, and output the error-corrected bits.

The descramblers 2290 and 2390 can descramble the bits output from the BCH decoders 2280 and 2380.

Specifically, the descramblers 2290 and 2390 correspond to the scramblers 211 and 312 of the transmitting apparatus 100, and can perform operations corresponding to the scramblers 211 and 312.

For this purpose, the receiving apparatus 200 may store information on parameters that the transmitting apparatus 100 has used for scrambling. Accordingly, the descramblers 2290 and 2390 can descramble the bits output from the BCH decoders 2280 and 2380 and output them.

Accordingly, the L1 basic signaling transmitted from the transmitting apparatus 100 can be restored. If segmentation for L1 detail signaling is not performed in the transmission apparatus 100, the L1 detail signaling transmitted from the transmission apparatus 100 can also be restored.

However, when the transmission apparatus 100 performs segmentation on the L1 detail signaling, the demagnetization unit 2395 can de-segment the bits output from the descrambler 2390.

Specifically, the de-segmentation unit 2395 is a component corresponding to the segmentation unit 311 of the transmission apparatus 100, and can perform an operation corresponding to the segmentation unit 311. [

To this end, the receiving apparatus 200 may store information on parameters used by the transmitting apparatus 100 for segmentation. Accordingly, the demaggregation unit 2395 can combine the bits output from the descrambler 2390, that is, the segments for L1 detail signaling, to restore L1 detail signaling before segmentation.

On the other hand, information on the length of the L1 signaling is provided as shown in FIG. Accordingly, the receiving apparatus 200 can calculate the length for the L1 detail signaling and the length for the additional parity.

Referring to FIG. 27, the receiving apparatus 200 has to calculate the length of the L1 detail signaling and the length of the additional parity bits in that L1 basic signaling provides information of L1 detail total cells.

Specifically, when the L1B_L1_Detail_additional_parity_mode of L1 basic signaling non-zero, the information of a given L1B_L1_Detail_total_cells the total cell length (= N _{L1 _detail_total_cells)} to indicate so, the receiving device 200 is L1 detail on the basis of Equation 32 and 35 below It can calculate the length N and the length _{L1 _detail_cells} N _{AP_total_cells} for adding a parity for the signaling.

In this case, obtain the N _{AP_total_cells} value based on Equation 32 to Equation 34 N _{L1 _detail_total_cells} value and the N _FEC, N _{L1D_FECFRAME} and the modulation order (η _MOD) which can be obtained from the L1 basic signaling L1B_L1_Detail_total_cells information on the basis of . As an example, N _{AP_total_cells} can be calculated by the following equation (35).

The syntax and field semantics of the L1 basic signaling field are shown in Table 14 below.

Therefore, the receiving apparatus 200 can perform the receiver operation on the additional parity bits in the next frame based on the additional parity bits transmitted to the N _{AP_total_cells} cell among the received L1 detail cells.

28 is a flowchart illustrating a parity permutation method according to an embodiment of the present invention.

First, parity bits are generated by encoding input bits (S2510).

Subsequently, LDPC information bits including outer encoded bits and zero bits including input bits and parity bits are configured (S2520).

Then, LDPC information bits are encoded (S2530).

On the other hand, in step S2520, based on the shortening pattern as shown in Table 1, padding the zero bits into at least a part of the plurality of bit groups constituting the LDPC information bits.

Here, in step S2520, based on Equation (3) or (4), it is possible to calculate the number N _pad of the bit groups in which all bits among the plurality of bit groups are padded with zero bits.

In step S2520, all of the? _S (0) th bit group,? _S (1) th bit group, ...,? _S (N _pad -1) bit group among the plurality of bit groups Padding the zeros bits to bits and additionally padding zero bits to K _ldpc -N _outer -360 x N _pad bits from the first bit of the group of [pi] _s (N _pad ) bits.

On the other hand, specific methods for performing shortening based on Table 1 have been described above.

Meanwhile, a non-transitory computer readable medium in which a program for sequentially performing the shortening method according to the present invention is stored may be provided.

A non-transitory readable medium is a medium that stores data for a short period of time, such as a register, cache, memory, etc., but semi-permanently stores data and is readable by the apparatus. In particular, the various applications or programs described above may be stored on non-volatile readable media such as CD, DVD, hard disk, Blu-ray disk, USB, memory card, ROM,

Although the buses are not shown in the above-described block diagrams for the transmitting apparatus and the receiving apparatus, the communication between the respective elements in the transmitting apparatus and the receiving apparatus may be performed via the bus. In addition, each device may further include a processor such as a CPU, a microprocessor, or the like that performs the various operations described above, and each device may further include a memory for performing the various operations described above.

Also, in the embodiment of the present invention, terms such as "module", "unit", "part", and the like are terms for referring to components performing at least one function or operation, May be implemented in software or a combination of hardware and software. It should also be understood that a plurality of " modules ", " units ", " parts ", etc. may be integrated into at least one module or chip, (Not shown).

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, but, on the contrary, It will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the present invention.

100: transmitting apparatus 110: outer encoder
120: zero padding unit 130: LDPC encoder

Claims (4)

In a zero bit padding method of a transmitting apparatus,
Filling a bit region of a predetermined size with input bits and zero bits;
Encoding bits included in the bit region of the predetermined size;
Removing the zero bits of the encoded bits included in the bit region of the predetermined size; And
And mapping the remaining bits of the encoded bits included in the bit region of the predetermined size to the stores for quadrature phase shift keying (QPSK), wherein the zero bits are removed,
Wherein the encoding step comprises:
Encodes the bits included in the bit region of the predetermined size based on a LDPC (Low Density Parity Check) code according to a code rate of 3/15 and a code length of 16,200,
Wherein the filling step comprises:
Dividing the bit region of the predetermined size into a plurality of bit group regions, padding the zero bits into at least one bit group region of the plurality of bit group regions,
Wherein the order of the bit group areas in which the zero bits are padded is determined based on the following table:

Here, π _s (j) represents the index of the bit groups area padded with the j-th order bit of said plurality of group areas, N _{info _group} represents the number of the plurality of bit groups area. The method according to claim 1,
Wherein the filling step comprises:
And calculating the number of bit group areas in which all bits of the plurality of bit group areas are padded with zero bits based on the following equation: &lt; EMI ID =

Where N _pad is the number of bit group regions where all bits are padded with zero bits, K _ldpc is the number of bits contained in the bit region of the predetermined size, and N _outer is the number of input bits. 3. The method of claim 2,
Wherein the filling step comprises:
And zero bits are padded to all the bits of the bit group region from? _S (0) to? _S (N _pad -1) of the plurality of bit group regions based on the table. Way. The method of claim 3,
Wherein the filling step comprises:
π _s (N _pad) th bit from the first group, the second bit further of K _outer -360 _ldpc -N × N of zero _pad bits zero bit padding method characterized in that the padding of the area.

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