KR101897370B1 - Method and apparatus for replace page - Google Patents

Abstract

A page replacement method and a page replacement apparatus are disclosed. The disclosed page replacement method determines a replacement deferring value of each of a plurality of candidate pages included in a memory in consideration of a storage write generation amount and a page fault rate, Select a page of pages to be replaced in memory. At this time, the replacement reservation value may be calculated based on at least one of the number of dirty sub-pages and the performance status of the system.

Description

[0001] METHOD AND APPARATUS FOR REPLACE PAGE [0002]

The following description relates to a page replacement method and a page replacement apparatus, and more particularly, to a method and apparatus for selecting a sacrifice page based on a replacement reserve value determined in consideration of a storage write generation amount and a page failure rate.

The page replacement policy determines the order of release of the pages included in the page cache, based on the number of past references to the page and whether or not the reference time page is dirty. That is, the priority of a page in the page cache is based on whether the page is dirty to determine whether there is a change in the data contained in the page, the number of page references indicating how many times the page has been referenced from the process, and / The victim page is selected.

Such a page replacement policy is based on a hard disk drive (HDD), and the difference between the read speed and the write speed is small. However, a new page replacement policy is required as recent write speeds are 5 to 10 times slower than read speeds.

By selecting a sacrifice page based on the amount of storage writes and the rate of page absent, a new page replacement algorithm can be provided that is suitable for storage with a write rate slower than the read rate.

By choosing the sacrifice page based on the number of dirty subpages and the amount of storage writes, the write traffic on storage with slower write speeds can be reduced.

By selecting the sacrifice page in consideration of the performance status of the system, the sacrifice page can be dynamically selected according to the performance condition of the system.

A page replacement method according to an exemplary embodiment includes determining a replacement deferring value of each of a plurality of candidate pages included in a memory in consideration of a storage write generation amount and a page fault rate; And selecting a sacrificial page to be replaced in the memory among the candidate pages considering the replacement reserve value.

In the page replacement method according to an exemplary embodiment, the step of determining the replacement reserve value may include: determining a number of dirty sub pages related to the storage write amount among a plurality of sub pages constituting each of the candidate pages; Determining a performance condition of the system related to the page percentage; And calculating the replacement reservation value based on at least one of the number of the dirty sub-pages and the performance status of the system.

In the page replacement method according to an exemplary embodiment, the dirty subpage may be a subpage modified after being entered into the memory among the plurality of subpages.

In a page replacement method according to an embodiment, the performance status of the system may be determined based on at least one of a capacity of the memory and a performance importance of a processor requesting a page in the memory.

In a page replacement method according to an embodiment, the performance status of the system can be determined based on an increase or decrease in the rate of page failure for the memory, which occurs as the capacity of the memory varies.

In the page replacement method according to an embodiment, the step of calculating the replacement reservation value may calculate the replacement reservation value as the number of the dirty sub pages increases.

In the page replacement method according to an embodiment, the step of calculating the replacement reservation value may calculate the replacement reservation value as the performance condition of the system is better.

In the page replacement method according to an embodiment, the step of selecting the sacrifice page may select a candidate page whose number of replacement reservations exceeds the replacement reservation value among the plurality of candidate pages as a sacrifice page to be replaced in the memory.

In the page replacement method according to an embodiment, the plurality of candidate pages may be selected based on a reference bit indicating whether the plurality of pages included in the memory have recently been accessed.

A page replacement apparatus according to an exemplary embodiment includes a processor for selecting a sacrifice page to be replaced among a plurality of candidate pages included in a memory, And selects a sacrificial page to be replaced in the memory among the candidate pages by considering the replacement reserve value.

According to one embodiment, by selecting a sacrifice page based on the amount of storage writes and the rate of page absent, a new page replacement algorithm may be provided that is suitable for storage having a slower write speed than the read rate.

According to an embodiment, by selecting a sacrifice page in consideration of the storage write amount based on the number of dirty sub-pages, write traffic occurring in the storage having a write speed lower than the read speed can be reduced.

According to one embodiment, a sacrifice page can be dynamically selected according to the performance status of the system by selecting a sacrifice page in consideration of the performance status of the system.

1 is a diagram illustrating a relationship between a processor, a memory, and a storage according to an embodiment.
2 is a diagram illustrating an example of a page according to one embodiment.
3 is an illustration of an example of a plurality of pages included in a memory according to one embodiment.
4 is a diagram illustrating an example of a process of replacing a page in consideration of a performance status of a system according to an exemplary embodiment.
5 is a diagram illustrating an example of a page replacement algorithm in accordance with one embodiment.
FIGS. 6 and 7 are views illustrating an example of a page absent rate and a storage write amount according to the number of dirty sub pages according to an embodiment.
8 is an exemplary diagram illustrating a change in a coefficient according to an embodiment of the present invention.
9 is a diagram illustrating a page replacement method according to an embodiment.

Specific structural or functional descriptions of embodiments are set forth for illustration purposes only and may be embodied with various changes and modifications. Accordingly, the embodiments are not intended to be limited to the specific forms disclosed, and the scope of the disclosure includes changes, equivalents, or alternatives included in the technical idea.

The terms first or second, etc. may be used to describe various elements, but such terms should be interpreted solely for the purpose of distinguishing one element from another. For example, the first component may be referred to as a second component, and similarly, the second component may also be referred to as a first component.

It is to be understood that when an element is referred to as being "connected" to another element, it may be directly connected or connected to the other element, although other elements may be present in between.

The singular expressions include plural expressions unless the context clearly dictates otherwise. In this specification, the terms "comprises ", or" having ", and the like, are used to specify one or more of the described features, numbers, steps, operations, elements, But do not preclude the presence or addition of steps, operations, elements, parts, or combinations thereof.

Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art. Terms such as those defined in commonly used dictionaries are to be interpreted as having a meaning consistent with the meaning of the context in the relevant art and, unless explicitly defined herein, are to be interpreted as ideal or overly formal Do not.

The embodiments described below can be used to replace pages. Embodiments may be implemented in various forms of products such as personal computers, laptop computers, tablet computers, smart phones, smart home appliances, intelligent cars, kiosks, wearable devices, and the like. For example, embodiments may be applied to replacing pages contained in memory in smart phones, mobile devices, smart home systems, and the like. Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. Like reference symbols in the drawings denote like elements.

1 is a diagram illustrating a relationship between a processor, a memory, and a storage according to an embodiment.

Referring to FIG. 1, a processor 110, memory 120, and storage 130 in accordance with one embodiment are shown.

The processor 110 may request the memory 120 to provide the data necessary to run the program and may receive the requested data from the memory 120. [ For example, the processor 110 may be a Central Processing Unit (CPU), and may include an L1 I-cache, an L1 D-cache, an L2 cache, and a Last Level Cache (LLC).

The memory 120 may be a random access memory, for example, a dynamic random-access memory (DRAM). Memory 120 may include one or more pages received from storage 130. The processor 110 may read from the memory 120 at a high rate without receiving a page from the storage 130 if the page requested by the processor 110 is included in the memory 120. [

The storage 130 may be a data storage device having a slower write speed than the read speed, for example, a phase-change memory (PCM) and a flash memory. The storage 130 may also be referred to as a swap device.

In general, it is important to minimize storage access in system management since the storage 130 has a significantly slower rate than the memory 120. Here, when a page is requested by the processor 110, a rate at which a storage access is required because the corresponding page is not present in the memory 120 may be referred to as a page fault rate.

If the page requested by the processor 110 is not in the memory 120, the page is transferred from the storage 130 to the memory 120. At this time, if there is not enough free space for a new page because the memory 120 already contains many pages, a victim page is selected from a plurality of pages included in the memory 120, Thereby freeing up space for the page requested by the processor 110. This behavior can be referred to as page replacement. That is, the page replacement means an operation of releasing any one of a plurality of pages on the memory 120 in order to enter a new page into the memory 120 in a state where all the space of the memory 120 is being used .

If the sacrificial page emitted from the memory 120 has been modified after being imported into the memory 120, the sacrificial page may be written to the storage 130 and deleted from the memory 120. [ However, since the write speed of the storage 130 is slower than the read speed, if the amount of storage write due to the release of the victim page is large, the performance of the system may deteriorate. Therefore, it is necessary to take into consideration the storage write amount in the process of selecting the sacrifice page.

2 is a diagram illustrating an example of a page according to one embodiment.

Referring to FIG. 2, there is shown a diagram illustrating a page 200 included in a memory, according to one embodiment.

The page 200 may include a plurality of sub-pages 210, 220, 230, .... For example, the size of the page 200 may be set to 4 Kbytes, and the size of the sub page may be set to 512 bytes.

A page 200 may have a reference bit set. The reference bit may indicate whether the page 200 has been recently accessed. For example, reference bit '1' may indicate that page 200 has not been accessed recently, and reference bit '0' may indicate that page 200 has been accessed recently. A process of selecting a candidate page among a plurality of pages included in the memory based on the reference bit will be described later with reference to FIG.

Each of the plurality of sub pages 210, 220, 230, ... may be set with a dirty bit. The dirty bit may indicate whether the subpage has been modified since it was imported into memory. For example, the dirty bit '0' indicates that the subpage has not been modified since it was imported into memory, and the dirty bit '1' may indicate that the subpage was modified after being imported into memory. Thus, for dirty bit '1', when a page containing a modified subpage in memory is released from memory, the modified subpage must be flushed to storage. This dirty bit may be set from '0' to '1' when the LLC cache block is rewritten to a page of memory. The dirty bit can be taken into account when estimating the amount of storage write caused by the release of the page.

Referring to the dirty bits in FIG. 2, the first sub page 210, the third sub page 230, and the second sub page 220 indicate unmodified subpages after being imported into the memory, The modified subpage may be displayed after being imported into the subpage.

The reference bits and dirty bits described above are according to one embodiment. In some cases, the meaning indicated by '0' and '1' may be opposite to each other.

3 is an illustration of an example of a plurality of pages included in a memory according to one embodiment.

Referring to FIG. 3, a plurality of pages included in memory 300 are illustrated in accordance with one embodiment.

A candidate page among a plurality of pages included in the memory 300 may be selected based on the reference bit. For convenience of explanation, in FIG. 3, reference bits can be represented by numbers in parentheses. That is, the reference bits of the first page 310, the third page 330, the fourth page 340 and the sixth page 360 are '0', and the second page 320, the fifth page 350 ) May be '1'.

A page having a reference bit set to '0' among a plurality of pages may be selected as a candidate page. For example, in FIG. 3, the first page 310, the third page 330, the fourth page 340, and the sixth page 360 may be selected as candidate pages.

Among the selected candidate pages, the sacrifice page can be selected based on the dirty bit. The dirty subpages associated with the storage write incidence among the plurality of pages included in each of the candidate pages may be identified based on the dirty bit. The number of dirty subpages included in each of the candidate pages may be determined based on the identification result.

The more dirty pages the larger the number of sub-pages, the greater the amount of storage writes generated when selected as the victim page. Thus, by determining the sacrifice page based on the number of dirty subpages associated with the amount of storage writes, it is possible to replace the page with minimal storage write throughput.

In the example illustrated in FIG. 3, the third page 330 has the largest number of dirty subpages among the candidate pages, so that the third page 330 is reserved as much as possible in the memory 300, Can be reduced. On the other hand, since the number of dirty subpages of the first page 310 is the smallest, it is possible to perform page replacement while minimizing the storage write amount by selecting the first page 310 as a sacrifice page.

4 is a diagram illustrating an example of a process of replacing a page in consideration of a performance status of a system according to an exemplary embodiment.

Referring to FIG. 4, an example of a process of replacing a page in consideration of a performance situation of a system according to an embodiment is shown.

The sacrificial page may be selected from the candidate pages based on the page absent rate. The sacrifice page can be selected based on the performance status of the system in relation to the page absent rate.

The performance status of the system refers to the overall system in which the memory is utilized and may be determined based on at least one of, for example, the capacity of the memory and the performance importance of the processor requesting the page in memory.

For example, the performance status of the system can be determined based on an increase or decrease in the rate of page absences for a memory that occurs as the capacity of the memory varies. It is assumed that the additional memory 420 is allocated to the pre-allocated memory 410.

At this time, if the performance of the page is improved due to a decrease in the page absent rate, it can be judged that the performance of the system is not good. That is, in this case, it can be determined that the current memory 410 is insufficient. Since the performance situation of the system is not good, the sacrifice page may be selected so that the page miss rate is reduced rather than the sacrifice page is selected so that the storage write amount is reduced.

Conversely, if the variation of the page percentage is below a predetermined reference value, the performance condition of the system can be judged to be good. That is, in this case, it can be determined that the current memory 410 is sufficient. Since the performance of the system is good, the sacrifice page may be selected to reduce the amount of storage writes generated rather than selecting a sacrifice page so that the percentage of page misses is reduced.

Thus, the performance status of the system may be determined based on the difference between the page absent rate of the currently pre-allocated memory 410 and the page absent rate when the additional memory 420 is provided. This technique can be referred to as Belady's lifetime function. Belady's lifetime function can be a function that approximates the hit ratio of references as the memory size changes. The page absent rate A _i can be calculated by the following equation (1).

In the above equation (1), i represents a memory size, and c and k represent control parameters. The control parameter can determine the degree of temporal locality. For example, as c becomes smaller or k becomes larger, provisional zoning can increase.

5 is a diagram illustrating an example of a page replacement algorithm in accordance with one embodiment.

Referring to FIG. 5, an example of a page replacement algorithm according to one embodiment is shown.

A page replacement device according to one embodiment can replace pages in the main memory layer at the top of the storage based on a page replacement policy called WS-CLOCK (Working-Set Sensitive CLOCK). The main memory is a memory 120 of FIG. 1, which can exchange data with an LLC on a subpage-by-subpage basis, and can perform storage and communication on a page-by-page basis.

The WS-CLOCK can simultaneously reduce page outage rate and storage write throughput (e.g., write traffic) by selecting a sacrifice page to replace in memory based on the reference bits of each page and the dirty bits contained in each page. When the page is accessed, the dirty bit of the accessed subpage may be set to '1' when the reference bit of the page is set to '1' and the access is write.

Like CLOCK, WS-CLOCK can use a clock-hand that moves in a specific direction through a circular list of pages. Whenever a replacement is needed to accommodate a new page, the WS-CLOCK can check the reference bit and dirtiness of the page pointed to by the clock-hand. Here, the dirty degree can be determined by the number of dirty sub-pages in the page. If the reference bit is '1', WS-CLOCK can reset the reference bit of the page to '0' and move the clock-hand to the next page. If the reference bit is '0', WS-CLOCK can check the dirty level of the page. In WS-CLOCK, the release of dirty pages may be deferred for a certain number of clock cycles even if the page reference bit is '0'. To this end, WS-CLOCK can control the deferring count of each page. If the reservation count of the page does not exceed a predetermined reservation level, the clock-hand may proceed to the next page. This process can be repeated until the WS-CLOCK finds the victim page.

WS-CLOCK can assign different reservation levels to the page based on the dirty information of the page. That is, the higher the number of dirty sub pages, the higher the reserve level can be allocated. x can be set to the number of dirty subpages included in the page, and the function f can be set to the reserved level of the page in proportion to the dirtiness of the page. Where f may be a monotonic increasing function. This can mean that the page that causes WS-CLOCK to generate a large amount of storage writes will hold it in memory for a long time.

The algorithm shown in Fig. 5 relates to the operations described above. Here, the deferring count can be calculated as the product of the number of dirty subpages and a coefficient. The number of dirty subpages may indicate the number of dirty subpages included in the page based on one page.

In addition, the coefficient may indicate the performance status of the system. For example, when the performance of the system is good, the coefficient is determined to be high, so the retention rate can also be determined to be high. On the other hand, when the performance of the system is not good, the coefficient is determined to be low, and the retention rate can be determined to be low. A high reserve rate may mean that a page containing a large number of dirty subpages will hold more release from memory.

FIGS. 6 and 7 are views illustrating an example of a page absent rate and a storage write amount according to the number of dirty sub pages according to an embodiment.

Referring to Figures 6 and 7, an example of measured page yield and storage write throughput in a number of exemplary situations in accordance with one embodiment is shown.

If the memory capacity is not sufficient to accommodate the full working-set pages, the page-unavailability can be greatly reduced if the memory is heavily occupied by dirty pages. It is necessary to set an appropriate reservation level for the performance status of the system.

Figures 6 and 7 illustrate virtual memory access traces of four Linux applications, such as the freecell game, the gedit text editor, the kghostview PDF file viewer, and the xmms music player. The results are shown. The characteristics of each virtual memory access trace may be as shown in Table 1 below. In this virtual memory access trace, the page size is set to 4 Kbytes and the sub page size is set to 512 bytes, so that the page can be composed of 8 sub pages.

FIGS. 6 and 7 show the page absent rate and the storage write generation amount (for example, the total write traffic number) as the function f changes. The memory size can be set to 10% and 30% of the memory footprint for each workload. As shown in FIG. 6 and FIG. 7, when the reserved level is high while the performance is degraded, the amount of storage write can be reduced. This may indicate that there is a tradeoff between page outage rate and storage write generation. The optimal reservation level depends on the workload and the system state, and can not be fixed simply. Thus, you can monitor the current working set size of the system and control the reservation level for the page so as not to degrade system performance. For example, if the system's current working set size is large, WS-CLOCK can keep the reservation level low and focus on reducing page faults for overall system performance. Conversely, if the system has sufficient memory (ie, a small set of operations), WS-CLOCK can maintain a high reserve level to reduce storage write throughput.

8 is an exemplary diagram illustrating a change in a coefficient according to an embodiment of the present invention.

Referring to Fig. 8, the coefficient variation of the function f according to the performance condition of the system is shown.

The total memory size can be set to 20% of the smallest footprint of any running application. By changing the number of running applications to 1, 2, 3, 1, 4, and 4 over time, we controlled the working set size. As shown in FIG. 8, the larger the working set size, the lower the deferring level. Conversely, the smaller the working set size, the higher the retention level can be.

9 is a diagram illustrating a page replacement method according to an embodiment.

Referring to Fig. 9, a page replacement method performed by a processor of a page replacement apparatus according to an embodiment is shown.

In step 910, the page replacement apparatus determines a replacement deferring value of each of a plurality of candidate pages included in the memory in consideration of the storage write generation amount and the page fault rate.

The page replacement apparatus can determine the number of dirty subpages related to the storage write generation amount among the plurality of subpages constituting each of the candidate pages. The page replacement apparatus can determine the performance status of the system related to the page absent rate. The page replacement device may then calculate a replacement reservation value based on at least one of the number of dirty sub-pages and the performance status of the system.

Here, the dirty subpage may be a modified subpage after being entered into the memory among the plurality of subpages.

In addition, the performance status of the system can be determined based on at least one of the capacity of the memory and the performance importance of the processor requesting pages in the memory.

For example, the performance status of the system can be determined based on an increase or decrease in the rate of page failure for a memory that occurs as the capacity of the memory varies. The greater the decrease in the percentage of page faults with respect to the memory that occurs as the memory capacity increases, the more the performance of the system may be determined to be poor. When the fluctuation of the page absent rate with respect to the memory that occurs as the capacity of the memory increases is less than or equal to a predetermined reference value, the performance condition of the system can be determined to be good.

In addition, the performance importance of the processor may refer to the processor performance dependency required when the program is run. Higher processor performance implies that high performance of the processor is required and that the page miss rate is low. Therefore, it is determined that the performance of the system is not good as the performance importance of the processor is high, so that it is possible to focus on improving the page absent rate. Conversely, the lower the performance importance of a processor, the better the performance of the system is determined to be good, reducing the amount of storage write can be focused.

The page replacement apparatus according to an exemplary embodiment may calculate a lower reserve value as the number of dirty sub pages increases. Also, the page replacement apparatus can calculate a higher reserve replacement value as the system performance condition is better.

Here, the plurality of candidate pages may be selected based on a reference bit indicating whether the plurality of pages included in the memory have been recently accessed.

In step 920, the page replacement apparatus selects a sacrificial page to be replaced in the memory among the candidate pages in consideration of the replacement reservation value. For example, the page replacement apparatus can select a candidate page among the plurality of candidate pages whose replacement reservation count exceeds the replacement reservation value as a sacrifice page to be replaced in the memory. Here, the number of replacement reservations may mean the number of times that the page is not replaced and is reserved.

Here, the replacement reservation value is a value indicating the degree to which a specific page is reserved in the memory, for example, the reservation rate, the reservation count, and the reservation level described above.

The steps described above with reference to FIGS. 1 to 8 are applied to each step shown in FIG. 9 as it is, and a detailed description will be omitted.

The embodiments described above may be implemented in hardware components, software components, and / or a combination of hardware components and software components. For example, the devices, methods, and components described in the embodiments may be implemented within a computer system, such as, for example, a processor, a controller, an arithmetic logic unit (ALU), a digital signal processor, such as an array, a programmable logic unit (PLU), a microprocessor, or any other device capable of executing and responding to instructions. The processing device may execute an operating system (OS) and one or more software applications running on the operating system. The processing device may also access, store, manipulate, process, and generate data in response to execution of the software. For ease of understanding, the processing apparatus may be described as being used singly, but those skilled in the art will recognize that the processing apparatus may have a plurality of processing elements and / As shown in FIG. For example, the processing unit may comprise a plurality of processors or one processor and one controller. Other processing configurations are also possible, such as a parallel processor.

The software may include a computer program, code, instructions, or a combination of one or more of the foregoing, and may be configured to configure the processing device to operate as desired or to process it collectively or collectively Device can be commanded. The software and / or data may be in the form of any type of machine, component, physical device, virtual equipment, computer storage media, or device , Or may be permanently or temporarily embodied in a transmitted signal wave. The software may be distributed over a networked computer system and stored or executed in a distributed manner. The software and data may be stored on one or more computer readable recording media.

The method according to an embodiment may be implemented in the form of a program command that can be executed through various computer means and recorded in a computer-readable medium. The computer-readable medium may include program instructions, data files, data structures, and the like, alone or in combination. The program instructions to be recorded on the medium may be those specially designed and configured for the embodiments or may be available to those skilled in the art of computer software. Examples of computer-readable media include magnetic media such as hard disks, floppy disks and magnetic tape; optical media such as CD-ROMs and DVDs; magnetic media such as floppy disks; Magneto-optical media, and hardware devices specifically configured to store and execute program instructions such as ROM, RAM, flash memory, and the like. Examples of program instructions include machine language code such as those produced by a compiler, as well as high-level language code that can be executed by a computer using an interpreter or the like. The hardware devices described above may be configured to operate as one or more software modules to perform the operations of the embodiments, and vice versa.

The components described in the embodiments may be implemented by a programmable logic device such as one or more DSP (Digital Signal Processor), a processor, a controller, an application specific integrated circuit (ASIC), and a field programmable gate array Logic Element, other electronic devices, and combinations thereof. ≪ RTI ID = 0.0 > At least some of the functions or processes described in the embodiments may be implemented by software, and the software may be recorded in a recording medium. The components, functions and processes described in the embodiments may be implemented by a combination of hardware and software.

Although the embodiments have been described with reference to the drawings, various technical modifications and variations may be applied to those skilled in the art. For example, it is to be understood that the techniques described may be performed in a different order than the described methods, and / or that components of the described systems, structures, devices, circuits, Lt; / RTI > or equivalents, even if it is replaced or replaced.

110: Processor
120: Memory
130: Storage

Claims (14)

Determining a replacement deferring value of each of a plurality of candidate pages included in the memory in consideration of a storage write generation amount and a page fault rate; And
Selecting a sacrificial page to be replaced in the memory among the candidate pages in consideration of the replacement reserve value
Lt; / RTI >
The step of determining the replacement reserve value
Determining a replacement reservation value based on the performance status of the system related to the page percentage and the storage write amount,
The performance status of the system may include,
Is determined based on an increase or decrease in the rate of page faults in the memory caused by a change in the amount of use of the memory, and the difference between the page fault rate of the currently allocated memory and the page fault rate when the additional memory is provided Lt; / RTI >
Wherein the step of selecting the sacrificial page comprises:
Wherein the storage write generation amount is reduced without selecting a sacrifice page so that the page absent rate is reduced when the variation of the page absence rate is equal to or less than a predetermined reference value as the usage amount of the memory is increased or decreased. The method according to claim 1,
Wherein the step of determining the replacement reservation value comprises:
Determining a number of dirty subpages related to the storage write generation amount among a plurality of subpages constituting each of the candidate pages;
Determining a performance condition of the system related to the page percentage; And
Calculating the replacement reservation value based on at least one of the number of the dirty sub-pages and the performance status of the system
/ RTI > 3. The method of claim 2,
The dirty sub-
Wherein the subpage is a subpage modified after being entered into the memory among the plurality of subpages. 3. The method of claim 2,
The performance status of the system may include,
The amount of memory used, and the performance importance of the processor requesting a page in the memory. The method according to claim 1,
Wherein when the amount of the page is decreased as the amount of use of the memory increases, the sacrifice page is selected so as to decrease the rate of page faults. 3. The method of claim 2,
Wherein the step of calculating the replacement reservation value comprises:
Wherein the replacement reservation value is calculated to be higher as the number of dirty subpages increases. 3. The method of claim 2,
Wherein the step of calculating the replacement reservation value comprises:
Wherein the replacement reserve value is calculated to be higher as the performance condition of the system is better. The method according to claim 1,
Wherein the step of selecting the sacrificial page comprises:
Wherein a candidate page in which the number of replacement reservations exceeds a replacement reservation value among the plurality of candidate pages is selected as a sacrifice page to be replaced in the memory. The method according to claim 1,
The plurality of candidate pages may include:
Wherein the page is selected based on a reference bit indicating whether the plurality of pages included in the memory have recently been accessed. And a processor for selecting a sacrificial page to be replaced among a plurality of candidate pages included in the memory,
The processor comprising:
Determining a replacement deferring value of each of the plurality of candidate pages based on a performance status of the system and a storage write occurrence amount related to a page absent rate,
Selecting a sacrifice page to be replaced in the memory among the candidate pages in consideration of the replacement reserve value,
The performance status of the system may include,
The page absent rate of the currently pre-allocated memory and the page absent rate of the page memory when the additional memory is provided is determined and determined based on an increase or decrease in the page absent rate for the memory that occurs as the usage amount of the memory varies. Rate, < / RTI >
The processor comprising:
Wherein the storage write generation amount is reduced without selecting a sacrifice page so that the page absent rate is reduced when the fluctuation of the page absence rate is equal to or less than a predetermined reference value as the usage amount of the memory is increased or decreased. 11. The method of claim 10,
The processor comprising:
Determining a replacement reservation value based on at least one of a number of dirty subpages associated with the storage write amount and a performance status of the system related to the page percentage,
The dirty sub-
And a dirty subpage related to the storage write generation amount among a plurality of subpages constituting each of the candidate pages. 12. The method of claim 11,
The performance status of the system may include,
The amount of memory used, or the performance importance of the processor requesting a page in the memory. 12. The method of claim 11,
The processor comprising:
And calculates a lower reserve value as the number of the dirty sub pages increases. 12. The method of claim 11,
The processor comprising:
And the higher the performance condition of the system, the higher the replacement reserve value.

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