KR101886056B1 - forming method of nanostructure pattern by vacuum deposition and sensor device thereby - Google Patents

Abstract

The present invention provides a method for forming a nanostructure pattern using a vacuum deposition process, the method comprising: a first step of preparing a substrate; a second step of forming a mask pattern layer exposing a part of the upper surface of the substrate; A third step of setting a vacuum deposition condition that satisfies a minimum critical radius of the nanostructure necessary for growing the nanostructure on the exposed region and the mask pattern layer; A fourth step of growing a nanostructure on the mask pattern layer and a fifth step of removing the mask pattern layer to form a nanostructure on the exposed region of the substrate to form a nanostructure pattern on the substrate Wherein the surface of the substrate of the first step is subjected to hydrophobic surface treatment to form the mask pattern layer of the second step, After forming a mask pattern layer in step 2, the sensor element method nanostructure pattern formed by vacuum deposition, and using the same to the partial region of the substrate exposed to the upper characterized in that hydrophobic surface treatment by a technical base. Accordingly, the present invention forms a nanostructure pattern on a substrate using a vacuum deposition process by setting vacuum deposition conditions that satisfy a minimum critical radius of a nanostructure necessary for growing the nanostructure, It is possible to form a nanostructure pattern having a structure distribution easily and it is possible to form a nanostructure pattern on a flexible substrate such as a polymer substrate which is vulnerable to high temperature because a heat treatment process is not required and minimizing the shape and thickness deformation of the nanostructure There is an advantage that a high-quality device can be provided.

Description

[0001] The present invention relates to a method of forming a nanostructure pattern by vacuum deposition and a sensor element using the same,

The present invention relates to a method for forming a nanostructure pattern by using a vacuum deposition process, which comprises subjecting a substrate surface to a hydrophobic surface treatment for uniform growth of a nanostructure and setting a vacuum deposition condition satisfying a minimum critical radius required for growing the nanostructure A method of forming a nanostructure pattern on a substrate using a vacuum deposition process, a method of manufacturing a sensor element using the same, and a sensor element manufactured thereby.

In recent years, studies on nanostructures and their fabrication methods have been actively pursued in accordance with the trend toward high integration and miniaturization of devices. In general, nanostructures exhibit different properties depending on the particle size, material, and shape.

Such nanostructures are utilized in various fields such as materials, electric and electronic fields as well as biotechnology, and are used in various fields such as display, sensor, laser, LED, solar cell, and capacitor by forming a specific pattern.

In a conventional method of forming a nanostructure, a chemical process (Korean Patent No. 10-1032791) in which a dispersion solvent containing nanoparticles is coated on a substrate and a solvent is removed through a sintering process (Korean Patent No. 10-1032791) It has been widely used because it can be mass-produced at a high cost.

However, this conventional chemical method has disadvantages in that uniform adsorption of nanoparticles on a large-sized substrate is not easy, and the size control of nanoparticles is not easy and the utilization thereof is low.

In addition, this method is not easy to form a pattern, has a high temperature and pressure in a sintering process, and has difficulty in a process. It is difficult to uniformly disperse nanoparticles in a solvent and to distribute the nanoparticles uniformly on a substrate , And does not contribute to improvement of efficiency using nanoparticles.

In particular, nanoparticles exhibit various properties depending on the size, shape, etc. of the pattern. In order to utilize these characteristics, it is very important to control the pattern using nanoparticles for each application field and to form a pattern having a uniform distribution of nanoparticles in a desired shape and size at appropriate positions.

Accordingly, a method of forming a nanopattern by various methods has been studied. In the past, a method including a photolithography process or a nanoimprint lithography process, a thin film deposition process, a patterning process, an etching process, And a technique for forming nanoparticles on the seed layer (Korean Patent Registration No. 1419531, Application No. 10-2015-0001430).

However, in the above method, since a mask (or a mask layer) or an imprint stamp corresponding to the size and density of the nanopattern must be fabricated, the process is complicated and the formation of a single type of nanopattern corresponding to the mask or imprint stamp pattern The control of the nano pattern is not easy and the process of depositing and removing the seed layer is required and the process is complicated.

Particularly, in the case of forming a sensor detection material used for a sensor element, a photoresist pattern is formed on a substrate, and a dispersion solvent containing nanoparticles by the chemical method described above is dropped on the substrate on which the photoresist pattern is formed However, it is difficult to uniformly form a nanostructure on the detection material formation region due to the agglomeration of nanoparticles as described above. Thus, a sensor device with high sensitivity There have been difficulties in making.

In addition, these processes must be accompanied by a heat treatment process at a high temperature of 500 ° C or more, such as forming a nanostructure by inducing de-wetting by a heat treatment process. Thus, the time required for the temperature increase The process takes a long time and the heat treatment is carried out at a temperature higher than 500 ° C, which makes it difficult to form a nanostructure on a flexible substrate such as a polymer substrate.

Further, diffusion and intermixing of the element material may occur due to the heat treatment process at a high temperature, or the shape and thickness of the nanostructure may be deformed, which may degrade the quality and characteristics of the device. do.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and it is an object of the present invention to provide a method of manufacturing a nanostructure by hydrophobic surface treatment of a substrate surface for uniform growth of a nanostructure and vacuum deposition conditions satisfying a minimum critical radius required for growing the nanostructure, A method of forming a nanostructure pattern on a substrate, a method of manufacturing a sensor element using the same, and a sensor element manufactured by the method.

According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising the steps of: preparing a substrate; forming a mask pattern layer exposing a part of the upper surface of the substrate; A third step of setting a vacuum deposition condition that satisfies the minimum critical radius of the nanostructure necessary for growth of the nanostructure, and a third step of growing a nanostructure on the exposed region of the substrate and the mask pattern layer by a vacuum deposition process And a fifth step of removing the mask pattern layer to form a nanostructure on the exposed region of the substrate to form a nanostructure pattern on the substrate, After forming the mask pattern layer of the second step after the hydrophobic surface treatment of the surface of the base material or after forming the mask pattern layer of the second step, And a nanostructure pattern by vacuum deposition characterized in that hydrophobic surface treatment to the exposed area of the upper part forming method and a sensor device using the same technology as a base.

The present invention relates to a method of forming a nanostructure pattern on a substrate using a vacuum deposition process by setting a vacuum deposition condition that satisfies a minimum critical radius required for growing a nanostructure, As a result, there is no need to manufacture a separate mask or imprint stamp for forming the nanostructure pattern, or to form a seed layer, thereby simplifying the process.

In addition, it is possible to form various types of nanostructure patterns easily and easily according to vacuum deposition conditions, and basically, the nanostructures can be uniformly distributed on a substrate. In addition to the size and shape of the nanostructure pattern Position control can be easily performed, and the nanostructure pattern can be easily formed while having a uniform nanostructure distribution as a whole.

In addition, by setting special vacuum deposition conditions, a conventional heat treatment process is not required, and the process time for warming and lowering the temperature to a high temperature heat treatment temperature is drastically shortened, which is economical. It is expected that the formation of the nanostructure pattern is easy and the application fields thereof will be diversified.

Further, a heat treatment step at a high temperature is not required, problems such as diffusion and mixing of element materials can be prevented, and the shape and thickness deformation of the nanostructure can be minimized, thereby providing a high-quality device.

Particularly, in the case of forming the detection region used for the sensor element, the detection substance is formed in the nanostructure pattern on the detection substance formation region by the vacuum deposition process according to the specially set vacuum deposition condition, not by the conventional chemical method It is easy to form a uniform detection region and it is possible to provide a sensor element with high sensitivity.

1 to 4 are schematic views of a method of forming a nanostructure pattern by vacuum deposition according to the present invention.
FIG. 5 is a view showing a mechanism for setting a deposition rate and a deposition thickness range to satisfy a minimum critical radius of a nanostructure for growing a nanostructure according to the present invention. FIG.
Figure 6 - SEM (Scanning Electron Microscope) image of Au nanostructure shape by controlling the thickness of Au deposition by E-beam evaporator on Si substrate after hydrophobic surface treatment of Si substrate without hydrophobic surface treatment Fig.
FIG. 7 - Diameter distribution of Au nanostructure on 5 nm thick Au deposited on Si substrate by electron beam evaporator after hydrophobic surface treatment of Si substrate and hydrophobic surface treatment.
8 is a graph showing the results of SEM image and energy dispersive X-ray analysis (EDX) of an Au nanostructure and a pattern after 5 nm thick Au deposition on an Si substrate and a PC substrate using an electron beam evaporator. .
FIG. 9 is a graph showing a shape analysis (SEM image) and a composition analysis (EDX) of a Pt nanostructure and a pattern after depositing 5 nm thick Pt on an Si substrate and a PC substrate using an electron beam evaporator.
FIG. 10 is a graph showing the shape analysis (SEM image) and the component analysis (EDX) of a Pd nanostructure and a pattern after 5 nm thick Pd deposition on an Si substrate and a PC substrate using an electron beam evaporator.
11 - Analysis of shape (SEM image) and composition of Pt and Pd nanostructures and patterns after continuously depositing 5 nm thick Pt and 5 nm thick Pd on an Si substrate and a PC substrate in an in-situ manner using an electron beam evaporator Analysis (EDX) results.
FIG. 12 is a graph showing a shape analysis (SEM image) and a composition analysis (EDX) of a TiO ₂ nanostructure and a pattern after 5 nm thick TiO ₂ deposition on an Si substrate and a PC substrate using an electron beam evaporator.
FIG. 13 is a graph showing a shape analysis (SEM image) and a composition analysis (EDX) of a ZnS nanostructure and a pattern after 5 nm thick ZnS deposition on an Si substrate and a PC substrate using an electron beam evaporator.
FIG. 14 is a graph showing the shape analysis (SEM image) and the composition analysis (EDX) of a MgF ₂ nanostructure and a pattern after depositing 5 nm thick MgF ₂ on an Si substrate and a PC substrate using an electron beam evaporator.
15 is a diagram showing the shape analysis (SEM image) and the component analysis (EDX) of an InP nano structure and a pattern after InP deposition of 20 nm thickness on a Si substrate by chemical vapor deposition (CVD).
FIG. 16 is a graph showing the shape analysis (SEM image) and the composition analysis (EDX) of an Au nanostructure and a pattern after depositing 5 nm thick Au on a Si substrate and a PC substrate by sputtering.
Fig. 17 is a SEM image of an Au nanostructure pattern using nano / micro scale unevenness formed substrate. Fig.
18 shows an SEM image of an embodiment in which an Au nanostructure is applied to a sensor sensing material for application as a sensor sensing material.
19 - PC substrate was subjected to hydrophobic surface treatment and hydrophobic surface treatment, and 1.5 nm thick Au was deposited on PC substrate using electron beam evaporator, and then UV-Vis spectrophotometer was used (SPR) characteristic analysis result of the surface plasmon resonance (SPR) characteristic data.

The present invention relates to a method for forming a nanostructure pattern by using a vacuum deposition process, and more particularly, to a method for hydrophobic surface treatment of a substrate surface for uniform growth of a nanostructure and a vacuum deposition condition satisfying a minimum critical radius required for growing the nanostructure And a nanostructure pattern is formed on the substrate using a vacuum deposition process.

This makes it unnecessary to manufacture a mask or an imprint stamp or a seed layer for manufacturing a nanostructure pattern, simplifying the process, facilitating control of the nanostructure pattern for each application field according to vacuum deposition conditions, It is possible to form various types of nanostructure patterns easily and easily.

In addition, by forming the nanostructure pattern by a vacuum deposition process, basically, the nanostructure can be uniformly distributed on the substrate, and the size and shape of the nanostructure pattern as well as the position control can be easily controlled, It is easy to form a nanostructure pattern while having a distribution.

In addition, by setting the special vacuum deposition conditions, the conventional heat treatment process is not required, and the process time for heating and lowering the temperature to the high temperature heat treatment temperature is drastically shortened, and the nanostructure on the flexible substrate, It is expected that pattern formation will be easy and the application field will be diversified.

Further, it is unnecessary to carry out a heat treatment step at a high temperature, and problems such as diffusion and mixing of element materials can be prevented, and it is possible to provide a high-quality element by minimizing the shape and thickness deformation of the nanostructure.

Particularly, in the case of forming the detection region used for the sensor element, the detection substance is formed in the nanostructure pattern on the detection substance formation region by the vacuum deposition process according to the specially set vacuum deposition condition, not by the conventional chemical method It is easy to form a uniform detection region, and a sensor element with high sensitivity can be provided.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings. 1 to 4 are schematic views illustrating a method of forming a nanostructure pattern by vacuum deposition according to the present invention.

As shown in FIG. 1, a method of forming a nanostructure pattern by vacuum deposition according to the present invention includes a first step of preparing a substrate, a second step of forming a mask pattern layer exposing a part of the upper surface of the substrate, A third step of setting a vacuum deposition condition that satisfies the exposed region of the substrate and the minimum critical radius of the nanostructure necessary for growth of the nanostructure on the mask pattern layer; A fourth step of growing a nanostructure on the mask pattern layer and a fourth step of forming a nanostructure pattern on the substrate by forming the nanostructure on the exposed region of the substrate by removing the mask pattern layer, Wherein the surface of the substrate of the first step is subjected to a hydrophobic surface treatment to form the mask pattern layer of the second step, After the mask pattern layer of the second stage is formed, a part of the exposed top of the substrate is subjected to hydrophobic surface treatment.

The present invention relates to a method of forming a nanostructure pattern on a substrate, wherein the nanostructure has a size of several nanometers to several hundreds of nanometers and is not limited in shape and size such as a cylinder, a cone, a spherical shape or a polygonal shape, Is implemented in a predetermined pattern so as to be suitable for an application field, it is referred to as a nanostructure pattern in the present invention.

Such a nanostructure pattern may be formed in a single pattern on various types of substrates (substrate or thin film, transistor structure in a sensor element), or by repeating a single pattern or combining various patterns in accordance with application fields of devices And these patterns may be implemented regularly or irregularly. The nanostructure forming material for this purpose can be variously implemented as a single layer or a plurality of layers of homogeneous or heterogeneous materials.

As shown in FIG. 1, in the method of forming a nanostructure pattern by vacuum deposition according to the present invention, a substrate is first prepared (first step), and a mask pattern layer is formed to expose a part of the upper surface of the substrate . (Step 2)

As described above, the substrate may be of various types depending on the application of the nanostructure pattern, and may be a substrate, a thin film, a transistor structure in a sensor element, or the like.

Specifically, the substrate (substrate in the transistor structure) may be formed of a material selected from the group consisting of silicon (Si), gallium arsenide (GaAs), gallium phosphorus (GaP), gallium arsenide (GaAsP), boron nitride (BN), SiC, GaN, ZnO, MgO, sapphire, quartz, and glass can be used.

In addition, depending on the field of application, the substrate may be formed of a material selected from the group consisting of polycarbonate (PC), polyethylene naphthalate (PEN), polynorbornene (PN), polyacrylate, polyvinyl alcohol , PVA), polyimide (PI), polyethylene terephthalate (PET), polyethersulfone (PES), polystyrene (PS), polypropylene (PP), polyethylene (PE), polyvinylchloride (PVC), polyamide (PA), polybutyleneterephthalate (PBT), polymethyl methacrylate (PMMA) and polydimethylsiloxane ) Can be used.

On this substrate, a mask layer made of a thermosetting resin or a photocurable resin, specifically, an imprint resin, a lithography resist, or the like may be formed, or a photosensitive film using DFR (Dry Film Resist) or the like, a SiO ₂ SiN _x and a Si ₃ N ₄ is formed and then patterned to form a mask pattern layer such that a part of the upper surface of the substrate is exposed.

Here, after the surface of the substrate is subjected to the hydrophobic surface treatment, the mask pattern layer is formed (Figs. 1 and 3) or after the mask pattern layer is formed, the surface of the exposed part of the upper surface of the substrate is covered with a hydrophobic surface (Fig. 2 and Fig. 4).

The hydrophobic surface treatment may be performed before or after the mask pattern layer is formed according to the type of the base material and the mask pattern layer, the hydrophobic surface treatment method, and the surface of a part of the substrate exposed by the mask pattern layer, Coating or plasma treatment.

The hydrophobic material may be coated on the surface of the substrate with an anti-sticking material. The anti-sticking material may include octadecyltrichlorosilane (OTS), 1H, 1H, 2H, 2H-perfluorodecyltrichlorosilane (FDTS), tridecafluoro- Any one of 1,1,2,2-tetra-hydrocytyltrichlorosilane (FOTS), dichlorodimethylsilane (DDMS) and diamond-like carbon (DLC) may be used.

Hydrophobic surface treatment of the substrate surface minimizes adhesion on the surface of the nanostructure to increase the contact angle between the nanostructure and the substrate surface to uniformly induce the size of the nanostructure generating nuclei to form a uniform nanostructure .

The irregularities may be first formed on the prepared substrate of the first step, and the irregularities may be formed in a pattern of nano or microscale by a separate patterning and etching process on the substrate, and various patterns of nanostructure patterns As shown in Fig.

As shown in FIG. 3, after the hydrophobic surface treatment of the surface of the substrate having the irregularities formed thereon, a mask pattern layer may be formed to expose a part of the upper surface of the substrate having the irregularities formed thereon. Alternatively, A mask pattern layer may be formed on a substrate and a hydrophobic surface treatment may be performed on a part of the substrate exposed by the mask pattern layer.

Here, before forming the mask layer for forming the mask pattern layer, a polymer layer may be formed on the substrate, and a mask pattern layer may be formed on the polymer layer.

The polymer layer may be selectively formed depending on the kind of the substrate, the purpose of use, the kind of the mask layer formed on the substrate, or the like, and the coating property and the film property of the mask layer formed on the polymer layer And etching resistance in the dry etching process in the patterning process, contributing to the precise formation of the mask pattern layer.

The polymer layer is formed by dry-etching a part of the polymer layer using the mask pattern layer as a dry etching mask to expose a part of the lower substrate in a part of the polymer layer, As the structure is formed, it contributes to formation of a precise nanostructure pattern.

The polymer layer may be formed of a material selected from the group consisting of polyvinyl chloride (PVC), neoprene, polyvinyl alcohol (PVA), poly methyl methacrylate (PMMA), polybenzyl methacrylate (PBMA), polystyrene, spin on glass (SOG), polydimethylsiloxane , Polyvinyl formal (PVFM), parylene, polyester, epoxy, polyether, polyimide, and lift-off resist (LOR).

Then, after forming a mask pattern layer exposing a part of the substrate, a vacuum deposition condition that satisfies the minimum critical radius of the nanostructure for the growth of the nanostructure on the exposed region of the substrate and the mask pattern layer (Step 3)

That is, a vacuum deposition condition is set so as to satisfy the minimum critical radius for growing the nano structure as a nano structure without growing the nano structure, and then the exposed region of the substrate and the mask pattern layer Thereby growing the nanostructure. (Step 4)

The vacuum deposition conditions are preferably set such that the deposition rate is in a range of 0.01 nm / second to 5 nm / second and a thickness of 30 nm or less.

This shows the mechanism for setting the deposition rate and the deposition thickness range to satisfy the minimum critical radius (r _crit in FIG. 5) of the nanostructure for nanostructure growth, as shown in FIG.

As shown in FIG. 5, when the radius of the nanostructure is r _crit or more, the nanostructure can be continuously grown so that it grows as a crystal nucleus and exists as a stable nanostructure. When the radius of the nanostructure is r _crit Or less, the thermodynamically stable state can not be maintained, so that the particles can not grow into nuclei, and the unstable particle state is maintained.

The vacuum deposition condition according to the present invention is that the deposition rate is in the range of 0.01 nm / sec to 5 nm / sec and the nanostructure is grown to a thickness of 30 nm or less. When the condition is that the radius of the nanostructure is r _crit or more Followed by a minimum radius condition that can grow into crystal nuclei.

In other words, when the deposition rate is out of the range, the crystal nuclei that can grow as a nanostructure can not be formed, and cotton growth occurs mainly through volume growth rather than volume growth. When the thickness of the nanostructure is thicker than that, Growth is made by thin film instead of structure.

By thus growing the nanostructure by the vacuum deposition process, it is possible to uniformly distribute the nanostructure on the substrate, and it is possible to easily control the position and the size of the nanostructure pattern as well as the pattern, do.

In addition, by growing the nanostructure by a vacuum deposition process, it is not necessary to manufacture a separate mask or imprint stamp or a seed layer forming process for manufacturing the nanostructure pattern, and the process is simple, and the nanostructure The pattern can be easily controlled and the formation of various types of nanostructure patterns can be easily and easily formed.

After the vacuum deposition conditions are set, the nanostructure is grown on the exposed region of the substrate and on the mask pattern layer by a vacuum evaporation process under vacuum deposition conditions satisfying the minimum critical radius of the nanostructure.

That is, the nanostructure is grown while satisfying the minimum critical radius condition for nanostructure formation using the set vacuum deposition conditions.

The nanostructure may be first grown by a vacuum deposition process under a vacuum deposition condition satisfying a minimum critical radius of the nanostructure, plasma treatment or heat treatment may be performed on the primarily grown nanostructure, And secondarily growing the nanostructure at a relatively high deposition rate as compared to the deposition conditions.

In other words, a low-speed deposition rate is set so that a nanostructure having a minimum critical radius required for nanostructure formation in the first step is formed in order to form a uniform nanostructure by the 2 step method. And then the nuclei are crystallized through plasma treatment or heat treatment. In the second step, nanostructures are formed at a relatively higher deposition rate than the vacuum deposition conditions in the first step Thereby making it possible to form uniform nanostructures with excellent crystallinity in a short period of time as a whole.

In addition, after the nanostructure is first grown by a vacuum deposition process under a vacuum deposition condition that satisfies the minimum critical radius of the nanostructure, the nanostructure is grown at a deposition rate different from the deposition rate in the vacuum deposition condition, (1 + n) (where n is a natural number of 1, 2, 3, ..., and n is a natural number) of the same or different nanostructures.

That is, to control the crystallinity of the nanostructure by the (1 + n) step method and to realize the growth of the nanostructure having various composition profiles or crystal structures. In the first step, A low rate deposition rate is set to produce a nanostructure with the required minimum critical radius to induce uniform size nucleation and a different deposition rate, such as a higher deposition rate, a lower deposition rate, (1 + n) (n is 1, 2, 3,, and n are natural numbers) at the deposition rate alternately implemented.

Here, the nanostructures grown in each deposition step can be grown with different deposition rates in the same kind, and can be grown with different deposition rates in different kinds.

Thus, various composition profiles, crystal structures, surface states, and shapes according to the deposition rate can be realized while achieving uniform growth and crystallinity of the nanostructure, thereby adapting to various application fields.

In addition, after the first nano structure is grown, plasma processing or heat treatment may be selectively performed on the nano structure grown in the first nano structure before the next nano structure growth. This may further improve the crystallinity of the grown nano structure Thereby improving the characteristics of the device.

As described above, in the present invention, by setting special vacuum deposition conditions for growing the nanostructure, the conventional heat treatment process becomes unnecessary, and the process time for the temperature increase and the temperature decrease to the high temperature heat treatment temperature is drastically shortened. The present invention can be applied to a flexible substrate such as a polymer substrate.

Further, the heat treatment step at a high temperature is not necessary, problems such as diffusion and mixing of element materials can be prevented, and the shape and thickness deformation of the nanostructure can be minimized, thereby providing a high-quality device.

The nanostructure can be variously provided depending on the application field. In particular, in the case of a sensor element, various materials can be deposited according to a substance to be detected, and a metal, a metal oxide, a fluoride, a sulfide and a phosphide Or more by vacuum evaporation using the above-mentioned material to form the exposed region of the substrate and the mask pattern layer.

The growth of the nanostructure can be performed multiple times or different times of the same kind of material under the same deposition condition or different deposition conditions as required for the application field and the necessity.

The growth of the nanostructure can be accomplished by a vacuum deposition process according to a predetermined vacuum deposition condition and can be realized by at least one of an electron beam evaporator, a thermal evaporation evaporator, a sputtering process, and a chemical vapor deposition . However, the present invention is not limited to such a vacuum deposition process and a variety of known vacuum deposition processes or methods may be used as needed.

Here, the diameter of the nanostructure and the spacing of the nanostructures can be basically controlled according to the vacuum deposition conditions. In addition, after the growth of the nanostructure by the vacuum deposition process, a heat treatment process or a plasma treatment process is performed, The diameter of the structure and the spacing of the nanostructures can be controlled.

Then, after the nano structure is grown on the exposed region of the substrate and the mask pattern layer, the mask pattern layer is removed to form a nanostructure on the exposed region of the substrate, (Step 5)

That is, when the mask pattern layer is removed on the substrate, a nanostructure pattern having a pattern corresponding to the mask pattern layer on the substrate is formed.

The chemical solution to be used may be acetone, isopropyl alcohol, water (H ₂ O), KOH, NaOH, NH ₄ OH, H ₂ SO ₄ , HF, HCl, H ₃ PO ₄ , HNO ₃ , CH ₃ COOH, H ₂ O ₂ and BOE (Buffered Oxide Etchant), and uses dipping or sonication.

On the other hand, an additional mask pattern layer may be formed after removal of the mask pattern layer in accordance with the application field or the purpose of use, and the nanostructure of the fourth step may be formed on the same region or another region where the nanostructure pattern on the substrate is formed. By additionally forming a homologous or heterogeneous nanostructure, a continuous or discontinuous nanostructure pattern may be additionally formed from the nanostructure pattern of the fifth step.

The nanostructure pattern formed by the vacuum deposition according to the present invention may also be realized as a sensing material of a sensor element. The nanostructure pattern may include a GaN buffer layer formed on a substrate, a GaN layer formed on the buffer layer, A substrate including a source electrode and a drain electrode formed on the one kind of layer and one kind of layer selected from the group consisting of an Al _x Ga _{1 - x} N layer, an InAlN layer and an InAlGaN layer formed, Forming a mask pattern layer which exposes a part of the base material while masking the drain electrode and the exposed region of the base material and a minimum critical radius of the nanostructure necessary for growing the nanostructure on the mask pattern layer, And a step of growing a nanostructure on the exposed region of the substrate and the mask pattern layer by a vacuum deposition process, By removing the group mask pattern layer, it is made larger in a step of forming a nanostructure on an exposed region of the substrate to form a nanostructure pattern on the substrate top.

Here, hydrophobic surface treatment may be performed on a part of the upper portion of the substrate before or after the mask pattern layer is formed, or hydrophobic surface treatment may be performed on a part of the exposed portion of the substrate.

The important structure of the HEMT (High Electron Mobility Transistor) element is a well-known technology, and a method of manufacturing a sensor having a high electron mobility transistor structure (Appl. No. 10-2016- 0036136), and a detailed description thereof will be omitted in the present invention.

As described above, basically, a mask pattern layer is formed on a substrate, and a nanostructure pattern is formed by a vacuum deposition process. Thus, a duplicate description will be omitted. A buffer layer of GaN series formed on a substrate, a GaN layer formed on the buffer layer, an Al _x Ga _{1 - x} N layer formed on the GaN layer, an InAlN layer and an InAlGaN layer (e.g., HEMT) And a source electrode and a drain electrode formed on the one kind of layer.

Forming a mask pattern layer for masking the source electrode and the drain electrode on the substrate so as to hydrophobic surface-treat a part of the upper surface of the substrate and to expose a part of the substrate; masking the source electrode and the drain electrode, After forming a mask pattern layer that exposes a part of the base material, the surface of a part of the exposed base material is subjected to a hydrophobic surface treatment.

The x value of the Al _x Ga _{1 - x} N layer is 0 <x? 1, and a GaN cap layer having a thickness of 10 nm or less may be additionally formed on the one layer.

Further, it is possible to form a recessed region in which a part of the one kind of layer is etched, after mask patterning the source electrode and the drain electrode, and forming a mask pattern layer exposing a part of the upper part of the substrate.

The recess region is a part of the exposed upper part of the substrate, that is, a part of the area between the source electrode and the drain electrode. By etching the recessed area, the area of the sensing material forming area is widened to increase the sensor sensitivity.

The formation of the recessed region may be realized by dry or wet etching after masking an area other than the region where the recessed region is to be formed.

In this case, the nanostructure is grown by setting deposition conditions that satisfy the minimum critical radius condition for forming the above-described nanostructure on a part of the exposed top of the substrate, thereby forming a nanostructure pattern corresponding to the mask pattern layer Respectively.

A part of the exposed upper part of the substrate on which the nanostructure is grown becomes a part of a region between the source electrode and the drain electrode and a sensing material layer of the sensor element is formed on this area, The nanostructures are grown with the detection material for the nanostructure.

Here, the nanostructure for forming the detection material layer is formed by vacuum deposition using at least one of metal, metal oxide, fluoride, sulfide and phosphide, and reacts with a gas or biochemical substance to be detected, A material capable of changing the potential of the active layer is selected and used.

For example, Pd, Pt or Pd and Pt are used as the detection substance of hydrogen gas, ZnO nanowire is used as a detection substance of Co gas, InZnO is used as detection substance of oxygen gas, Ag / AgCl electrode, ZnO nanorod as a detection substance of clucose or lactic acid, and thioglycolic acid / Au as a detection substance of water temperature ion.

In addition to the above-exemplified detection substances, it is also possible to grow the nanostructure a plurality of times in the same or different materials as required, depending on the substance or environment to be sensed, or after the removal of the mask pattern layer, A pattern layer is formed on the substrate and the same or different types of nanostructures as the nanostructure are additionally formed on the same region or another region on which the nanostructure pattern on the substrate is formed to form a continuous or discontinuous nanostructure Pattern can be additionally formed.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

In the hydrophobic surface treatment, the Si substrate, the PC substrate and the FOTS solution were placed in a sealed space and heated at 80 ° C for 15 minutes using a vacuum oven. The FOTS solution was vaporized and bonded onto the Si substrate, The surface of the substrate was subjected to a hydrophobic treatment. FIG. 6A shows the results of deposition of Au thicknesses of 0.75 nm, 1.5 nm, 5 nm, 10 nm and 20 nm, respectively, at a deposition rate of 0.025 nm / sec using an electron beam evaporator without hydrophobic surface treatment of the Si surface, After surface treatment, Au was deposited at 0.75 nm, 1.5 nm, 5 nm, 10 nm, and 20 nm, respectively, at a deposition rate of 0.025 nm / sec. As the thickness of the Au deposition increases, the size of the Au nanostructure increases, and it is confirmed that the diameter and distribution of the Au nanostructure can be controlled by adjusting the Au thickness. In addition, it was confirmed that the control of the deposition thickness is an important factor in the diameter, shape and distribution of the Au nanostructure.

7 is a diameter distribution diagram of an Au nanostructure on a Si substrate without a hydrophobic surface treatment and a 5 nm thick Au deposition on an Si substrate with an electron beam evaporator after hydrophobic surface treatment. The average diameter of the Au nanostructures formed on the substrate without the hydrophobic surface treatment was 16.9 nm, and the average diameter of the Au nanostructures when the hydrophobic surface treatment was performed was 10.2 nm. The hydrophobic surface treatment on the surface of the base material through the present embodiment (Figs. 6 and 7) minimizes the adhesion on the substrate surface when the nanostructure is formed, uniformly inducing the size of the nanostructure generating nuclei, It was confirmed that the formation of

Only a rectangular area (10 탆 by 75 탆 and 20 탆 by 80 탆) was opened with a photoresist on top of a Si wafer and a PC substrate having a thickness of 200 탆, and hydrophobic surface treatment was performed by the above method. Thereafter, Au was deposited to a thickness of 5 nm at a deposition rate of 0.025 nm / sec using an electron beam evaporator, followed by dipping in acetone to remove the photoresist, ultrasonication for 10 minutes, N ₂ blowing, Are shown in Figs. 8 (a) and 8 (b). 8 (c) and (d)], it was confirmed that Au nanostructure formation and Au nanostructure pattern fabrication were possible on Si wafer and PC substrate.

Only a rectangular area (10 탆 by 75 탆 and 20 탆 by 80 탆) was opened with a photoresist on top of a Si wafer and a PC substrate having a thickness of 200 탆, and hydrophobic surface treatment was performed by the above method. Thereafter, Pt was deposited to a thickness of 5 nm at a deposition rate of 0.025 nm / sec using an electron beam evaporator, and then dipped in acetone for 10 minutes to remove the photoresist. Ultrasonication was performed for 10 minutes. After N ₂ blowing, Are shown in Figs. 9 (a) and 9 (b). 9 (c) and (d)), it was confirmed that the Pt nanostructure and the Pt nanostructure pattern can be fabricated on the Si wafer and the PC substrate.

Only a rectangular area (10 탆 by 75 탆 and 20 탆 by 80 탆) was opened with a photoresist on top of a Si wafer and a PC substrate having a thickness of 200 탆, and hydrophobic surface treatment was performed by the above method. Thereafter, Pd was deposited to a thickness of 5 nm at a deposition rate of 0.025 nm / sec using an electron beam evaporator. Ultrasonication was performed for 10 minutes by dipping in acetone to remove the photoresist, followed by N ₂ blowing, 10 (a) and 10 (b). 10 (c) and (d)), it was confirmed that Pd nanostructure formation and Pd nanostructure pattern fabrication were possible on Si wafer and PC substrate.

Only a rectangular area (10 탆 by 75 탆 and 20 탆 by 80 탆) was opened with a photoresist on top of a Si wafer and a PC substrate having a thickness of 200 탆, and hydrophobic surface treatment was performed by the above method. Then, the thicknesses of Pt and Pd were continuously deposited in-situ at a deposition rate of 0.025 nm / sec using an electron beam evaporator, and then dipped in acetone and subjected to ultrasonication for 10 minutes to remove the photoresist. N ₂ The pattern results of the composite nanostructure after blowing are shown in FIGS. 11 (a) and (b). 11 (c) and (d)), it was confirmed that Pt and Pd composite nanostructures and Pt and Pd composite nanostructure patterns can be fabricated on Si wafer and PC substrate.

Only a rectangular area (10 탆 by 75 탆 and 20 탆 by 80 탆) was opened with a photoresist on top of a Si wafer and a PC substrate having a thickness of 200 탆, and hydrophobic surface treatment was performed by the above method. Thereafter, TiO ₂ was deposited to a thickness of 5 nm at a deposition rate of 0.025 nm / sec using an electron beam evaporator, then dipped in acetone to remove the photoresist, ultrasonicated for 10 minutes, and then subjected to N ₂ blowing. The results are shown in Figs. 12 (a) and 12 (b). In addition, EDX component analysis result of Fig. 12 (c), (d) ] for the manufacture of forming and TiO ₂ nanostructure pattern of the TiO ₂ nanostructure available Si wafer and the PC substrate was confirmed by.

Only a rectangular area (10 탆 by 75 탆 and 20 탆 by 80 탆) was opened with a photoresist on top of a Si wafer and a PC substrate having a thickness of 200 탆, and hydrophobic surface treatment was performed by the above method. After that, ZnS was deposited to a thickness of 5 nm at an evaporation rate of 0.025 nm / sec using an electron beam evaporator, and then dipped in acetone to remove the photoresist and subjected to ultrasonication for 10 minutes. After N ₂ blowing, Are shown in Figs. 13 (a) and 13 (b). 13 (c) and (d)), it was confirmed that ZnS nanostructure and ZnS nanostructure pattern can be formed on Si wafer and PC substrate.

Only a rectangular area (10 탆 by 75 탆 and 20 탆 by 80 탆) was opened with a photoresist on top of a Si wafer and a PC substrate having a thickness of 200 탆, and hydrophobic surface treatment was performed by the above method. Subsequently, MgF ₂ was deposited to a thickness of 5 nm at a deposition rate of 0.025 nm / sec using an electron beam evaporator, followed by dipping in acetone to remove the photoresist, ultrasonication for 10 minutes, N ₂ blowing, The results are shown in Figs. 14 (a) and 14 (b). In addition, EDX component analysis result of Fig. 14 (c), (d) ] for the production of formed and MgF ₂ nanostructure pattern of MgF ₂ nanostructures are possible in Si wafer and the PC substrate was confirmed by an.

A 50 nm thick SiO ₂ thin film was deposited by a chemical vapor deposition method. Only a rectangular region (10 μm by 75 μm and 20 μm by 80 μm) was opened with a photoresist and then a dry etching process was performed to form a Si surface . Then, hydrophobic surface treatment was carried out by the above-mentioned method, and InP was deposited to a thickness of 20 nm at a deposition rate of 5 nm / sec using a chemical vapor deposition method. Then, HF was dipped for 5 minutes in order to remove the SiO ₂ mask pattern layer, The pattern results of the nanostructure after rinsing on the wafer are shown in Figs. 15 (a) and (b). In addition, it was confirmed through the EDX component analysis (Fig. 15 (c)) that formation of an InP nano structure and pattern formation on a Si wafer were possible.

As shown in FIGS. 8, 12, 13, 14, and 15, it was confirmed that nanostructures having various components such as oxides, sulfides, fluorides, and phosphates as well as metals can be formed.

In this method, only a rectangular area (10 μm by 75 μm and 20 μm by 80 μm) was opened as a photoresist on a hydrophobic surface-treated Si wafer and a 200 μm thick PC substrate, and then sputtering was performed to deposit 0.25 nm / sec After the Au layer was deposited to a thickness of 5 nm, the pattern of the nanostructure was observed after dipping in acetone and ultrasonication for 10 minutes to remove the photoresist and N ₂ blowing. The results of the patterning of the nanostructure are shown in FIGS. 16 (a) and 16 (b). 16 (c) and (d)), it was confirmed that the Au nanostructure and the Au nanostructure pattern could be formed on the Si wafer and the PC substrate, and the average diameter of the Au nanostructure was 16.5 nm. From this result, it was possible to form an Au nanostructure having a nanostructure similar to an electron beam evaporator. 8 (b) and FIG. 16 (b), the deposition rate was 0.025 nm / sec (average diameter 10.2 nm) to 0.25 nm / sec (average diameter 16.5 nm], the average diameter of the Au nanostructures increased. From these results, it was confirmed that the deposition rate is an important factor in controlling the diameter size of the Au nanostructure.

Also, as shown in FIGS. 8 and 16, it was confirmed that the nanostructure can be formed through the hydrophobic surface treatment of the substrate surface before and after the formation of the mask pattern layer in order to form the nanostructure.

A 50 nm line, a 500 nm line and a 1 micron line pattern are formed on the top of a Si wafer by using electron beam lithography and photolithography, and then the electron beam lithography and the photolithography resist pattern are dry etched on the lower Si substrate , A Si structure having a 50 nm line, a 500 nm line and a 1 탆 line pattern (irregularities) having a height of 200 nm was prepared.

950 PMMA A5 (Micro Chem Co., USA) was spin-coated on top of 50 nm line, 500 nm line and 1 μm line (nano or micro) Si structure at 2000 rpm and baked at 170 ° C. for 300 seconds to form a 350 nm thick PMMA layer A perfluoropolyether (PFPE) resin was dropped onto a silicon master stamp (Si Stamp having a hole diameter of 300 nm), and a PET (polyethylene-terephthalate) substrate was squeezed. A PFPE mold was produced. After the imprint resin was spin-coated on the top of the PMMA layer with NIP-SC28LV400 (Chem Optics, Korea), the pillar-patterned PFPE stamps were pressed, irradiated with ultraviolet rays for 2 minutes, and PFPE stamps were relieved, An imprint pattern having a hole diameter was formed on top of a Si structure having a 50 nm line, a 500 nm line and a 1 탆 line pattern. Thereafter, the imprint residual film was descumped and the PMMA layer under the 300 nm Hole was etched to expose the surface of the Si structure having the 50 nm line, the 500 nm line and the 1 탆 line pattern located under the hole of 300 nm diameter, a).

Thereafter, hydrophobic surface treatment was performed on the top of the Si structure having the nano / micro concave and convex portions formed by the above-mentioned method, and then Au was deposited to a thickness of 5 nm at a deposition rate of 0.025 nm / sec using an electron beam evaporator. As a result, it was confirmed that an Au nanostructure was formed inside the hole.

17 (c). The result of N ₂ blowing is shown in Fig. 17 (c). Au nanostructures are formed on the top of a 50 nm line, a 500 nm line and a 1 μm line (nano or micro) It was confirmed that the pattern was patterned in a hole region having a diameter of 300 nm. From this result, it was confirmed that a nanostructure can be formed on a nano or microscale pattern (concavity and convexity).

In order to apply the technique of the present invention to a sensor for detecting a nano structure, a 2 nm thick GaN layer (GaN cap layer) / a 20 nm thick AlGaN layer / a 2 um thick GaN buffer layer / sapphire substrate is subjected to photolithography The resist was left only in the isolation region, and the resist pattern was subjected to 500 nm dry etching (Isolation process [Fig. 18 (a)] using a dry etching mask. After that, only the source and drain electrode regions were opened by photolithography for the ohmic contact and then Ti / Al / Ni / Au (20 nm / 100 nm / 25 nm / 50 nm) was deposited using an electron beam evaporator. 18 (b) and 18 (c)). In order to form the pad metal electrode, only the pad metal region is opened to the photoresist by photolithography After that, Ti / Au = 30 nm / 270 nm was deposited using an electron beam evaporator, and then the photoresist was removed to form a pad metal electrode (FIG. 18 (d)). Then, only the rectangular area (20 탆 by 70 탆), which is a sensor detection material region, was opened with a photoresist, hydrophobic surface treatment was carried out by the above-mentioned method, and an electron beam evaporator was used at a deposition rate of 0.025 nm / The result of removing the photoresist after depositing the thickness of 5 nm is shown in FIG. By this method, it was confirmed that the Au nanostructure can be uniformly formed in the entire area of the sensor detection material (20 μm by 70 μm, FIG. 18 (e)).

FIG. 19 is a graph showing the results of the measurement of the thicknesses of Au films deposited on hydrophobic surface treated PC substrates and hydrophobic surface treated PC substrates using an electron beam evaporator, Surface plasmon resonance characteristics. In the case of a sample subjected to a hydrophobic surface treatment on a PC substrate, it can be seen that the maximum absorption peak wavelength value of the Au nanostructure is shifted to a short wavelength (Blue shift) as compared with a sample not subjected to the hydrophobic surface treatment. It was confirmed that the full width at half maximum (FWHM) value of the Au nanostructure was smaller than the half width value of the Au nanostructure of the sample without the hydrophobic surface treatment. That is, it can be seen that the diameter of the Au nanostructure of the sample subjected to the hydrophobic surface treatment is smaller than that of the sample having the maximum absorption peak wavelength shifted to a shorter wavelength. From the point where the half width value of the peak is smaller, It was confirmed that the nanostructure size distribution was narrower (Narrow).

It can be confirmed that the hydrophobic surface treatment of the substrate or the thin film can form a nanostructure having a uniform nanostructure size and a narrow size distribution as compared with the case where the surface treatment is not performed.

Claims (15)

A first step of preparing a substrate;
A second step of forming a mask pattern layer exposing a part of the upper surface of the substrate;
A third step of setting a vacuum deposition condition that satisfies the exposed region of the substrate and the minimum critical radius of the nanostructure necessary for growth of the nanostructure on the mask pattern layer;
A fourth step of growing the nanostructure on the exposed region of the substrate and the mask pattern layer by a vacuum deposition process; And
And a fifth step of removing the mask pattern layer to form a nanostructure on an exposed region of the substrate to form a nanostructure pattern on the substrate,
The surface of the base material of the first step is subjected to hydrophobic surface treatment to form the mask pattern layer of the second step,
After the mask pattern layer of the second step is formed, a portion of the exposed upper portion of the substrate is subjected to hydrophobic surface treatment,
In the third step,
The deposition rate is set to a thickness of 30 nm or less in a range of 0.01 nm / second to 5 nm / second, and the diameter of the nanostructure and the interval of the nanostructures are controlled according to the vacuum deposition conditions A method of pattern formation of nanostructure by vacuum deposition. The method according to claim 1, wherein the hydrophobic surface treatment comprises:
Wherein the nanostructure pattern is formed by coating a hydrophobic substance on the entire surface of the substrate or by plasma treatment. The method as claimed in claim 1,
Wherein the nanostructure is grown by a vacuum deposition process under a vacuum deposition condition satisfying the minimum critical radius of the nanostructure of the third step. The method as claimed in claim 1,
A first step of growing the nanostructure by a vacuum deposition process under a vacuum deposition condition satisfying the minimum critical radius of the nanostructure of the third step,
The first grown nanostructure is subjected to a plasma treatment or a heat treatment,
Wherein the nanostructure is grown at a relatively higher deposition rate than the vacuum deposition conditions. The method as claimed in claim 1,
A first step of growing the nanostructure by a vacuum deposition process under a vacuum deposition condition satisfying the minimum critical radius of the nanostructure of the third step,
(1 + n) (where n is 1, 2, 3, ..., n) of the nanostructure and the homologous or heterogeneous nanostructure in the primary growth at a deposition rate different from the deposition rate in the vacuum deposition condition, Wherein the nanostructured material is continuously grown at a temperature higher than the melting point of the nanostructure. 6. The method of claim 5, wherein after growing the first-order nanostructure,
Wherein the nanostructure grown in the previous step is selectively subjected to a plasma treatment or a heat treatment prior to the next step of growing the nanostructure. delete The method of forming a pattern of a nanostructure according to claim 1, wherein the base material of the first step is formed with unevenness. The substrate according to claim 1,
And an inorganic material substrate made of one of silicon (Si), gallium arsenide (GaAs), gallium phosphorus (GaP), gallium arsenide (GaAsP), boron nitride (BN), SiC, GaN, ZnO, MgO, sapphire, quartz, Lt; / RTI &
The above-
Polycarbonate (PC), polyethylene naphthalate (PEN), polynorbornene (PN), polyacrylate, polyvinyl alcohol (PVA), polyimide ), Polyethylene terephthalate (PET), polyethersulfone (PES), polystyrene (PS), polypropylene (PP), polyethylene (PE), polyvinylchloride And is a polymer substrate that is any one of polyvinylidene chloride (PVC), polyamide (PA), polybutyleneterephthalate (PBT), polymethyl methacrylate (PMMA) and polydimethylsiloxane To form a nanostructure pattern by vacuum deposition. 2. The method of claim 1,
A polymer layer is formed on the substrate, a mask pattern layer is formed on the polymer layer,
Wherein the polymer layer
Polyvinyl Chloride (PVC), Neoprene, PVA (Polyvinyl Alcohol), PMMA (Poly Methyl Meta Acrylate), PBMA (Poly Benzyl Meta Acrylate), PolyStylene, SOG (Spin On Glass), PDMS (Polydimethylsiloxane) , Parylene, polyester, epoxy, polyether, polyimide, and lift-off resist (LOR). 2. The nanostructure according to claim 1,
A method of forming a pattern of a nanostructure by vacuum vapor deposition, characterized in that vacuum deposition is performed using at least one of a metal, a metal oxide, a fluoride, a sulfide, and a phosphide. The method according to claim 1, wherein the growth of the nanostructure of the fourth step comprises:
A method of forming a pattern of a nanostructure by vacuum vapor deposition, characterized in that the same material or different materials are vapor-deposited a plurality of times. 2. The method of claim 1, wherein, after growing the nanostructure of the fourth step,
Wherein a heat treatment process or a plasma treatment process is further implemented. &Lt; RTI ID = 0.0 &gt; 18. &lt; / RTI &gt; The method as claimed in claim 1,
After the removal of the mask pattern layer, an additional mask pattern layer is formed,
The nanostructure of the fourth step is further formed with the same or different kind of nanostructure as the nanostructure of the fourth step on the same region or another region where the nanostructure pattern on the substrate is formed, Wherein a structure pattern is additionally formed on the surface of the nanostructure. A sensor element using a nanostructure pattern, which is produced by the method of any one of claims 1 to 6 and 8 to 14.

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