KR101884094B1 - Apparatus and method for controlling voltage of a multilevel converter - Google Patents

Abstract

In one embodiment, a method for controlling the voltage of a multi-level converter comprising a NPC topology and a secondary circuit including a full bridge, in one embodiment, includes the steps of: Controlling a plurality of switches for controlling at a multilevel according to a first switching pattern and controlling the plurality of switches in accordance with a second switching pattern in a falling period of the primary side voltage, The switching pattern and the second switching pattern are set such that the voltage waveform of the rising section and the voltage waveform of the falling section do not have symmetry with each other.

Description

TECHNICAL FIELD [0001] The present invention relates to a method and an apparatus for controlling a voltage of a multilevel converter,

To a method and apparatus for controlling the voltage of a multi-level converter, and more particularly to a method and apparatus for controlling voltage for energy transfer in a multi-level DC-DC converter based on Power Electronics technology do.

In recent years, there have been many cases where high voltage is used in the industry, and instead of increasing the rated voltage, a method of applying multi-level voltage to the converter is widely used. Among the methods of applying multi-level voltage, a three-level Neutral Point Clamped DAB (Dual Active Bridge) converter has a structure in which two switches are connected in series and a diode is added as compared with a single level DAB converter, and a single level DAB Like the converter, the energy is transferred using the phase difference between the primary side voltage and the secondary side voltage of the inductor.

In the NPC DAB converter, current flows through the diode, causing the voltage to level, and thus the waveform of the voltage across the inductor. By adjusting the waveform of this voltage, the waveform of the current can be made close to the sinusoidal form. However, there is room for increasing the power conversion efficiency by reducing the peak value and the root mean square of the current according to the switching pattern for voltage control.

According to one aspect, a method for controlling a voltage of a multi-level converter including a NPC topology and a secondary circuit including a full bridge includes controlling the voltage of the primary side in a rising period of the primary side voltage, Level in accordance with a first switching pattern, and controlling the plurality of switches in accordance with a second switching pattern in a falling period of a primary side voltage, wherein the first switching Pattern and the second switching pattern are set such that the voltage waveform of the rising section and the voltage waveform of the falling section do not have symmetry with each other.

In one embodiment, the first switching pattern is set to control the plurality of switches to have a maximum voltage at a point where the voltage of the rising section transitions to a positive voltage.

In one embodiment, the second switching pattern is set to control the plurality of switches to have a lowest voltage at a point where the voltage of the falling period transitions to a negative voltage.

In one embodiment, the primary side circuit includes a first leg and a second leg, wherein the first leg includes a first switch Sa1, a second switch Sa2, a third switch Sb1, And a fourth switch Sb2, and the second leg includes a fifth switch Sa3, a sixth switch Sa4, a seventh switch Sb3, and an eighth switch Sb4.

In one embodiment, the first switch Sa1, the fifth switch Sa3, the second switch Sa2, the sixth switch Sa4, the third switch Sb1, and the seventh switch Sb3 ), And the fourth switch (Sb2) and the eighth switch (Sb4) are complementarily switched with each other.

In one embodiment, the voltage control method of the multi-level converter further comprises the step of controlling the secondary side voltage such that the secondary side voltage has a phase difference with the primary side voltage.

In one embodiment, the secondary side circuit includes a ninth switch S1, a tenth switch S2, an eleventh switch S3 and a twelfth switch S4 for controlling the secondary side voltage .

In an embodiment, the ninth switch S1 and the tenth switch S2, and the eleventh switch S3 and the twelfth switch S4 are complementarily switched with each other.

In one embodiment, the first switching pattern and the second switching pattern have a power transfer formula

에 기초하여 결정되고, 여기서, V_p 는 1차 측 전압, V_s 는 2차 측 전압, Φ는 1차 측 전압 및 2차 측 전압 간의 위상 차, α는 제1 위상 지연, β는 제2 위상 지연을 나타낸다.

Where V _p is the primary side voltage, V _s is the secondary side voltage,? Is the phase difference between the primary side voltage and the secondary side voltage,? Is the first phase delay,? Is the second phase delay, Phase delay.

According to another aspect, a multi-level converter includes a primary circuit including an NPC topology with a plurality of switches for multi-level control of the primary side voltage, a secondary circuit including a full bridge, And control means for controlling said plurality of switches in accordance with a first switching pattern in a rising period of the side voltage and controlling said plurality of switches in accordance with a second switching pattern in a falling period of the primary side voltage, The switching pattern and the second switching pattern are set such that the voltage waveform of the rising section and the voltage waveform of the falling section do not have symmetry with each other.

In one embodiment, the first switching pattern is set to control the plurality of switches to have a maximum voltage at a point where the voltage of the rising section transitions to a positive voltage.

In one embodiment, the second switching pattern is set to control the plurality of switches to have a lowest voltage at a point where the voltage of the falling period transitions to a negative voltage.

In one embodiment, the primary side circuit includes a first leg and a second leg, wherein the first leg includes a first switch Sa1, a second switch Sa2, a third switch Sb1, And a fourth switch Sb2, and the second leg includes a fifth switch Sa3, a sixth switch Sa4, a seventh switch Sb3, and an eighth switch Sb4.

In one embodiment, the first switch Sa1, the fifth switch Sa3, the second switch Sa2, the sixth switch Sa4, the third switch Sb1, and the seventh switch Sb3 ), And the fourth switch (Sb2) and the eighth switch (Sb4) are complementarily switched with each other.

In one embodiment, the control means controls the secondary side voltage such that the secondary side voltage has a phase difference from the primary side voltage.

In one embodiment, the secondary side circuit includes a ninth switch S1, a tenth switch S2, an eleventh switch S3 and a twelfth switch S4 for controlling the secondary side voltage .

In an embodiment, the ninth switch S1 and the tenth switch S2, and the eleventh switch S3 and the twelfth switch S4 are complementarily switched with each other.

In one embodiment, the first switching pattern and the second switching pattern have a power transfer formula

에 기초하여 결정되고, 여기서, V_p 는 1차 측 전압, V_s 는 2차 측 전압, Φ는 1차 측 전압 및 2차 측 전압 간의 위상 차, α는 제1 위상 지연, β는 제2 위상 지연을 나타낸다.

Where V _p is the primary side voltage, V _s is the secondary side voltage,? Is the phase difference between the primary side voltage and the secondary side voltage,? Is the first phase delay,? Is the second phase delay, Phase delay.

1 is an exemplary illustration of a portion of a multilevel converter in accordance with one embodiment.
2 is a diagram for explaining a voltage control method of a multi-level converter according to an embodiment.
3 is a view for explaining a voltage control method of a multi-level converter according to an embodiment.
FIG. 4 is a view showing a voltage waveform formed by a voltage control method of a multi-level converter according to an embodiment.
FIG. 5 is a view showing a waveform of a current formed by a voltage control method of a multi-level converter according to an embodiment.
FIG. 6 is a view showing a voltage waveform formed by the voltage control method of the multi-level converter according to the embodiment.
FIG. 7 is a view showing a waveform of a current formed by a voltage control method of a multi-level converter according to an embodiment.

Specific structural or functional descriptions of embodiments are set forth for illustration purposes only and may be embodied with various changes and modifications. Accordingly, the embodiments are not intended to be limited to the specific forms disclosed, and the scope of the disclosure includes changes, equivalents, or alternatives included in the technical idea.

The terms first or second, etc. may be used to describe various elements, but such terms should be interpreted solely for the purpose of distinguishing one element from another. For example, the first component may be referred to as a second component, and similarly, the second component may also be referred to as a first component.

It is to be understood that when an element is referred to as being "connected" to another element, it may be directly connected or connected to the other element, although other elements may be present in between.

The singular expressions include plural expressions unless the context clearly dictates otherwise. In this specification, the terms "comprises ", or" having ", and the like, are used to specify one or more of the described features, numbers, steps, operations, elements, But do not preclude the presence or addition of steps, operations, elements, parts, or combinations thereof.

Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art. Terms such as those defined in commonly used dictionaries are to be interpreted as having a meaning consistent with the meaning of the context in the relevant art and, unless explicitly defined herein, are to be interpreted as ideal or overly formal Do not.

Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. However, the scope of the rights is not limited or limited by these embodiments. Like reference symbols in the drawings denote like elements.

1 is an exemplary illustration of a portion of a multilevel converter in accordance with one embodiment. As shown in FIG. 1, the multi-level converter according to an embodiment includes an NPC topology on the primary side and a full bridge on the secondary side, respectively.

In one embodiment, the primary side circuit includes two legs. A voltage of three levels can be formed in each leg, and a voltage of five levels can be formed by combining two legs. For example, the first leg may include a first switch Sa1, a second switch Sa2, a third switch Sb1, and a fourth switch Sb2, and the second leg may include a fifth switch Sa3 , A sixth switch Sa4, a seventh switch Sb3, and an eighth switch Sb4.

In one embodiment, the secondary circuit may have a full bridge configuration. The voltage across the transformer can be controlled at two levels and the energy between the primary and secondary sides can be transferred using the phase difference. For example, the secondary side circuit may include a ninth switch S1, a tenth switch S2, an eleventh switch S3, and a twelfth switch S4.

When using a conventional symmetrical switching scheme, a large amount of energy that can be delivered when considering the waveform of the inductor current but can not actually be delivered may remain. In this regard, it is necessary to propose an optimized operation method by analysis of energy loss and mathematical analysis through analysis of relation with inductor current according to switching pattern of multilevel converter.

In particular, according to one embodiment, the peak value and the effective value of the inductor current can be reduced through a new pattern voltage control method of asymmetrically transforming the primary voltage waveform, and a relatively larger amount of energy can be transmitted .

2 is a diagram for explaining a voltage control method of a multi-level converter according to an embodiment. 2 may be, for example, a voltage control method for operating the multilevel converter shown in FIG.

In the example shown, the primary side voltage V _p and the secondary side voltage V _s are controlled to have a phase difference by? For energy transfer. Further, by adjusting? And? Corresponding to the delays between the individual switches, the voltage of the second level or the third level can be made into five levels as can be seen from V _p in FIG.

In the control system of FIG. 2, the primary voltage V _p may have a symmetrical waveform in the voltage rising period and the voltage falling period, and the inductor current I around the reference time point is folded back and forth depending on? And? .

If the peak value of the current according to the symmetrical switching pattern is formulated, it can be expressed by the following Equation 1.

Here,? Represents the phase difference between V _p and V _s . The power transfer formula according to the symmetric switching pattern can be expressed by Equation (2) below.

Where alpha represents a first phase delay and beta represents a second phase delay. When the influence of? And? On the output power P _o is reflected according to Equation (2), the value of P _o becomes smaller and the inductance L decreases. In the symmetrical switching pattern, the peak value of the current becomes larger as shown in Equation (1) due to the reduced inductance.

3 is a view for explaining a voltage control method of a multi-level converter according to an embodiment. 3 may be, for example, a voltage control method for operating the multi-level converter shown in Fig.

In the illustrated example, it can be seen that, unlike the control scheme of FIG. 2, the primary voltage V _p has an asymmetric waveform in the voltage rising period and the voltage falling period. Specifically, the plurality of switches Sa1, Sa2, Sb1, and Sb2 constituting the primary-side circuit can be controlled to have the maximum voltage at the point where the voltage of the rising section transitions to the positive voltage, and the voltage of the falling section It can be controlled to have the lowest voltage at the point where it transitions to the negative voltage.

In the case of the plurality of switches Sa3, Sa4, Sb3 and Sb4 not shown in Fig. 3, they can be switched complementarily with corresponding switches. For example, the first switch Sa1, the fifth switch Sa3, the second switch Sa2 and the sixth switch Sa4, the third switch Sb1 and the seventh switch Sb3, And the fourth switch Sb2 and the eighth switch Sb4 may be complementarily switched with each other.

Using this asymmetrical switching pattern, the amount of energy transferred can be optimized by varying the peak value and the effective value of the inductor current.

If the peak value of the current according to the symmetrical switching pattern is formulated, it can be expressed as Equation (3) below.

Here,? Represents the phase difference between V _p and V _s . The power transfer formula according to the asymmetric switching pattern can be expressed by Equation (4) below.

Where alpha represents a first phase delay and beta represents a second phase delay. As can be seen from the above equation 3, and 4, the output power P _o value is small it is possible to suppress the peak increase in current in the form of an α and β of the inductance L is reduced, even if the reduced inductance compensation effect.

As a result, if the peak value and the effective value of the current are reduced through the asymmetric switching pattern, the energy conversion efficiency can be increased by minimizing the conduction loss.

4 to 7 are waveforms of voltage and current formed by the voltage control method of the multi-level converter according to the embodiment. 4 to 7 correspond to the results of comparing the performance of the symmetric switching pattern and the asymmetric switching pattern through simulation. In order to compare the performance by simulations, α and β are fixed at 0.056 π (10 °) and 0.194 π (35 °), respectively. At 3.8 kW, the primary side voltage is 1500 V and the secondary side voltage is 380 V .

FIG. 4 shows waveforms of the primary side voltage 410 and the secondary side voltage 420 when the symmetrical switching pattern is used, and FIG. 5 shows waveforms of the inductor current 510 when the symmetrical switching pattern is used . 6 shows the waveforms of the primary side voltage 610 and the secondary side voltage 620 when the asymmetrical switching pattern is used, and FIG. 7 shows the waveforms of the inductor current 710 when the symmetrical switching pattern is used. Wave form.

As can be readily seen from the figure, the primary side voltage 410 of FIG. 4 is symmetrical with the rising and falling periods in the cycle, but the primary side voltage 610 of FIG. And the falling sections do not have symmetry with each other.

When the asymmetrical switching pattern is used, the effective value of the current is reduced by about 0.4 A compared with the current value of 3.93 A in the case of using the symmetrical switching pattern of 3.51 A. Also, it can be seen that the THD is 14% when the asymmetric switching pattern is used, which is about 2% higher than 11.7% when the symmetrical switching pattern is used.

As described above, since the effective value of the inductor current can be reduced through the asymmetrical switching pattern, the conduction loss can be minimized and the energy conversion efficiency can be improved.

The embodiments described above may be implemented in hardware components, software components, and / or a combination of hardware components and software components. For example, the devices, methods, and components described in the embodiments may be implemented within a computer system, such as, for example, a processor, a controller, an arithmetic logic unit (ALU), a digital signal processor, such as an array, a programmable logic unit (PLU), a microprocessor, or any other device capable of executing and responding to instructions. The processing device may execute an operating system (OS) and one or more software applications running on the operating system. The processing device may also access, store, manipulate, process, and generate data in response to execution of the software. For ease of understanding, the processing apparatus may be described as being used singly, but those skilled in the art will recognize that the processing apparatus may have a plurality of processing elements and / As shown in FIG. For example, the processing unit may comprise a plurality of processors or one processor and one controller. Other processing configurations are also possible, such as a parallel processor.

The software may include a computer program, code, instructions, or a combination of one or more of the foregoing, and may be configured to configure the processing device to operate as desired or to process it collectively or collectively Device can be commanded. The software and / or data may be in the form of any type of machine, component, physical device, virtual equipment, computer storage media, or device , Or may be embodyed temporarily. The software may be distributed over a networked computer system and stored or executed in a distributed manner. The software and data may be stored on one or more computer readable recording media.

The method according to an embodiment may be implemented in the form of a program command that can be executed through various computer means and recorded in a computer-readable medium. The computer-readable medium may include program instructions, data files, data structures, and the like, alone or in combination. The program instructions to be recorded on the medium may be those specially designed and configured for the embodiments or may be available to those skilled in the art of computer software. Examples of computer-readable media include magnetic media such as hard disks, floppy disks and magnetic tape; optical media such as CD-ROMs and DVDs; magnetic media such as floppy disks; Magneto-optical media, and hardware devices specifically configured to store and execute program instructions such as ROM, RAM, flash memory, and the like. Examples of program instructions include machine language code such as those produced by a compiler, as well as high-level language code that can be executed by a computer using an interpreter or the like. The hardware devices described above may be configured to operate as one or more software modules to perform the operations of the embodiments, and vice versa.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. For example, it is to be understood that the techniques described may be performed in a different order than the described methods, and / or that components of the described systems, structures, devices, circuits, Lt; / RTI > or equivalents, even if it is replaced or replaced. Therefore, other implementations, other embodiments, and equivalents to the claims are also within the scope of the following claims.

Claims (19)

A method of controlling a voltage of a multi-level converter including a NPC topology in a primary side circuit and a full bridge in a secondary side circuit,
Controlling a plurality of switches for controlling the primary side voltage to a multilevel in a rising section of the primary side voltage according to a first switching pattern; And
Controlling the plurality of switches according to a second switching pattern in a falling period of the primary side voltage
Lt; / RTI >
Wherein the first switching pattern and the second switching pattern are set such that a voltage waveform of the rising section and a voltage waveform of the falling section do not have symmetry with each other,
A method for controlling the voltage of a multilevel converter. The method according to claim 1,
Wherein the first switching pattern is set to control the plurality of switches such that an output voltage has a maximum voltage at a point where the voltage of the rising section transitions to a positive voltage,
A method for controlling the voltage of a multilevel converter. The method according to claim 1,
Wherein the second switching pattern is set to control the plurality of switches such that an output voltage has a lowest voltage at a point where the voltage of the falling period transitions to a negative voltage,
A method for controlling the voltage of a multilevel converter. The method according to claim 1,
Wherein the primary side circuit includes a first leg and a second leg,
The first leg includes a first switch Sa1, a second switch Sa2, a third switch Sb1, and a fourth switch Sb2,
The second leg includes a fifth switch Sa3, a sixth switch Sa4, a seventh switch Sb3, and an eighth switch Sb4.
A method for controlling the voltage of a multilevel converter. 5. The method of claim 4,
Wherein the first switch Sa1 and the fifth switch Sa3, the second switch Sa2 and the sixth switch Sa4, the third switch Sb1 and the seventh switch Sb3, 4 switch Sb2 and the eighth switch Sb4 are complementarily switched with each other,
A method for controlling the voltage of a multilevel converter. The method according to claim 1,
Controlling the secondary side voltage so that the secondary side voltage has a phase difference from the primary side voltage
≪ / RTI >
A method for controlling the voltage of a multilevel converter. The method according to claim 6,
The secondary side circuit includes a ninth switch S1, a tenth switch S2, an eleventh switch S3 and a twelfth switch S4 for controlling the secondary side voltage.
A method for controlling the voltage of a multilevel converter. 8. The method of claim 7,
The ninth switch S1 and the tenth switch S2 and the eleventh switch S3 and the twelfth switch S4 are complementarily switched to each other,
A method for controlling the voltage of a multilevel converter. The method according to claim 1,
Wherein the first switching pattern and the second switching pattern have a power transfer formula

Lt; / RTI >
Where V _p is the primary side voltage, V _s is the secondary side voltage,? Is the phase difference between the primary side voltage and the secondary side voltage,? Is the first phase delay,? Is the second phase delay,
A method for controlling the voltage of a multilevel converter. A computer-readable medium having embodied thereon a program for executing a method of controlling a voltage of a multi-level converter including a NPC topology and a secondary circuit including a full bridge, the program comprising:
Controlling a plurality of switches for controlling the primary side voltage to a multilevel in a rising section of the primary side voltage according to a first switching pattern; And
Controlling the plurality of switches according to a second switching pattern in a falling period of the primary side voltage
Lt; / RTI >
Wherein the first switching pattern and the second switching pattern are set such that a voltage waveform of the rising section and a voltage waveform of the falling section do not have symmetry with each other,
A computer readable recording medium. In a multilevel converter,
A primary side circuit comprising an NPC topology with a plurality of switches for controlling the primary side voltage to a multilevel;
A secondary side circuit including a full bridge; And
A control means for controlling said plurality of switches in accordance with a first switching pattern in a rising section of a primary side voltage and controlling said plurality of switches in accordance with a second switching pattern in a falling period of a primary side voltage,
/ RTI >
Wherein the first switching pattern and the second switching pattern are set such that a voltage waveform of the rising section and a voltage waveform of the falling section do not have symmetry with each other,
Multilevel converters. 12. The method of claim 11,
Wherein the first switching pattern is set to control the plurality of switches such that an output voltage has a maximum voltage at a point where the voltage of the rising section transitions to a positive voltage,
Multilevel converters. 12. The method of claim 11,
Wherein the second switching pattern is set to control the plurality of switches such that an output voltage has a lowest voltage at a point where the voltage of the falling period transitions to a negative voltage,
Multilevel converters. 12. The method of claim 11,
Wherein the primary side circuit includes a first leg and a second leg,
The first leg includes a first switch Sa1, a second switch Sa2, a third switch Sb1, and a fourth switch Sb2,
The second leg includes a fifth switch Sa3, a sixth switch Sa4, a seventh switch Sb3, and an eighth switch Sb4.
Multilevel converters. 15. The method of claim 14,
Wherein the first switch Sa1 and the fifth switch Sa3, the second switch Sa2 and the sixth switch Sa4, the third switch Sb1 and the seventh switch Sb3, 4 switch Sb2 and the eighth switch Sb4 are complementarily switched with each other,
Multilevel converters. 12. The method of claim 11,
Wherein the control means controls the secondary side voltage so that the secondary side voltage has a phase difference from the primary side voltage,
Multilevel converters. 17. The method of claim 16,
The secondary side circuit includes a ninth switch S1, a tenth switch S2, an eleventh switch S3 and a twelfth switch S4 for controlling the secondary side voltage.
Multilevel converters. 18. The method of claim 17,
The ninth switch S1 and the tenth switch S2 and the eleventh switch S3 and the twelfth switch S4 are complementarily switched to each other,
Multilevel converters. 12. The method of claim 11,
Wherein the first switching pattern and the second switching pattern have a power transfer formula

Lt; / RTI >
Where V _p is the primary side voltage, V _s is the secondary side voltage,? Is the phase difference between the primary side voltage and the secondary side voltage,? Is the first phase delay,? Is the second phase delay,
Multilevel converters.

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