KR101881329B1 - Data Buffer Capable of Compensating Data Skew on Common Data Bus and Buffering Method thereof - Google Patents

Abstract

Disclosed are a data buffer compensating a data skew of a common data bus and a data buffering method thereof. The data buffer of the present invention is connected to a plurality of data output ends through a common data bus to buffer output data of one among the plurality of data output ends, and can be used in a data line of a memory device such as static RAMs. The data buffer of the present invention buffers data loaded in the common data bus by delaying the same as much as necessary, in spite of data skew generated when using the common data bus.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data buffer for compensating data skew of a common data bus,

The present invention relates to a data buffer connected to a plurality of data output terminals through a common data bus and buffering output data of one of the plurality of data output terminals, and is capable of compensating a data skew in a common data bus, And a method of buffering the data.

The integrated circuits including the data bus circuit have more and more input (In) and output (Out) ends, thereby having more input and output data buses and a burden of increasing the size of the chip. One of the ways to solve this problem is the 'common data bus'. For example, Figure 1 is an example of a conventional semiconductor memory circuit having a common data bus. Referring to FIG. 1, a plurality of output units 31, 33, and 35 and a single output data buffer 51 or 53 are connected to one common data bus 11 or 13 . Since each of the output units 31, 33, and 35 has M output stages, the circuit of FIG. 1 includes all the M common data buses 11 and 13 and M output data buffers 51 and 53 .

For example, the output units 31, 33, and 35 may be a semiconductor memory cell array (cell array) block. Cell data extracted from the cell array is decoded through a column decoder and amplified to a Cmos level in a sense amplifier. The common data buses 11 and 13 corresponding to the output data lines are capable of efficiently sending data of the cells to the output data buffers 51 and 53 while introducing the concept of a block when designing a large- . The output data buffers 51 and 53 buffer the data transmitted from the output units 31, 33, and 35 and finally output the buffered data.

Even if the common data bus structure is adopted, the number of output sections (n) connected to one data bus 11 can reach several tens, and the length of the common data bus 11 can be extended to several thousand .mu.m or more. Therefore, even when a common data bus structure is employed, metal loading and gate loading can not be avoided due to a long data bus and a number of output units connected to the data bus. One way to solve this problem is to arrange the output driver at the connection portion between the output units 31, 33, and 35 and the common data bus 11, for example. The output driver of FIG. 1 is formed of a series connection of a NAND gate and an inverter

In addition, the common data bus architecture causes various problems as buses are shared. One of the important problems is data skew. The data skew means that a parallax occurs between data output from each of the output units 31, 33, and 35 based on a reference timing point (for example, activation of a control signal) in the design. Figure 2 shows a timing diagram according to skew that can occur in Figure 1. The timing at which the data output from the first output section 31 disposed the farthest from the data buffer 51 reaches the data buffer 51 via the common data bus 11 on the basis of the activation of the control signal OEn And the timing at which the data output from the n-th output section 55 relatively close to the data buffer 51 reaches the data buffer 51 via the common data bus 11 can be changed. For this reason, as shown in FIGS. 2A and 2B, the timing at which the data DQb of the output units 31, 33, and 35 arrive at the data buffer 51 differs with respect to the control signal OEn .

2 (a) shows a normal operation, in which the control signal OEn is activated to a logical low while data is being loaded on the common data bus 11. In FIG. The data buffer 51 finally outputs the output signal Q buffered by the data loaded on the common data bus 11 in conjunction with the activation of the control signal OEn at time ta.

The data of FIG. 2 (b) arrives too early than the time tc at which the control signal OEn is activated to the logic low, and has already disappeared at time tb. The data buffer 51 does not change the output signal Q because the control signal OEn is activated at time tc but there is no data loaded on the common data bus 11. [ In FIG. 2 (b), the data buffer 51 fails to output the data loaded on the common data bus 11.

As described above, when data skew occurs when a plurality of output units load a signal on one common data bus, signal transmission may be missed.

[Related Technical Literature]

1. Korean Patent Publication No. 2310-0127276 (entitled Improved Bit Line Tracking in High Performance Memory Compilers)

An object of the present invention is to provide a data buffer, which is connected to a plurality of data output terminals through a common data bus and buffers output data of one of the plurality of data output terminals, and which compensates data skew in a common data bus, A data buffer for preventing an error and a method of buffering the data.

In order to achieve the above object, a data buffer according to the present invention buffers a first data signal (DQb), which is triggered by a negative edge on which a control signal (OEn) is activated, do. The data buffer of the present invention includes a delay data latch unit and a buffer unit.

The delay data latch unit receives the first data signal DQb and the control signal OEn and outputs a second data signal DQDb. At this time, the second data signal DQDb is transited from a negative edge where the first data signal DQb starts to be loaded to a logic low, and the active period d2 of the control signal OEn is shifted to the end A signal having a gate delay of a predetermined time from the first data signal DQb as a signal to be restored from a positive edge to a logic high again.

The buffer unit is triggered by the control signal OEn during the active period d3 of the second data signal DQDb to buffer the first data signal DQb.

According to the embodiment, the buffer unit includes a fifth inverter U71, a first buffer unit, a sixth inverter U72, a second buffer unit, and a seventh inverter U73.

The fifth inverter (U71) inverts the first data signal (DQb) to output the third node signal (Vn3). The fifth inverter (U71) is turned on while the second data signal (DQDb) And transfers the first data signal DQb to the third node n3 during the gate delay.

The first buffer unit includes an eighth inverter U74 provided between the third node n3 and the fourth node n4 to output the fourth node signal Vn4 by inverting the third node signal Vn3, And a ninth inverter (U75) operating when the second data signal (DQDb) is logic low to feed back the fourth node signal (Vn4) to the third node (n3), wherein the third node signal ).

The sixth inverter U72 is provided between the fourth node n4 and the fifth node n5 and outputs the fifth node signal Vn5 by inverting the fourth node signal Vn4, ≪ / RTI > is logic low.

The second buffer unit includes a tenth inverter (U76) provided between the fifth node (n5) and the sixth node (n6) and inverting the fifth node signal (Vn5) to output a sixth node signal (Vn6) And an eleventh inverter (U77) operating when the control signal (OEn) is at a logic high to feed back the sixth node signal (Vn6) to the fifth node (n5), wherein the fifth node signal Invert latch.

The seventh inverter (U73) inverts the fifth node signal (Vn5), which is the output of the second buffer unit, and outputs the final signal (Q).

According to another embodiment, the delay data latch unit is provided between the first data signal DQb and the second node n2 and receives the first data signal DQb and the control signal OEn A latch for latching and outputting a second node signal Vn2; And an active period which is provided between the second node (n2) and the second data signal (DQDb) and overlaps an active period of the second node signal (Vn2) with an active period of the control signal (OEn) And a signal combiner for outputting the second data signal DQDb.

The second node signal Vn2 has a logic high value if the first data signal DQb and the control signal OEn are both logic low and the second node signal Vn2 has a logic high value when the first data signal DQb and the control signal OEn are logic low, (3) if the first data signal (DQb) is logic high and the control signal (OEn) is a logic low, the logic low value is set to a logic high value if the control signal (OEn) is logic low and the control signal (4) if the first data signal DQb and the control signal OEn are both logic high, the second node signal Vn2 in the previous state is held. For example, the latch unit may be an SR latch using two NAND gates U5 and U7.

According to another embodiment, the latch unit may receive a reset signal Reset and reset the second node signal Vn2 to a logic low when the reset signal becomes a logic low.

According to still another embodiment, the delay data latch unit may further include a first inverter U1 and a second inverter U2 that buffer the first data signal DQb and input the buffered data to the latch unit.

The signal synthesizer may further include a third inverter U9 for inverting the second node signal Vn2 and a third inverter U9 for inverting the output of the third inverter U9 and the control signal OEn, And a fourth inverter U13 for inverting the output of the first NAND gate U11 and outputting the second data signal DQDb.

The present invention also relates to a method of buffering the data buffer. The buffering method of the present invention includes the steps of receiving a first data signal and a control signal and outputting a second data signal and outputting the control signal OEn during an active period d3 of the second data signal DQDb, And buffering the first data signal DQb.

The data buffer of the present invention is connected to a plurality of data output terminals through a common data bus and can buffer output data of one of the plurality of data output terminals. For example, a static RAM and a memory such as a DRAM Can be used in the data line of the device.

The data buffer of the present invention can buffer the data loaded on the common data bus by delaying it as necessary in spite of the data skew that may occur according to the use of the common data bus.

1 shows an example of a conventional memory circuit having a common data bus,
Fig. 2 is a timing chart when data skew occurs on the common data bus of Fig. 1; Fig.
3 is a block diagram of a data buffer of the present invention;
FIG. 4 is a circuit diagram according to an embodiment of the delay data latch unit of FIG. 3;
FIG. 5 is a timing chart provided in the operation description of the delay data latch unit of FIG. 4,
6 is a circuit diagram of a delay data latch unit according to another embodiment of the present invention,
7 is a circuit diagram according to an example of a buffer unit included in the data buffer of the present invention, and
8 is a timing chart provided in an operation description of the buffer unit in Fig.

3, the data buffer 300 of the present invention includes a delay data latch unit 310 and a buffer unit 330 to compensate data skew generated in the common data bus 10, It is possible to buffer the data signal DQb loaded on the data bus 10 and output the final signal Q. Hereinafter, for convenience of explanation, the data signal DQb loaded on the common data bus 10 is referred to as a first data signal DQb and the second data DQb, which is the output of the delay data latch unit 310 Signal DQDb.

Delay data latch section

The delay data latch unit 310 receives the first data signal DQb and the control signal OEn loaded on the common data bus 10 and outputs the first data signal DQb and the second data signal DQb, (Low, Logical 0) at the edge of the control signal OEn and (2) at the positive edge where the active period d2 of the control signal OEn ends, And outputs the second data signal DQDb. Therefore, the active period d3 of the second data signal DQDb becomes longer than the first data signal DQb. The delay data latch unit 400 of FIG. 4 is an example of the delay data latch unit 310 of FIG.

The delay data latch unit 400 of FIG. 4 includes a latch unit L1 and a signal combiner L2. The latch unit L1 receives the first data signal DQb and the control signal OEn and latches the first data signal DQb to output the second node signal Vn2. The latch unit L1 latches the first data signal DQb, The second node signal Vn2 maintains the latch state until the activation time of the control signal OEn, unless the control signal OEn is activated while the control signal OEn is being loaded. The signal synthesizing unit L2 superposes the active period d1 of the second node signal Vn2 and the active period d2 of the control signal OEn and outputs the second data signal DQDb.

4 shows an example in which the first inverter U1 and the second inverter U3 that serially connect the first node n1 and the first data signal DQb, which are the input terminals of the latch unit L1, More examples include. The first inverter U1 and the second inverter U3 output the first node signal Vn1 buffered by the input first data signal DQb, It is not a configuration. Although the first node signal Vn1 and the first data signal DQb have a delay corresponding to two gates, they are not important in the description of the present invention. Therefore, the first node signal Vn1 is described separately from the first data signal DQb in the following description. However, if necessary, the first node signal Vn1 may be divided into the first data signal Dnb and the second data signal Dbb without considering the delay caused by the first inverter U1 and the second inverter U3, The one node signal Vn1 and the first data signal DQb may be described as being the same.

The signal synthesizing unit L2 includes a third inverter U9 for inverting the second node signal Vn2 and a third inverter U9 for negatively ANDing the output of the third inverter U9 and the control signal OEn A first NAND gate U11 and a fourth inverter U13 for inverting the output of the first NAND gate U11 and outputting the second data signal DQDb.

The latch unit L1 latches the first node signal Vn1 as a latch operating in an active low state. For normal operation, the second node signal Vn2, which is the output of the latch section L1, is reset to a logic low at the start of operation and remains logic low even when the first data signal DQb is not loaded .

In conjunction with the first data signal DQb being loaded on the common data bus 10, the second node signal Vn2, which is the output of the latch unit L1, is activated to logic high. The latch unit L1 maintains the second node signal Vn2 at a logical high while at least the first node signal Vn1 is activated at a logic low and particularly the skew occurs to activate the first data signal DQb The second node signal Vn2 is held at logic high until the control signal OEn is activated even if the control signal OEn is not activated for a while.

The latch unit L1 may be any unit as long as it operates as shown in Table 1 below. 4 is implemented as an SR latch using two NAND gates, that is, a second NAND gate U5 and a third NAND gate U7. However, the latch portion L1 of FIG. 4 is constructed by using a NOR gate, You may.

Vn1 (t) OEn Vn2 (t + 1) Remarks 0 0 One 0 One One set One 0 0 reset One One Vn2 (t) Retain previous signal

Fig. 5 is a timing diagram for explaining the operation of the circuit of Fig. 4, wherein (a) shows a case where the control signal OEn is activated while the first data signal DQb is activated, And the control signal OEn is not activated while the signal DQb is being activated.

5A, the second node signal Vn2 transits to a logic high when the first node signal Vn1 becomes a logic low, and then the control signal OEn and the first node signal Vn1 become logic high. The control signal OEn maintains a logic low and restores to a logic low again at time t12 when only the first node signal Vn1 returns to a logic high. In summary, when the control signal OEn is activated while the first data signal DQb is activated, the latch unit L1 outputs the second node signal Vn2 of the inverted version of the first node signal Vn1 do.

In FIG. 5B, the second node signal Vn2 is different from FIG. 5A. When the first node signal Vn1 becomes logic low, the second node signal Vn2 transitions to a logic high. Even if the first node signal Vn1 returns to the logic high again at t21, the control signal OEn maintains the logic high, so that the latch unit L1 latches the second node signal Vn2 as logic high according to Table 1 . The latch portion L1 resets the second node signal Vn2 in accordance with the negative edge of the control signal OEn only when the control signal OEn is activated at a logic low at t22, ≪ / RTI > returns to a logic low. Therefore, even if the control signal OEn is not activated during the active period of the first data signal DQb, the latch section L1 maintains the active period d1 until the control signal OEn starts at ts And outputs the second node signal Vn2. At this time, due to the gate delay, the active period d1 of the second node signal Vn2 is finely overlapped with the active period d2 of the control signal OEn.

5A and 5B, the rising edge of the second node signal Vn2 is shifted from the falling edge ts of the first data signal DQb to the falling edge ts of the first data signal DQb. There is a gate delay according to the inverter U1, the second inverter U3 and the latch unit L1. This delay enables the operation of the buffer unit 330.

The third inverter U9 and the first NAND gate U11 of the signal combining unit L2 combine the active period d1 of the second node signal Vn2 and the active period d2 of the control signal OEn. The second node signal Vn2 and the control signal OEn are activated at a logic low while the control signal OEn is maintained at a logic high while the second node signal Vn2 is kept at a logic low and activated to a logic high, The activation section of the latch section L1 is designed to be partially overlapped by the latch section L1 so that it can be combined into one signal by the logic circuit.

4, the first NAND gate U11 is used, the second node signal Vn2 is inverted by using the third inverter U9, and then a negative-AND operation is performed with the control signal OEn. do. According to the logic structure, even if the control signal OEn is inverted and then the second node signal Vn2 is negatively-ORed, the same result can be obtained. The second data signal DQDb is obtained by inverting the output of the first NAND gate U11 again using the third inverter U9.

5A and 5B, like the second node signal Vn2, the time point ts1 at which the second data signal DQDb transits to logic low is the time when the first data signal DQb is loaded There is a constant gate delay from the time point ts. The delay between the second data signal DQDb and the first data signal DQb enables the buffer unit 330 to operate.

6 shows a delay data latch unit 600 according to another embodiment of the present invention. In the delay data latch unit 600 of FIG. 6, the latch unit L3 is reset by the reset signal Reset to reset the second node signal Vn2 to a logic low. As described above, the second node signal Vn2 must maintain a logic low before the first data signal DQb is loaded onto the common data bus 10. [ Accordingly, the latch unit L3 of FIG. 6 forcibly resets the second node signal Vn2 to a logic low when the reset signal becomes logic low, thereby preventing the whole of the delay data latch unit 600 from malfunctioning .

The buffer unit

The buffer unit 330 receives the first data signal DQb loaded on the common data bus 10 and receives the first data signal DQb and the second data signal DQb using the second data signal DQDb and the control signal OEn, ). FIG. 7 shows an example of the buffer unit 330. FIG.

7, the buffer unit 700 includes a first buffer unit L4 for latching the first data signal DQb, and a second buffer unit L4 for latching the output of the first buffer unit L4 again And a first transfer gate controlled by the second data signal DQDb to transfer the first data signal DQb to the first buffer L4 A sixth inverter U72 which operates as a second transfer gate controlled by the control signal OEn and transfers the output of the first buffer L4 to the second buffer L5, And a seventh inverter U73 for inverting the output of the second buffer L5 and outputting the final signal Q. The buffer unit 700 further includes a twelfth inverter U78 for generating a signal DQD by inverting the second data signal DQDb and a thirteenth inverter U78 for generating a signal OE in which the control signal OEn is inverted, And inverter U79.

The fifth inverter U71 acts as a transfer gate by being operated or controlled by the second data signal DQDb. When the second data signal DQDb is logic high, the fifth inverter U71 operates to output the third node signal Vn3 which inverts the first data signal DQb, and the second data signal DQDb When it is a logic low, it is turned off in a high impedance state.

The first buffer unit L4 is provided between the third node n3 and the fourth node n4 and outputs the fourth node signal Vn4, which is the inverted third node signal Vn3, And a ninth inverter U75 operating when the second data signal DQDb is logic low to invert the fourth node signal Vn4 and feed back the third node signal Vn4 to the third node n3.

The sixth inverter U72 is provided between the fourth node n4 and the fifth node n5 and operates as a transfer gate by being controlled by the control signal OEn. When the control signal OEn is logic low, the sixth inverter U72 operates to output the fifth node signal Vn5 which inverts the fourth node signal Vn4, which is the output of the first buffer unit L4, When the control signal OEn becomes logic high, it becomes a high impedance state.

The second buffer unit L5 is provided between the fifth node n5 and the sixth node n6 and outputs a sixth node signal Vn6 by inverting the fifth node signal Vn5 again, And an eleventh inverter U77 which is enabled when the control signal OEn is at logic high to invert the sixth node signal Vn6 and feed back to the fifth node n5.

Operation of the buffer unit (Fig. 8)

First, the fifth inverter U71 operates at a time point ts when the first data signal DQb is activated to transfer the first data signal DQb to the first buffer unit L4, The buffer unit L4 receives the first data signal DQb. the fifth inverter unit U71 is turned off and the first buffer unit L4 latches the first data signal DQb during the active period d3 of the second data signal DQDb from the time ts1 delayed from ts.

When the control signal OEn is activated during the active period d3 of the second data signal DQDb, the sixth inverter U72 operates to output the output of the first buffer L4 to the second buffer L5 And the second buffer unit L5 and the seventh inverter U73 invert the output of the first buffer unit L4 to output the final signal Q. The first buffer L3 continues to latch the first data signal DQb until the control signal OEn is switched to the logic high so that the sixth inverter U72 is turned on when the control signal OEn is switched to logic high, And the second buffer unit L5 latches the output of the first buffer unit L4 as it is.

≪ Operation of the fifth inverter which is the first transfer gate >

First, the second data signal DQDb becomes a logic low at a time point ts1 delayed from the time ts at which the first data signal DQb is activated to several gates. Therefore, when the first data signal DQb is loaded on the common data bus 10, since the second data signal DQDb is still logic high, the fifth inverter U71 is turned on to invert the first data signal DQb And outputs the third node signal Vn3 of logic high. When the second data signal DQDb becomes logic low at time ts1, it is immediately inactivated. The gate delay between ts and ts1 is sufficient time for fifth inverter U71 to operate.

≪ Latch of first buffer part >

The gate delay between ts and ts1 is sufficient time for signal transmission by the fifth inverter U71 and the eighth inverter U74. Accordingly, when the fifth inverter U71 inverts the first data signal DQb and outputs the third node signal Vn3 while the first data signal DQb is activated, Since the inverter U75 is still not operated by the second data signal DQDb which is logic high, the third node signal Vn3 is directly inverted to output the fourth node signal Vn4 which is a logic low.

The fifth inverter U71 is turned off and the ninth inverter U75 is turned on and the feedback is turned on when the second data signal DQDb becomes a logic low at a constant gate delay ts1 from the activation of the first data signal DQb. And latches the fourth node signal Vn4 which is logic low by operation. The fourth node signal Vn4 is a signal that is triggered by the first data signal DQb.

The control signal OEn is normally activated while the first data signal DQb is activated as shown in FIG. 5A or the first data DQb is activated before the control signal OEn is generated due to the skew as shown in FIG. The second data signal DQDb is maintained until the active period d2 of the control signal OEn is ended even if the loading of the signal DQb is ended and therefore the ninth inverter U75 outputs the second data signal DQDb The fourth node signal Vn4 is latched until the active period d3 of the fourth node signal V3 ends.

≪ Transmission of the output of the first buffer unit to the second buffer unit >

The control signal OEn is activated to a logic low while the second data signal DQDb is held and thus the sixth inverter U72 is turned on when the control signal OEn becomes logic low (t11, t22) The fourth node signal Vn5 is inverted by inverting the fourth node signal Vn4 of the logic low latched by the fourth node L4 and inverting the fourth node signal Vn4 to a logic high to output the fifth node signal Vn5 to the second buffer L5 ). The control signal OEn does not activate the control signal OEn when the first data signal DQb is loaded as shown in FIG. And the signal Vn4 is transferred to the second buffer unit L5.

When the control signal OEn becomes logic high again, the sixth inverter U72 turns off and does not operate in a high impedance state.

≪ Buffering of the second buffer part >

Since the eleventh inverter U77 of the second buffer unit L5 does not operate when the control signal OEn is activated to a logic low, the fifth node signal Vn5 transmitted by the sixth inverter U72 is at the tenth Inverted by the inverter U76 and output to the sixth node signal Vn6 of the logic low. This state continues until the eleventh inverter U77 is operated again, that is, when the control signal OEn becomes logic high (tx). The output of the sixth node signal Vn6 is also held at a logic low because the fourth node signal Vn4 keeps the logic low for the active period d2 of the control signal OEn.

At tx, when the control signal OEn becomes logic high, the eleventh inverter U77 latches the sixth node signal Vn6 of the logic low as it forms the feedback path. The sixth node signal Vn6 is inverted again by seventh inverter U73 to output the final signal Q of logic high.

On the other hand, when the first data signal DQb becomes logic high and the control signal OEn also becomes logic high, and the second data signal DQDb becomes logic high again, the fifth inverter U71 is turned on, Inverter U75 is turned off and becomes a high impedance state. Therefore, the first data signal DQb in the logic high state is transferred to the fourth node n4. However, since the sixth inverter U72 is in the turned off state and the eleventh inverter U77 maintains the turn-on state, the fourth node signal Vn4 is not transferred to the second buffer L5.

Even if the first data signal DQb is not loaded onto the common data bus 10 in accordance with the control signal OEn by the buffer unit 700 described above, the buffer unit 700 can output the first data signal DQb Can be buffered. The operation of the buffer unit 700 is possible by keeping the second data signal DQDb at a logic low during the active period d2 of the control signal OEn.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is clearly understood that the same is by way of illustration and example only and is not to be construed as limiting the scope of the invention as defined by the appended claims. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present invention.

Claims (13)

A data buffer for buffering a first data signal DQb triggered by a negative edge on which a control signal OEn is activated and loaded at a logic low on a common data bus,
And the second data signal DQDb receives the first data signal DQb and the control signal OEn and outputs the second data signal DQDb while the first data signal DQb starts to be loaded As a signal that transitions from a negative edge to a logic low and returns to a logic high again from a positive edge where the active period d2 of the control signal OEn ends, A delay data latch unit which is a signal having a gate delay of a predetermined time from the data signal DQb; And
And a buffer unit which is triggered by the control signal (OEn) and buffers the first data signal (DQb) during an active period (d3) of the second data signal (DQDb) (DQb)
The buffer unit includes:
Wherein the first data signal (DQb) is turned on while the second data signal (DQDb) is at a logic high, and the third data signal A fifth inverter (U71) for transferring to the third node (n3) during the gate delay;
An eighth inverter (U74) provided between the third node (n3) and the fourth node (n4) and inverting the third node signal (Vn3) to output a fourth node signal (Vn4) And a ninth inverter (U75) operating when the third node signal (DQDb) is at a logic low to feed back the fourth node signal (Vn4) to the third node (n3) A first buffer unit;
And a fifth node n5 which is provided between the fourth node n4 and the fifth node n5 and inverts the fourth node signal Vn4 to output a fifth node signal Vn5, A sixth inverter U72 turned on;
A tenth inverter (U76) provided between the fifth node (n5) and the sixth node (n6) for inverting the fifth node signal (Vn5) to output a sixth node signal (Vn6) ) For inverting the fifth node signal (Vn5) by an inverter (U77) which operates when the first node signal (Vn5) is at logic high and feeds back the sixth node signal (Vn6) 2 buffer unit; And
And a seventh inverter (U73) for inverting a fifth node signal (Vn5) which is an output of the second buffer unit and outputting a final signal (Q).
delete The method according to claim 1,
Wherein the delay data latch unit comprises:
And a second node signal Vn2 provided between the first data signal DQb and the second node n2 to receive and latch the first data signal DQb and the control signal OEn, A latch portion; And
And an active period which is provided between the second node (n2) and the second data signal (DQDb) and overlaps an active period of the second node signal (Vn2) with an active period of the control signal (OEn) And a signal synthesizer for outputting the second data signal (DQDb)
The second node signal Vn2 has a logical high value if (1) the first data signal DQb and the control signal OEn are both logic low, (2) the first data signal DQb has a logic high value, (3) if said first data signal (DQb) is logic high and said control signal (OEn) is a logic low, said control signal (OEn) has a logic high value if said control signal (4) The data buffer holds the second node signal (Vn2) in the previous state when the first data signal (DQb) and the control signal (OEn) are both logic high.
The method of claim 3,
Wherein the latch unit is an SR latch using two NAND gates (U5, U7).
The method of claim 3,
The latch unit includes:
Receives a reset signal (Reset) and resets the second node signal (Vn2) to a logic low when the reset signal (Reset) becomes a logic low.
The method of claim 3,
Wherein the delay data latch unit comprises:
Further comprising a first inverter (U1) and a second inverter (U2) buffering the first data signal (DQb) and inputting the first data signal (DQb) to the latch unit.
The method of claim 3,
Wherein the signal combining unit comprises:
A third inverter U9 for inverting the second node signal Vn2;
A first NAND gate U11 for negatively ANDing the output of the third inverter U9 and the control signal OEn; And
And a fourth inverter (U13) for inverting an output of the first NAND gate (U11) and outputting the second data signal (DQDb).
A data buffering method for buffering a first data signal (DQb) triggered by a negative edge on which a control signal (OEn) is activated, the first data signal (DQb) being loaded into a logic low on a common data bus,
And outputting the second data signal (DQDb) by receiving the first data signal (DQb) and the control signal (OEn) (the second data signal (DQDb) (DQb) to a logic low at a positive edge where the active period of the control signal (OEn) ends and a gate delay at a predetermined time from the first data signal (DQb) ≪ / RTI > And
And buffering the first data signal (DQb) by being triggered by the control signal (OEn) during an active period (d3) of the second data signal (DQDb) (DQb)
The step of buffering the first data signal (DQb)
The fifth inverter U71 is turned on while inverting the first data signal DQb to output the third node signal Vn3 while the second data signal DQDb is logic high, ) Is turned to a logic low;
The eighth inverter U74 of the first buffer unit provided between the third node n3 and the fourth node n4 inverts the third node signal Vn3 while the second data signal DQDb is logic high, And the ninth inverter U75 outputs the fourth node signal Vn4 to the third node n3 when the second data signal DQDb becomes logic low, Latching the fourth node signal (Vn4);
A sixth inverter U72 provided between the fourth node n4 and the fifth node n5 inverts the fourth node signal Vn4 while the control signal OEn is logic low to generate a fifth node signal Vn5) and turned off when the control signal (OEn) becomes logic high;
The tenth inverter U76 of the second buffer unit provided between the fifth node n5 and the sixth node n6 inverts the fifth node signal Vn5 while the control signal OEn is logic low, The sixth node signal Vn6 is fed back to the fifth node n5 by the eleventh inverter U77 when the control signal OEn becomes logic high, Latching the node signal (Vn6); And
And the seventh inverter (U73) inverts the fifth node signal (Vn5), which is the output of the second buffer unit, to output the final signal (Q).
delete 9. The method of claim 8,
The step of outputting the second data signal (DQDb)
And a latch unit between the first data signal DQb and the second node n2 to receive and latch the first data signal DQb and the control signal OEn to output the second node signal Vn2 A latch step for outputting; And
And outputting the second data signal (DQDb) having an active period in which an active period of the second node signal (Vn2) is overlapped with an active period of the control signal (OEn)
The second node signal Vn2 has a logical high value if (1) the first data signal DQb and the control signal OEn are both logic low, (2) the first data signal DQb has a logic high value, (3) if said first data signal (DQb) is logic high and said control signal (OEn) is a logic low, said control signal (OEn) has a logic high value if said control signal (4) If the first data signal DQb and the control signal OEn are both logic high, the second node signal Vn2 in the previous state is held.
11. The method of claim 10,
Wherein the latching portion of the latching step includes:
And a reset signal Reset to reset the second node signal Vn2 to a logic low when the reset signal becomes a logic low.
11. The method of claim 10,
Wherein the signal synthesis step comprises:
Performing a negative-AND operation between the signal obtained by inverting the second node signal (Vn2) and the control signal (OEn); And
And outputting the second data signal (DQDb) by inverting the result of the negative-AND operation.
11. The method of claim 10,
Further comprising the step of buffering the first data signal (DQb) using the first inverter (U1) and the second inverter (U2) and providing the buffered data to the latching step before the latching step .

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