KR101881143B1 - Clock controlled random password generator for minimizing bit error rate in wireless communication - Google Patents

Abstract

The present invention relates to a clock adjustable random code generator for minimizing bit error in wireless communication. The present invention provides a clock supply apparatus comprising: a clock providing unit (400b) for providing a clock; A first LFSR 100c outputting an output bit according to a clock provided by the clock providing unit 400b; A second LFSR 100d for outputting an output bit according to a clock provided by the clock providing unit 400b; A first bit memory 200c for receiving and storing previous carry values; A second bit memory 200d for receiving and storing previous memory state values; And the output bits of the first and second LFSRs 100c and 100d and the previous and previous memory values stored in the first and second bit memories 200c and 200d, A calculator 300b for generating a current memory state value, outputting the output key sequence as a cipher and providing a current carry value and a current memory state value to the first and second bit memories 200c and 200d; The first LFSR 100c has a random number generation function of 255 bits. The second LFSR 100d generates a random number of 257 bits, Function.
Thereby, it is possible to cope with a random bit error in wireless communication through an algorithm.
In addition, the present invention provides the effect of generating a random number sequence of a safe level in random number generation of a sufficient size LFSR.
In addition, the present invention provides an effect of making it difficult to perform malicious cryptanalysis through a correlation attack or the like by increasing nonlinearity.

Description

CLOCK CONTROLLED RANDOM PASSWORD GENERATOR FOR MINIMIZING BIT ERROR RATE IN WIRELESS COMMUNICATION BACKGROUND OF THE INVENTION [0001]

The present invention relates to a clock-controlled random-number generator for minimizing a bit error in a wireless communication, and more particularly, to a clock-controlled random-number generator for minimizing a bit error in a wireless communication, Type random random number generator.

Due to the development of communication media, the proportion of wireless communication is increasing. Wireless communication is more vulnerable to external noise than wired communication and is more vulnerable to distortion and modulation than wired communication. In particular, the effects of physically adjacent equipment can be so severe that data may be lost due to slowing or canceling of radio waves.

Despite these drawbacks, wireless communication has become a preferred communication method for many people due to its ease of use.

In order to protect the leakage of data according to the changing trend of Internet Of Things (IoT) and personal authentication method based on short range wireless communication (NFC, Blue tooth, ...), encryption is essential Is required.

In the case of block ciphers, if a specific block can not be delivered correctly, it can be a problem because it can affect the entire message decryption. Therefore, it can be considered that a stream cipher, which is encrypted by relatively small transmission based on one bit, is suitable for coping with an error of wireless communication.

Korean Patent Registration No. 10-1649996 entitled " Threshold clock controlled random password generator " Korean Patent Laid-Open Publication No. 10-2004-0058531 entitled " Device for controlling noise generator for clock " Korean Patent Laid-Open Publication No. 10-2010-0067211 "Multi-phase clock generation circuit and controlling method thereof" Korean Patent Registration No. 10-0723537 entitled " Method and Apparatus for Generating a Clock Signal and Method and Apparatus for Controlling the Clock Frequency Using the Clock Signal &

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and it is an object of the present invention to provide a clock-controlled random code generator for minimizing a wireless communication bit error so as to correspond to a wireless communication bit error through an algorithm.

The present invention also provides a clock-controlled random generator for minimizing a bit error in a wireless communication in order to generate a random sequence of a sufficient level for generation of a random number in an LFSR having a sufficient size.

The present invention also provides a clock-controlled random code generator for minimizing a bit error in a wireless communication in order to increase nonlinearity and make malicious cryptanalysis through a correlation attack difficult.

However, the objects of the present invention are not limited to the above-mentioned objects, and other objects not mentioned can be clearly understood by those skilled in the art from the following description.

According to an aspect of the present invention, there is provided a clock adjustable random code generator for minimizing a bit error in a wireless communication, comprising: a clock providing unit for providing a clock; A first LFSR 100c outputting an output bit according to a clock provided by the clock providing unit 400b; A second LFSR 100d for outputting an output bit according to a clock provided by the clock providing unit 400b; A first bit memory 200c for receiving and storing previous carry values; A second bit memory 200d for receiving and storing previous memory state values; And the output bits of the first and second LFSRs 100c and 100d and the previous and previous memory values stored in the first and second bit memories 200c and 200d, A calculator 300b for generating a current memory state value, outputting the output key sequence as a cipher and providing a current carry value and a current memory state value to the first and second bit memories 200c and 200d; The first LFSR 100c has a random number generation function of 255 bits. The second LFSR 100d generates a random number of 257 bits, Function.

In this case, in the first LFSR 100c and the second LFSR 100c, two primitive polynomials of 16 taps of 16 taps of 255 bits and 16 taps of 257 bits are output to the output key Can be used to generate a sequence.

을 원시 다항식으로 사용할 수 있다.Further, in another embodiment of the present invention, the first LFSR 100c includes:

Can be used as primitive polynomials.

을 원시 다항식으로 사용할 수 있다. Further, in another embodiment of the present invention, the second LFSR 100d includes:

Can be used as primitive polynomials.

In another embodiment of the present invention, the clock providing unit 400b may use a counter value of the first LFSR 100c and the second LFSR 100d, To the LFSR 100c and the second LFSR 100d.

에 의해 제공할 수 있다. Further, in another embodiment of the present invention, the clock providing unit 400b may set the clock provided to the second LFSR 100d as the state value of the first LFSR 100c,

Lt; / RTI >

에 의해 제공할 수 있다.
Further, in another embodiment of the present invention, the clock providing unit 400b may set the clock provided to the first LFSR 100c as the state value of the second LFSR 100d,

Lt; / RTI >

The clock-controlled random code generator for minimizing a bit error in a wireless communication according to an embodiment of the present invention provides an effect of coping with a wireless communication bit error through random random number generation algorithm.

In addition, the clock-controlled random code generator for minimizing a bit error in a wireless communication according to another embodiment of the present invention provides an advantageous effect that a random sequence of a sufficient level can be generated at a safe level in random number generation.

In addition, according to another embodiment of the present invention, a clock-controlled random code generator for minimizing a bit error in a wireless communication increases nonlinearity and provides an effect of making it difficult to perform malicious decryption through a correlation attack or the like.

FIG. 1 is a diagram for explaining a basic stream encryption algorithm among symmetric key encryption schemes used in a clock-controlled random code generator for minimizing a bit error in a wireless communication according to an embodiment of the present invention.
FIG. 2 is a block diagram of a clock-controlled random code generator (hereinafter referred to simply as " LFSR ") having two LFSRs having different random numbers as a basis of the clock- 1a.
3 is a block diagram showing a clock-controlled random code generator 1b for minimizing a bit error in a wireless communication according to an embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a detailed description of preferred embodiments of the present invention will be given with reference to the accompanying drawings. In the following description of the present invention, detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear.

In the present specification, when any one element 'transmits' data or signals to another element, the element can transmit the data or signal directly to the other element, and through at least one other element Data or signal can be transmitted to another component.

FIG. 1 is a diagram for explaining a basic stream encryption algorithm among symmetric key encryption schemes used in a clock-controlled random code generator for minimizing a bit error in a wireless communication according to an embodiment of the present invention.

Referring to FIG. 1, the encryption scheme is divided into a symmetric key or asymmetric key encryption. And symmetric key encryption can be divided into two kinds, and block cipher and stream cipher exist.

On the other hand, the clock-controlled random code generator uses a cryptosystem corresponding to the stream cipher in the symmetric key cipher. As shown in FIG. 1, a stream cipher has a structure in which random random numbers are sequentially generated and combined with data. A typical stream cipher generates a random random number in 1-bit units, XORs the generated value and each value to be encrypted to obtain 1-bit encrypted data.

The critical clock adjustable random encryption is basically the object of the mutual clock control type structure to increase the nonlinearity in the output key sequence, making it difficult to decrypt a correlation attack or the like. Through the random random number generation, it is possible to have different information values in the same data transmission by using encryption similar to OTP (One Time Password).

Two linear feedback shift registers (LFSRs) having different lengths are set to match synchronization between different devices. At this time, the LFSR is a type of shift register, in which the value input to the register is calculated as a linear function of the previous state values.

Since the operation of the LFSR is deterministic, the sequence of values generated by the LFSR is determined by the previous value. Since the number of values that a register can have is finite, this sequence is repeated by a specific number of times as in Equation (1) below.

2 is a block diagram showing a configuration of a random-number generator 1b according to an embodiment of the present invention. Referring to FIG. 2, 1 shows a clock adjustable random code generator 1a having a first LFSR 100a and a second LFSR 100b, which are LFSRs.

Referring to FIG. 2, the stream encryption of the clock-controlled random-number generator 1a includes two LFSRs having different random number values of 127 and 129, which are different predetermined bit values. The clock control type random password generator (1a) is applied to a clock control LM series, the key stream generator is used the period of the period from L _{i + 1} or L ₁ in the LFSR for the N on the basis of L _i to L _n do.

Also, in the stream encryption of the clock-adjustable random code generator 1a, the clock supplier 400a provides a clock to the first LFSR 100a and the second LFSR 100b.

The first LFSR 100a and the second LFSR 100b output an output bit according to a clock provided by the clock supplier 400a. The first bit memory 100a receives and stores the previous carry value, The second bit memory 100b receives and stores the previous memory state value.

The arithmetic unit 300a receives the output bits of the first LFSR 100a and the second LFSR 100b and the previous carry value stored in the first bit memory 200a and the second bit memory 200b, A current carry value and a current memory state value, and outputs the output key sequence as a cipher, and outputs the current carry value and the current memory state value to the first bit memory 200a and the second bit And provides it to the memory 200b.

The clock-controlled random password generator 1a including the components that perform this operation is simple, easy to use in hardware and software, and has high security. This is because the LFSR is generally used in the case of stream cipher, which is suitable for hardware and software, and permits fast encryption and decryption rates. Also, the feedback loop polynomial in each LFSR of the clock-controlled random-number generator 1a provides a feature that has a large period and good statistical characteristics and is continuously generated.

On the other hand, the clock-adjustable random code generator 1a is a hybrid generator, and is an improved generation generator in combination with a clock-controlled generator having high security.

Claim 1 LFSR to use a function of 127-bit (100a) is a clock controlled by the function (f _b) provided by the clock supply unit (400a), has the output values of the random integer. In addition, the second LFSR 100b using the 129-bit function is clock-controlled by the function f _a provided by the clock controller 400a and has an output value of a random integer.

The two clock-modulated functions (f _a , f _b ) provide multiple clocks to different LFSRs, so that the output of the LFSR is more unpredictable.

The clock-controlled random-number generator 1 is calculated using the same formula as z _j with the result of Equation (2) below. Then, the value of c _j is calculated using the formula shown in [Equation 3]. Further, the value of d _j is calculated by using the formula as shown in [Equation 4].

That is, when the first and second LFSRs 100a and 100b are a and b and the first and second bit memories 200a and 200b are c and d and the time is j, a _j and b _j Are the outputs of the first and second LFSRs 100a and 100b, respectively, the carry c _j is determined by f _c and the memory state d _j is determined by f _d . Here, the output function f _z is represented by a key sequence bit and z _j , and the output function can be expressed as f _c , f _d , and f _z , as shown in Equations (2) to (4).

In this case, initial carry value is shown when j-1 = 0 in c _j-1 , and initial memory state value when j-1 = 0 in d _j-1 .

As a result, in order to take advantage of the computed hydrodynamic characteristics of the vulnerability avoidance and the LFSR, the LFSR is adopted to give linearity to the sequence generator, and the nonlinear Boolean function is used as a combination function and a filtering function to have irregular periods in all of the LFSRs, Nonlinearity.

In order to improve the generation speed of the sequence generator and increase the nonlinearity of such a sequence generator, efforts to make malicious cryptanalysis through a correlation attack and the like continue to be difficult.

3 is a block diagram showing a clock-controlled random code generator 1b for minimizing a bit error in a wireless communication according to an embodiment of the present invention. Referring to FIG. 3, the clock-controlled random-number generator 1b for minimizing a bit error in a wireless communication has a structure similar to that of FIG. 2 and includes a first LFSR 100c, a second LFSR 100d, a first bit memory 200c ), A second bit memory 200d, an operator 300b and a clock supplier 400b. The output functions f _c , f _d , and f (x, y) according to the above- _z . In FIG. 2 and FIG. 3, symmetrical components such as the first LFSRs 100a and 100c and the second LFSRs 100c and 100d are denoted by the same reference numerals for ease of description and concise description. And performs other functions and operations as described below.

On the other hand, the clock-controlled random-number generator 1b for minimizing the bit error in the wireless communication is provided with an LFSR which satisfies the repetition times as in the above-mentioned Equation (1) 1 LFSR 100c and the polynomial used in the second LFSR 100d.

In other words, the following equations (5) and (6) are used for the two LFSRs 100c and 100d each having 16 taps of 255 bits and 16 taps of 257 bits, which are used in the first LFSR 100c and the second LFSR 100d. (two primitive polynomials).

If a clock-controlled random generator (1a) having a first LFSR (100a) and a second LFSR (100b) in FIG. 2 use a sufficiently sized LFSR for random number generation, a secure random sequence can be generated .

To this end, the clock-controlled random-number generator 1 for minimizing a bit error in the wireless communication according to the present invention includes a first LFSR 100c having a random number generation function of 255 bits of LFSR and a second LFSR 100c having a random number generation function of LFSR 257 bits. The LFSR 100d is used.

Each of the first LFSR 100c and the second LFSR 100d has a size of 2 ²⁵⁵ -1 and 2 ²⁵⁷ -1 when the number of bits is substituted into Equation (1). Therefore, the clock-controlled random code generator 1b for minimizing a bit error of a wireless communication using a 256-bit function can generate a random number having a length similar to 2 ⁵¹² -1.

In addition, the clock-controlled random generator 1b for minimizing the bit error of the wireless communication uses the state value of the other party to secure the disadvantage that each LFSR function has a predetermined size, The output order is changed as shown in Equation 8.

In this case, the first bit memory 200c and the first bit memory 200d, which are two state storage spaces, are used to weight the changes of the different LFSR functions and result values.

The clock-controlled random-number generator 1 for minimizing a bit error in the wireless communication has the same output as the clock-adjustable random-code generator 1a having the first LFSR 100a and the second LFSR 100b of FIG. 2 (2) to (4), which correspond to Equation (4).

The present invention can also be embodied as computer-readable codes on a computer-readable recording medium. A computer-readable recording medium includes all kinds of recording apparatuses in which data that can be read by a computer system is stored.

Examples of the computer-readable recording medium include a ROM, a RAM, a CD-ROM, a magnetic tape, a floppy disk, an optical data storage device and the like, and also implemented in the form of a carrier wave (for example, transmission over the Internet) .

The computer readable recording medium may also be distributed over a networked computer system so that computer readable code can be stored and executed in a distributed manner. And functional programs, codes, and code segments for implementing the present invention can be easily inferred by programmers skilled in the art to which the present invention pertains.

As described above, preferred embodiments of the present invention have been disclosed in the present specification and drawings, and although specific terms have been used, they have been used only in a general sense to easily describe the technical contents of the present invention and to facilitate understanding of the invention , And are not intended to limit the scope of the present invention. It is to be understood by those skilled in the art that other modifications based on the technical idea of the present invention are possible in addition to the embodiments disclosed herein.

1a, 1b: clock-controlled random password generator
100a, 100c: a first LFSR
100b, 100d: the second LFSR
200a, 200b: a first bit memory
200b and 200d: a second bit memory
300a, 300b: Operator
400a and 400b:

Claims (7)

A clock providing unit 400b for providing a clock; A first LFSR 100c outputting an output bit according to a clock provided by the clock providing unit 400b; A second LFSR 100d for outputting an output bit according to a clock provided by the clock providing unit 400b; A first bit memory 200c for receiving and storing previous carry values; A second bit memory 200d for receiving and storing previous memory state values; And the output bits of the first and second LFSRs 100c and 100d and the previous and previous memory values stored in the first and second bit memories 200c and 200d, A calculator 300b for generating a current memory state value, outputting the output key sequence as a cipher and providing a current carry value and a current memory state value to the first and second bit memories 200c and 200d; A random number generator for a random number generator, the random number generator comprising:
The first LFSR 100c includes primitive polynomials,

Has a random number generating function of 16 taps of 255 bits used for generation of the output key sequence,
The second LFSR 100d includes primitive polynomials,

And a random number generating function of 16 bits of 257 bits used for generating the output key sequence.
delete delete delete The clock distributor (400b) according to claim 1,
And provides the first LFSR (100c) and the second LFSR (100d) with a clock giving a change in the output order using the counterpart state values between the first LFSR (100c) and the second LFSR (100d) A clock-controlled random password generator for minimizing communication bit errors.
The clock distributor (400b) according to claim 1,
The clock provided to the second LFSR 100d as the state value of the first LFSR 100c,

Wherein the random number generator is provided by the random number generator.
The clock distributor (400b) according to claim 1,
The clock provided to the first LFSR 100c as the state value of the second LFSR 100d,

Wherein the random number generator is provided by the random number generator.

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