KR101877824B1 - Auxiliary memory unit - Google Patents

Abstract

According to an auxiliary memory device of the present invention, to control the operation of a plurality of semiconductor chips by processing a requested command of a user host through a controller, when data striping write is performed in a plurality of inactive NAND memory dies along an individual word line through the controller, the controller generates a parity about data to make adjacent word lines on the same layer belong to different parity groups, and the parity and data are written in a plurality of pages of one parity group in an individual inactive NAND memory die, and then, the parity and data are written in a plurality of pages of the other parity groups.

Description

AUXILIARY MEMORY UNIT}

The present invention relates to a semiconductor memory device which uses a semiconductor chip made of a 3D vertical-NAND flash and adopts a redundant array of inexpensive disks (RAID) and an auxiliary memory device for relieving an error bit of a semiconductor chip by minimally allocating a parity temporary storage area of an SRAM provided in a controller when generating a parity for data through a controller will be.

Generally, the auxiliary storage device is a storage device for assisting the main storage device (for example, the core storage device, the ROM, the RAM, etc. of the personal computer) when the storage capacity is insufficient. Here, the auxiliary storage device refers to a hard disk drive (HDD) or a solid state drive (SSD), but is limited to a solid state drive for the development of the invention.

The solid state drive uses a semiconductor memory chip as a storage medium. The semiconductor memory chip is a NAND flash memory chip. The NAND flash memory chip has a nonvolatile characteristic that preserves data written in the storage area even when the power is turned off. The solid state drive is electrically connected to a user host and mediates data exchange between the user host and the semiconductor memory chip using a controller provided in the solid state drive.

The solid state drive may be configured to write data in a bit region of a page along a page (unit of reading or writing of a NAND flash memory) corresponding to a word line of a semiconductor memory chip , A parity operation is performed on the data to be written in the bit area of the page in the parity generation circuit through the controller to temporarily store the parity in the parity temporary storage area of the SRAM , Fetches the parity from ESRAM and continues to record data and parity on the page.

Meanwhile, the solid state drive is a conventional technique for recovering a bit error generated in a bit area of a page after recording data and parity on a page. The solid state drive is disclosed in Korean Patent Publication No. 10-2017-0015757 Device and method of operation thereof ". In the conventional technology, the solid state drive includes two inactive memory devices made of a 2D plane-NAND flash and adopting a redundant array of inexpensive disks (RAID) It is used as a storage medium.

The RAID scheme is performed to divide data into page units and store the data in two inactive memory devices. Here, the solid state drive generates a parity for data to be written for each page according to the attribute of the page in the inactive memory device. The attributes of the page include at least two of a block offset, a plane offset, a page offset, a word line offset, and a number of bits stored per cell. However, the solid state drive must sequentially write data to the plurality of pages in the non-volatile memory device through the controller in accordance with the two-dimensional planar structure NAND flash characteristic of the non-volatile memory device.

The controller may include at least two parity temporary storage areas in the SRAM according to page attributes to generate parity for the data for each parity temporary storage area, And records the parity on the page according to the attribute of the page. The parity is used for relieving the error bit when an error bit occurs after a lapse of time from the data written to the page.

That is, as an example, when the page attribute is made up of word line offsets, the controller may include a first parity temporary storage area associated with the even word lines and a second parity temporary storage area associated with the odd numbered word lines, Numbered parity relating to an even-numbered word line and odd-numbered parity relating to an odd-numbered word line for data to be sequentially written to a plurality of pages in a memory device are simultaneously generated in the first and second parity temporary storage areas, And odd-numbered parity to record even and odd parity with data on the page in the inactive memory device.

Since the first and second parity temporary storage areas cause an increase in the number of parity temporary storage areas in the SRAM, the SRAM increases the burden on the price increase and storage ability. Similarly, as another example, when the page attribute is composed of two bits sequentially corresponding to one word line for each cell, the controller sets the page attribute to correspond to one word line in the SRAM A lower parity temporary storage area associated with a least significant bit (LSB) and a lower parity temporary storage area associated with a second significant bit (MSB).

In this case, the controller controls the upper parity relating to the first bit (LSB) and the lower parity relating to the second bit (MSB) for the data to be sequentially written to the plurality of pages in the inactive memory device, Respectively, and fetch the upper and lower parities from the SRAM to record the upper and lower parities together with the data on the page in the inactive memory device. Accordingly, the upper and lower parity temporary storage areas cause an increase in the number of parity temporary storage areas in the ESRAM, thereby imposing a burden on the cost increase and storage capability of the ESRAM.

If the page attribute consists of three pages (LSB, CSB, MSB) sequentially corresponding to one word line per cell, the SRAM is divided into upper and middle parity temporary storage areas It is not free from the burden of the price increase and the storage ability. Once again, the inactive memory device is made up of a two-dimensional planar structure NAND flash and adopts a RAID method when data is stored.

Since the controller relies on the sequential recording method (= raid method) of data on a page in the inactive memory device in generating the parity in the SRAM, the controller divides the data to be inputted to the plurality of pages according to the page attribute, The solid state drive is burdened with the use of the ESRAM in accordance with the increase of the component in the parity property.

Korean Patent Publication No. 10-2017-0015757

SUMMARY OF THE INVENTION The present invention has been conceived to solve the conventional problems, and it is an object of the present invention to provide a method and a system for realizing a method of storing data related to a request of a user host in a random manner along a plurality of pages in an inactive memory device having a NAND flash characteristic Before recording, the controller divides the data based on the property of the page of the semiconductor chip to input the divided data in the parity temporary storage area of the SRAM, while intermittently generating the parity in the SRAM parity temporary storage area, Which does not require an increase in the number of parity temporary storage areas as the number of components increases.

An auxiliary memory device according to the present invention is a device in which individual semiconductor chips are electrically connected to each other so as to manage the operation of a plurality of semiconductor chips by processing a requested command of a user host through a controller Wherein the individual memory dies include a plurality of memory blocks arranged in three dimensions, and the individual memory blocks comprise a plurality of vertically arranged vertically arranged memory blocks, A plurality of word lines having NAND channels and sequentially stacked along individual vertical NAND channels, wherein each individual word line is a read or write unit of data (date) associated with the requested command of the user host A plurality of pages, and striping the data on the plurality of memory dies along the individual word lines through the controller The controller generates a parity for the data such that adjacent word lines in the same layer belong to different parity groups, and in the individual memory die, one parity group And writes data and parity to a plurality of pages of the remaining parity group.

The parity group may be divided into even word lines and odd word lines in the same layer.

Wherein the individual memory block comprises a cell in an intersection area of the individual page and an individual string and the individual page includes a plurality of cells along the individual word line, Wherein the individual word lines have a plurality of bit pages each corresponding to the plurality of bits for each cell, and the parity can be stored in the individual pages.

The controller may write the plurality of bit pages consecutively in the cell of the individual word line in the separate memory die.

The controller may write one bit page in the separate memory die and then write the remaining bit pages sequentially.

Also, the auxiliary memory device according to the present invention may be configured such that individual semiconductor chips are connected to each other so as to manage the operation of a plurality of semiconductor chips by processing a requested command of a user host through a controller. Wherein the individual memory die comprises a plurality of memory blocks arranged in three dimensions, and the individual memory blocks comprise a plurality of two-dimensionally arranged memory blocks, And a plurality of word lines sequentially stacked along individual vertical NAND channels with a vertical NAND channel of the user host, wherein each word line is read or written (data) associated with the requested command of the user host, Wherein each page has a plurality of pages and each page has a plurality of strings and a plurality of cells in an intersecting area, Storing a plurality of bits in a plurality of types of bit pages and striping the data along the individual word lines to the plurality of memory dies through the controller, Wherein the controller generates a parity for the data so that adjacent word lines in the same layer belong to different parity groups and wherein in the plurality of memory dies the individual pages corresponding to the individual word lines , And writes data and parity for each type of bit page, and then writes data and parity for each of the remaining types of bit pages.

When the data is striped write to the plurality of memory dies, adjacent word lines in the same layer of the separate memory die may belong to different striping groups.

Also, the auxiliary memory device according to the present invention may be configured such that individual semiconductor chips are connected to each other so as to manage the operation of a plurality of semiconductor chips by processing a requested command of a user host through a controller. Wherein the individual memory die comprises a plurality of memory blocks arranged in three dimensions, and the individual memory blocks comprise a plurality of two-dimensionally arranged memory blocks, And a plurality of word lines sequentially stacked along individual vertical NAND channels with a vertical NAND channel of the user host, wherein each word line is read or written (data) associated with the requested command of the user host, Wherein the plurality of pages have a plurality of pages as a unit, and the controller writes the data along the individual word lines to the plurality of memory dies When striping write, the controller generates a parity for the data so that adjacent word lines in the same layer belong to different parity groups, and in a plurality of layers of the individual memory die And parity for the data is generated for each individual layer so as to belong to the parity group which is sequentially applied to the adjacent word lines in the same manner.

The controller transfers a parity generated in one of the plurality of layers of the individual memory die to an external memory and then fetches the parity of the parity group of the one layer when writing the data in the next layer, Can be performed.

The external memory may include a dynamic random access memory (DRAM) located around the controller.

The external memory may include a dynamic random access memory (DRAM) provided in the user host, and may allocate a part of the dynamic random access memory to exchange the parity with the semiconductor chip through the controller.

Also, the auxiliary memory device according to the present invention may be configured such that individual semiconductor chips are connected to each other so as to manage the operation of a plurality of semiconductor chips by processing a requested command of a user host through a controller. Wherein the individual memory die comprises a plurality of memory blocks arranged in three dimensions, and the individual memory blocks comprise a plurality of two-dimensionally arranged memory blocks, And a plurality of word lines sequentially stacked along individual vertical NAND channels with a vertical NAND channel of the user host, wherein each word line is read or written (data) associated with the requested command of the user host, Wherein the plurality of pages have a plurality of pages as a unit, and the controller writes the data along the individual word lines to the plurality of memory dies When striping write, the controller writes the data to individual word lines in the same layer of an individual memory die and generates a parity, and writes the same repeated word lines to individual layers in a plurality of layers of the individual memory die The parity of the parity group of the one layer when the parity is generated in the next layer after transferring the parity generated in one of the plurality of layers of the individual memory die to the external memory, And performs a parity operation.

The external memory may include a dynamic random access memory (DRAM) located around the controller.

The external memory may include a dynamic random access memory (DRAM) provided in the user host, and may allocate a part of the dynamic random access memory to exchange the parity with the semiconductor chip through the controller.

According to the present invention, there is provided a semiconductor chip comprising a plurality of memory dies in a semiconductor chip, a plurality of memory blocks arranged in three dimensions on an individual memory die, a plurality of memory blocks arranged in a two- A plurality of vertical NAND channels, and a plurality of word lines sequentially stacked along individual vertical NAND channels,

The present invention relates to a semiconductor memory device, in which adjacent word lines electrically connected to each other in one layer (= layer of word lines at the same horizontal level) in an individual memory block with a plurality of vertical NAND channels electrically isolated from each other in an individual memory block In order to exclude electrical interference between adjacent word lines and to cross data between the even word line and the odd word line in the same layer in the individual memory block through the controller so that adjacent word lines belong to different parity groups , The parity of the data is generated intermittently using only one parity temporary storage area in the SRAM through the controller, and the parity of the even word lines and the parity of the odd word lines are stored in the temporary storage area of the SRAM at predetermined intervals To store the parity temporary storage area of SRAM It is not required to increase the number.

The present invention eliminates electrical interference between adjacent word lines by having adjacent word lines electrically connected to each other in one layer in an individual memory block with a plurality of vertical NAND channels electrically isolated from each other in the individual memory blocks, In order to write data and parity for each bit page in one cell in a plurality of memory dies and write data and parity for each bit page in the remaining cells through cross writing of data to an even word line and an odd word line in the same layer through the same layer, The parity of the data is intermittently generated using only one parity temporary storage area in the SRAM, and one cell related parity and the remaining cell related parity are sequentially stored in the SRAM parity temporary storage area at predetermined time intervals Sram's number of parity temporary storage areas It does not require.

1 is a block diagram showing an auxiliary memory device according to the present invention.
2 is a block diagram schematically showing one memory die inside a semiconductor chip in the auxiliary memory device of FIG.
FIG. 3 is a circuit diagram showing the memory block in two dimensions in detail in the memory die of FIG. 2. FIG.
FIG. 4 is a circuit diagram showing the memory block in three dimensions in the memory die of FIG. 2. FIG.
FIG. 5 is a block diagram schematically illustrating a striping write applied to a plurality of memory dies in a semiconductor chip of the auxiliary memory device of FIG. 1; FIG.
FIGS. 6 to 8 are circuit diagrams schematically showing adjacent word lines belonging to different parity groups in the same layer in the memory block of FIG. 3. FIG.
FIGS. 9 and 10 are block diagrams for writing data and parity for each bit page in one cell in the plurality of memory dies of FIG. 5, and then writing data and parity for each bit page in remaining cells.
11 is a block diagram for generating a parity for data to belong to a parity group that is applied sequentially in succession to adjacent word lines for each individual layer in a plurality of layers of an individual memory die.

The following detailed description of the invention refers to the accompanying drawings, which illustrate, by way of illustration, specific embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. It should be understood that the various embodiments of the present invention are different, but need not be mutually exclusive. For example, certain features, structures, and characteristics described herein may be implemented in other embodiments without departing from the spirit and scope of the invention in connection with one embodiment. It is also to be understood that the position or arrangement of the individual components within each disclosed embodiment may be varied without departing from the spirit and scope of the invention. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is to be limited only by the appended claims, along with the full scope of equivalents to which such claims are entitled, if properly explained. In the drawings, like reference numerals refer to the same or similar functions throughout the several views, and length and area, thickness, and the like may be exaggerated for convenience.

Hereinafter, preferred embodiments (s) of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily carry out the present invention .

1 is a block diagram showing an auxiliary memory device according to the present invention.

Referring to FIG. 1, an auxiliary storage device 120 according to the present invention may include a controller 90 and a storage medium 110. The controller 90 may control the exchange of data between the user host 10 and the storage medium 110. The controller 90 includes a processor 20, a DRAM 30, an SRAM 40, an ECC unit 50, a host interface unit 60, and a storage medium interface unit 70.

The processor 20 can control all operations of the controller 90. [ The processor 1110 may store data in the storage medium 110 and read the stored data from the storage medium 110 at the request of the user host 10. The processor 20 may control the operation of firmware including garbage collection and wear leveling to efficiently manage the storage medium 110. [

The DRAM 30 may store program and program data used by the processor 20. The DRAM 30 may temporarily store the data transmitted from the host interface unit 60 before delivering the data to the storage medium 110. The data transmitted from the storage medium 110 may be temporarily stored before being transmitted to the user host 10. The ESRAM 40 may be used for storing program codes and data that are read by the processor 10.

The program code may include instructions that are processed by the processor 20 in order for the processor 20 to control the internal units of the controller 90. The ECC unit 50 may encode data to be stored in the storage medium 110, and may decode the data read from the storage medium 110. The ECC unit 50 can detect and correct errors generated in the data according to an ECC algorithm.

The host interface unit 60 may exchange requests and data with the user host 10. The storage medium interface unit 70 may transmit control signals and data to the storage medium 110. The storage medium interface unit 70 can receive data from the storage medium 110. The storage medium interface unit 70 may be connected to the storage medium 110 through a plurality of channels CH0 to CHn.

The storage medium 110 may include a plurality of semiconductor chips 100. The controller 90 includes a processor 20, a DRAM 30, an SRAM 40, an ECC unit 50, a host interface unit 60, and a storage medium And the interface unit 70 are electrically connected to each other.

FIG. 2 is a block diagram schematically showing one memory die inside a semiconductor chip in the auxiliary memory device of FIG. 1, and FIG. 3 is a circuit diagram showing two-dimensionally detailed memory blocks in the memory die of FIG.

Fig. 4 is a circuit diagram showing the memory block in three dimensions in the memory die of Fig. 2 in detail; Fig. 5 is a diagram illustrating a striping write applied to a plurality of memory dies in the semiconductor chip of the auxiliary memory device of Fig. As shown in FIG.

2 to 5, the auxiliary memory device 120 processes a requested command of a user host 10 through a controller to generate a plurality of semiconductor chips (100 in FIG. 1) ). Here, the individual semiconductor chips 100 include a plurality of memory dies electrically connected to each other. The plurality of memory dies are shown only in FIG. 2 in order to simplify the description of the present invention.

The individual memory dies include a plurality of memory blocks arranged in three dimensions as shown in FIGS. The individual memory blocks include a plurality of word lines (WL) sequentially stacked along individual vertical NAND channels with a plurality of two-dimensionally arranged vertical NAND channels, as shown in FIGS. 3 and 4. FIG. Although the word lines WL shown in FIG. 4 have only four word lines a, b, c, and d in one layer, they may be four or more word lines.

Hereinafter, the four word lines (a, b, c, and d) are continuously used to describe the present invention. Meanwhile, the plurality of word lines WL may be electrically connected to each other in the same layer. Each of the word lines WL has a plurality of pages as read or write units of data (date) related to the requested command of the user host as shown in FIG. 2 and FIG. The individual pages include a data area and a spare area. Here, the individual memory block includes a cell in an intersection area of individual pages and individual strings as shown in FIG.

The individual pages include a plurality of cells along individual word lines WL. Meanwhile, the striping light is performed to write data along a page corresponding to an individual word line WL in a plurality of memory dies (Die 0, Die 1, ..., Die N) as shown in FIG.

FIGS. 6 to 8 are circuit diagrams schematically showing adjacent word lines belonging to different parity groups in the same layer in the memory block of FIG. 3. FIG. Here, Figs. 6 to 8 will be described with reference to Figs. 2 to 5. Fig. In addition, the parity is formed in one parity temporary storage area in the ESRAM provided in the controller using the controller of the solid state drive as described in detail in "Problem to be Solved" and "Effect of the Invention" . Therefore, the generation of parity in the ESRAM is performed through the operation of the controller, so the description of the ESRAM is omitted by the controller.

Referring to FIG. 6, when the controller 90 strips data on a plurality of memory dies along an individual word line WL through the controller 90, (Parity 1 or Parity 2) for the data so that the word lines Oa, Ob, Oc, Od belong to different parity groups, and a plurality of pages of one parity group (Parity 1) and writes data and parity (Parity 2) to a plurality of pages of the remaining parity group.

Here, the parity group is divided into even word lines (0a, 0c) and odd word lines (0b, 0d) in the same layer.

Referring to FIG. 7, when the controller 90 strips data along a word line WL to a plurality of memory dies, the controller 90 determines whether adjacent (Even LSB Parity, Odd LSB Parity, Even CSB Parity, Odd CSB Parity, Even MSB Parity, or Odd MSB) for data so that the word lines Oa, Ob, Oc and Od belong to different parity groups. Parity (Even LSB Parity) is written to a plurality of pages of one parity group in an individual memory die, and data and parity (Odd LSB Parity, Even CSB Parity, Odd CSB Parity, Even MSB Parity, and Odd MSB Parity).

Here, the individual pages include a plurality of cells along individual word lines WL. The cell has data in a plurality of bits. The individual word lines WL have a plurality of bit pages corresponding to a plurality of bits on a cell-by-cell basis. The parity (even LSB Parity, Odd LSB Parity, Even CSB Parity, Odd CSB Parity, Even MSB Parity, ) Are stored in separate pages.

In addition, the controller 90 continuously writes a plurality of bit pages in a cell of an individual word line WL in an individual memory die.

8, when the controller 90 strips data on a plurality of memory dies along an individual word line WL through the controller 90, the controller 90 determines whether adjacent Parity 0a (LSB, CSB or MSB), Parity 0b (LSB, CSB or MSB), Parity 0c (LSB, CSB or MSB) (LSB, CSB, or MSB) to a plurality of pages of one parity group on an individual memory die, and generates parity 0b (LSB, CSB, or MSB) Write Parity 0b (LSB, CSB or MSB), Parity 0c (LSB, CSB or MSB) or Parity 0d (LSB, CSB or MSB) to multiple pages of the remaining parity group.

Here, the individual pages include a plurality of cells along individual word lines WL. The cell has data in a plurality of bits. The individual word lines WL have a plurality of bit pages corresponding to a plurality of bits on a cell-by-cell basis. The parity 0a (LSB, CSB or MSB), Parity 0b (LSB, CSB or MSB) LSB, CSB, or MSB) or Parity 0d (LSB, CSB, or MSB)) are stored in separate pages.

In addition, the controller writes one bit page in an individual memory die and then writes the remaining bit pages sequentially.

FIGS. 9 and 10 are block diagrams for writing data and parity for each bit page in one cell in the plurality of memory dies of FIG. 5, and then writing data and parity for each bit page in remaining cells. Here, Figs. 9 and 10 will be described with reference to Figs. 2 to 5. Fig. In addition, the parity is formed in one parity temporary storage area in the ESRAM provided in the controller using the controller of the solid state drive as described in detail in "Problem to be Solved" and "Effect of the Invention" . Therefore, the generation of parity in the ESRAM is performed through the operation of the controller, so the description of the ESRAM is omitted by the controller.

Referring to FIG. 9, an individual page has a plurality of strings and a plurality of cells in an intersecting area, while storing data in individual cells in a plurality of bits to form a plurality of types of bit pages of bit page.

When the controller 90 strips the data along the individual word lines WL to a plurality of memory dies, the controller 90 controls the adjacent word lines 0a, 0b L 3-page parity or Odd W / L 3-page parity) for the data so as to belong to different parity groups, Data and parity (Even W / L 3-page parity) for one type of bit page are written in an individual page corresponding to a word line, and data and parity Odd W / L 3-page parity.

Referring to FIG. 10, an individual page has a plurality of strings and a plurality of cells in an intersecting area, and stores data in individual cells in a plurality of bits to form a plurality of types of bit pages ).

When the controller 90 strips the data along the individual word lines WL to a plurality of memory dies, the controller 90 controls the adjacent word lines 0a, 0b (Parity 0a, Parity 0b, Parity 0c, or Parity 0d) for the data to be included in different parity groups, and to generate parity After writing data and parity (Parity 0a) for each type of bit page in the page, data and parity (Parity 0b, Parity 0c, or Parity 0d) are written for the remaining types of bit pages.

Here, when the data is striped write to a plurality of memory dies, adjacent word lines (0a, 0b, 0c, 0d) in the same layer of the individual memory die are connected to different striping groups .

11 is a block diagram for generating a parity for data to belong to a parity group that is applied sequentially in succession to adjacent word lines for each individual layer in a plurality of layers of an individual memory die. Here, FIG. 11 will be described with reference to FIGS. 2 to 5. In addition, the parity is formed in one parity temporary storage area in the ESRAM provided in the controller using the controller of the solid state drive as described in detail in "Problem to be Solved" and "Effect of the Invention" . Therefore, the generation of parity in the ESRAM is performed through the operation of the controller, so the description of the ESRAM is omitted by the controller.

11, when the controller 90 strips data on a plurality of memory dies along an individual word line WL through the controller 90, the controller 90 determines whether adjacent A parity copy, a parity copy, or a parity copy) for the data so that the word lines 0a, 0b, 0c, and 0d belong to different parity groups, (Parity a copy, Parity b copy) for the data so as to belong to the parity group which is sequentially applied to the adjacent word lines 0a, 0b, 0c, and 0d for each individual layer in a plurality of layers of the die , Parity c copy, or Parity d copy).

The controller 90 transfers a parity generated in one of a plurality of layers of an individual memory die to an external memory and then writes the data in one layer when starting writing data in the next layer. And performs a parity operation on the parity group. The external memory includes a dynamic random access memory (DRAM) 30 located around the controller 90. The external memory includes a dynamic random access memory (DRAM) (not shown) provided in the user host 10 and allocates a part of the dynamic random access memory to the semiconductor chip 100) and parity.

Similarly, when striping data across a plurality of memory dies along an individual word line WL through the controller 90, the controller 90 may control the same layer of the individual memory die , A parity group including a plurality of word lines WL repeatedly formed in a plurality of layers on an individual memory die is formed for each individual layer .

In addition, the controller 90 transfers a parity (parity a copy, parity c copy, or parity d copy) generated in one of a plurality of layers of an individual memory die to an external memory (Parity a copy, Parity c copy, or Parity d copy) of a parity group of one layer at the start of writing data in the next layer, and performs a parity operation.

Here, the external memory includes a dynamic random access memory (DRAM) 10 located around the controller 90. The external memory includes a dynamic random access memory (DRAM) (not shown) provided in the user host 10 and allocates a part of the dynamic random access memory to the semiconductor chip 100) and parity (parity a copy, parity c copy, or parity d copy).

layer; Layer, 0a, 0b, 0c, 0d; Word line
parity; Parity.

Claims (14)

An auxiliary memory device for managing the operation of a plurality of semiconductor chips by processing a requested command of a user host through a controller,
The discrete semiconductor chips include a plurality of memory dies electrically connected to each other, the discrete memory dies include a plurality of memory blocks arranged in three dimensions, and the individual memory blocks comprise two And a plurality of word lines sequentially stacked along individual vertical NAND channels with a plurality of dimensionally arranged vertical NAND channels, wherein each word line includes data associated with the requested command of the user host date as a unit of reading or writing a plurality of pages,
Wherein the controller is configured to strip the adjacent word lines in the same layer to a different parity group when striping the data along the individual word lines through the controller to the plurality of memory dies, Write data and parity to a plurality of pages of one parity group in the individual memory die, and write data and parity to a plurality of pages of the remaining parity group in the separate memory die.
The method according to claim 1,
Wherein the parity group is generated by dividing into even-numbered word lines and odd-numbered word lines in the same layer.
The method according to claim 1,
Wherein the individual memory block comprises:
A cell in an intersecting region of the individual page and an individual string,
The individual pages comprising a plurality of cells along the individual word lines,
The cell having the data as a plurality of bits,
The individual word lines having a plurality of bit pages each corresponding to the plurality of bits for each cell,
And said parity is stored in said separate page.
The method of claim 3,
The controller continuously writes the plurality of bit pages to the cell of the individual word line in the separate memory die.
The method of claim 3,
The controller writes one bit page in the separate memory die and then writes the remaining bit pages sequentially.
An auxiliary memory device for managing the operation of a plurality of semiconductor chips by processing a requested command of a user host through a controller,
The discrete semiconductor chips include a plurality of memory dies electrically connected to each other, the discrete memory dies include a plurality of memory blocks arranged in three dimensions, and the individual memory blocks comprise two A plurality of word lines having a plurality of dimensionally arranged vertical NAND channels and sequentially stacked along individual vertical NAND channels,
Each word line has a plurality of pages as a unit for reading or writing data related to a requested command of the user host, and each page has a plurality of strings and a plurality of cells ) Having a plurality of types of bit pages by storing the data in a plurality of bits in an individual cell,
Wherein the controller is configured to strip the adjacent word lines in the same layer to a different parity group when striping the data along the individual word lines through the controller to the plurality of memory dies, Data and parity for each type of bit page are written in the individual pages corresponding to the individual word lines in the plurality of memory dies and data and parity Auxiliary memory for writing.
The method according to claim 6,
When the data is striped write to the plurality of memory dies,
Wherein adjacent word lines in the same layer of the individual memory die belong to different striping groups.
An auxiliary memory device for managing the operation of a plurality of semiconductor chips by processing a requested command of a user host through a controller,
The discrete semiconductor chips include a plurality of memory dies electrically connected to each other, the discrete memory dies include a plurality of memory blocks arranged in three dimensions, and the individual memory blocks comprise two And a plurality of word lines sequentially stacked along individual vertical NAND channels with a plurality of dimensionally arranged vertical NAND channels, wherein each word line includes data associated with the requested command of the user host date as a unit of reading or writing a plurality of pages,
Wherein the controller is configured to strip the adjacent word lines in the same layer to a different parity group when striping the data along the individual word lines through the controller to the plurality of memory dies, Generating a parity for the data so as to belong to a parity group sequentially applied to the adjacent word lines for each individual layer in a plurality of layers of the individual memory die, Transferring a parity generated in one of the plurality of layers of the die to an external memory and fetching a parity of the parity group of the one layer when the data starts to be written in the next layer to perform a parity operation.
delete 9. The method of claim 8,
Wherein the external memory comprises a dynamic random access memory (DRAM) located around the controller.
9. The method of claim 8,
The external memory includes:
And a dynamic random access memory (DRAM) provided in the user host and allocating a part of the dynamic random access memory to exchange the parity with the semiconductor chip through the controller.
An auxiliary memory device for managing the operation of a plurality of semiconductor chips by processing a requested command of a user host through a controller,
The discrete semiconductor chips include a plurality of memory dies electrically connected to each other, the discrete memory dies include a plurality of memory blocks arranged in three dimensions, and the individual memory blocks comprise two And a plurality of word lines sequentially stacked along individual vertical NAND channels with a plurality of dimensionally arranged vertical NAND channels, wherein each word line includes data associated with the requested command of the user host date as a unit of reading or writing a plurality of pages,
When the controller strips the data along the individual word lines to the plurality of memory dies, the controller writes the data to individual word lines in the same layer of an individual memory die and generates a parity A parity group including word lines which are repeated in the same manner for each individual layer in a plurality of layers of the individual memory dies is constructed and the parity generated in one of the plural layers of the individual memory dies is transferred to the external memory And when the data is written in the next layer, fetches the parity of the parity group of the one layer to perform the parity operation.
13. The method of claim 12,
Wherein the external memory comprises a dynamic random access memory (DRAM) located around the controller.
13. The method of claim 12,
The external memory includes:
And a dynamic random access memory (DRAM) provided in the user host and allocating a part of the dynamic random access memory to exchange the parity with the semiconductor chip through the controller.

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