KR101852270B1 - Reference-less Low Power Pulse Width Modulation Data Recovery Circuit using Time Comparison Delay Line and Recovery Method thereof - Google Patents

Abstract

Disclosed are a reference-less low power pulse width modulation (PWM) data recovery circuit using a time comparison delay line and a recovery method thereof. The low power PWM data recovery circuit using the time comparison delay line according to an embodiment of the present invention comprises: a first time comparison delay line to which PWM data is applied and which is connected to a plurality of buffers having the same delay; a second time comparison delay line which is connected in parallel to the first time comparison delay line, to which the PWM data is applied and which is connected to a plurality of buffers having the same delay; and a switch control unit alternately driving the first time comparison delay line and the second time comparison delay line. The present invention can recover the PWM data input by using values output through the first time comparison delay line and the second time comparison delay line.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a low-power pulse-width modulated data restoration circuit and a restoration method using a time comparison delay line,

The following embodiments relate to a low power pulse width modulated data recovery circuit and a reconstruction method that do not use a reference signal using a time comparison delay line.

2. Description of the Related Art In recent years, various types of mobile devices have been developed to be wearable devices beyond the miniaturization. To meet this trend, mobile device designers must design chips with low power and small size.

Accordingly, when transmitting a signal having a different pulse width according to the value of a data bit to be transmitted, a separate channel is not used to transmit a clock, Data and clock information can be transmitted through a channel of a receiver and a receiver can easily transmit data and data using a conventional PLL So that the clock information can be restored.

A clock is recovered from data in the form of pulse-width modulation (PWM) using a conventional phase-locked loop (PLL), and data is simply restored using a D flip- The clock and data recovery circuit must maintain the jitter of the restored clock to be less than 0.16 UI to restore the data information to an error ) Can be restored without.

Korean Patent Laid-open No. 10-2016-0028048 relates to a clock and data restoration circuit and a restoration method which do not require an external reference clock of a pulse-width modulation type which improves such a data bit error tolerance, and by means of a jitter component Describes a technique for a clock and data recovery circuit that does not require an external reference clock of a pulse-width modulation type that improves the output bit error rate that can occur and improves the data bit error tolerance .

Embodiments describe a low power pulse width modulated data restoration circuit and a restoration method that do not use a reference signal using a time comparison delay line. More specifically, a reference signal is not required and a time And provides a low power pulse width modulation data recovery technique that does not use a reference signal using a comparison delay line.

Embodiments relate to a method and apparatus for recovering data without time margin problems by alternately connecting a plurality of time comparison delay lines in parallel, thereby providing a low power pulse that does not use a reference signal with a time comparison delay line having a small area and low power consumption Width modulation data restoration circuit and restoration method.

The low-power pulse-width-modulated data restoring circuit using the time comparison delay line according to an exemplary embodiment of the present invention includes a first time comparison delay line to which a plurality of buffers having the same delay are connected and pulse-width modulation (PWM) data is applied; A second time comparison delay line connected in parallel with the first time comparison delay line, the second time comparison delay line being connected to the plurality of buffers to which the pulse width modulation data is applied and having the same delay; And a switch controller for alternately driving the first time comparison delay line and the second time comparison delay line, wherein the first time comparison delay line and the second time comparison delay line The input pulse width modulation data can be restored.

Here, the first time comparison delay line and the second time comparison delay line are connected in series with the buffers having the same delay in the upper side and the lower side, respectively. The upper and lower buffers share input nodes in pairs, A dummy buffer may be formed on the upper side, and a D flip-flop may be formed on the lower side.

The first time comparison delay line and the second time comparison delay line may include a first switch disposed between the buffers connected in series on the upper side of the low-level period of the pulse width modulation data signal, And a second switch disposed between buffers connected in series at a lower side of the high-level section of the pulse-width modulated data signal, Each node is filled with VDD values from left to right and each node can be reset to the GND value from right to left through the lower route.

The switch control unit may generate switch signals by combining a signal obtained by dividing the rising edge of the applied pulse width modulation data by two and a signal obtained by dividing the falling edge of the pulse width modulation data by two.

A multiplexer (MUX) for summing the values output through the first time comparison delay line and the second time comparison delay line; And an inverter for inverting non-return-to-zero (NRZ) data by inverting an output value of the multiplexer.

The multiplexer can use a signal obtained by dividing the falling edge of the pulse width modulation data by 2 with the selection signal without using the reference signal.

A method for restoring low-power pulse-width modulation data using a time comparison delay line according to another embodiment is a method for restoring a low-power pulse-width-modulated data using a time- To generate a switch signal; A first time comparison delay line in which a plurality of buffers having the same delay are connected and a second time comparison delay line connected in parallel with the first time comparison delay line are alternately driven by the switch signal to pass the pulse width modulation data ; Summing the values output through the first time comparison delay line and the second time comparison delay line using a multiplexer (MUX); And inverting the output value of the multiplexer using an inverter to restore non-return-to-zero (NRZ) data.

Embodiments can provide a low-power pulse-width-modulated data restoration circuit and a restoration method that do not use a reference signal using a time comparison delay line that does not require a reference signal but is implemented as an open loop and quickly restores data.

According to embodiments, a plurality of time comparison delay lines are connected in parallel to operate alternately, thereby restoring data without a time margin problem, and not using a reference signal using a time comparison delay line having a small area and low power consumption A low-power pulse-width-modulated data restoration circuit and a restoration method can be provided.

1 is a diagram illustrating a pulse width modulation (PWM) format format of a MIPI M-PHY according to one embodiment.
2 is a diagram schematically illustrating a time comparison delay line circuit according to one embodiment.
3 is a diagram schematically showing a time comparison delay line circuit of a parallel structure according to one embodiment.
4 is a diagram for explaining a parallel structure time comparison delay line according to an embodiment.
FIG. 5 is a diagram showing an overall block diagram of a pulse width modulation (PWM) data recovery circuit according to an embodiment.
6 is a flowchart illustrating a method for recovering low-power pulse-width-modulated data using a time comparison delay line according to an exemplary embodiment.
7 is a diagram showing an operation waveform of a pulse width modulation (PWM) data recovery circuit according to an embodiment.
8 is a diagram showing waveforms of post-layout simulation results of a pulse width modulation (PWM) data restoration circuit according to an embodiment.
FIG. 9 is a diagram illustrating an eye-diagram of reconstructed data according to an exemplary embodiment of the present invention.

Hereinafter, embodiments will be described with reference to the accompanying drawings. However, the embodiments described may be modified in various other forms, and the scope of the present invention is not limited by the embodiments described below. In addition, various embodiments are provided to more fully describe the present invention to those skilled in the art. The shape and size of elements in the drawings may be exaggerated for clarity.

Research is underway to provide mobile equipment with low cost and low power consumption in the SOC (System On Chip) industry. Since the pulse-width modulation (PWM) signal has both data and clock information, the structure of the receiving end can be simplified and the power consumption can be reduced, which is often used in an interface such as MIPI M-PHY.

1 is a diagram illustrating a pulse width modulation (PWM) format format of a MIPI M-PHY according to one embodiment.

Referring to FIG. 1, there is shown an example of a fixed rate scheme and a bit stream in the pulse width modulation (PWM) format format of MIPI M-PHY according to an embodiment. The fixed rate scheme and the bit stream example have clock information of a falling edge of one bit, Data (data bits) 0 and 1 can be expressed by setting different lengths of a low-level interval and a high-level interval.

Here, the lengths of a low-level interval and a high-level interval may be set differently depending on the type of pulse-width modulation (PWM) data bits to be input, This can be expressed as data bits 0 and 1 (ie 0: 2 UI / 3, 1: 1 UI / 3).

A phase-locked loop (PLL) includes a phase-frequency detector (PFD) and a phase-locked loop (PLL) A charge pump (CP), a loop filter (LF), and a voltage controlled oscillator (VCO).

By restoring the clock from the data of the pulse-width modulation (PWM) type using the conventional phase locked loop (PLL) and simply restoring the data (Data) by using the D flip-flop The clock and data recovery (CDR) circuit must keep the jitter of the restored clock less than 0.16 UI to restore the data without error. have.

That is, when the above-described pulse width modulation (PWM) data signal is restored by using a conventional clock and data recovery (CDR) circuit, it has a narrow time margin of 0.16 UI.

To solve this problem, a low-power pulse width modulated data restoration circuit that does not use a reference signal (external reference clock) using a time comparison delay line according to an embodiment uses a time comparison delay line to perform pulse width modulation PWM) data can be restored and the data can be restored freely from the problem of the existing narrow time margin.

Therefore, the low-power pulse-width-modulated data recovery circuit that does not use the reference signal using the time comparison delay line according to one embodiment improves the disadvantage of the clock and data recovery (CDR) circuit, It is possible to improve the data bit error tolerance which reduces the output data bit error rate.

2 is a diagram schematically illustrating a time comparison delay line circuit according to one embodiment.

A delay line is a circuit used to delay a specific signal or clock by a desired amount, and delay cells may be configured in series.

The time comparison delay line (TCDL) circuit 200 according to an exemplary embodiment is configured such that buffers having the same delay are connected in series on the upper side and the lower side, You can share the input node and isolate each node using a switch.

In addition, the delay error can be reduced by constructing a dummy buffer on one side and a D flip-flop on the other side so that the D flip-flop has the same input capacitance as the buffer.

2, the time comparison delay line circuit 200 according to an exemplary embodiment is configured such that the buffers having the same delay are serially connected from the left side to the right side in the upper side and the serial side from the right side to the left side, Respectively. In this case, the upper and lower buffers share input nodes in pairs, and each node can be separated using a switch.

And the upper right end constitutes a dummy buffer and the lower left end constitutes a D flip flop. Here, the D flip-flop can be designed to have the same input capacitance as the buffer, reducing the delay error.

The first switch SW1 turns on only a low level section of the pulse width modulation (PWM) signal and the second switch SW2 turns on only a high level section of the pulse width modulation (PWM) signal Can be turned on. Therefore, VDD values are filled from left to right through the upper route during one bit of data, and each node can be reset to the GND value from right to left through the lower route.

In this case, when the data of 0 is input, since the low-level section is longer than the high-level section, the first node n1 can not be reset to GND, .

Conversely, when data of 1 is input, since the high-level section is longer than the low-level section, the node n1 may be reset to GND and Q may be output as 0.

3 is a diagram schematically showing a time comparison delay line circuit of a parallel structure according to one embodiment.

Referring to FIG. 3, all nodes must be initially reset to ground (GND) in order for the time comparison delay line to operate correctly. When one bit of operation is completed, all nodes can be reset by using the reset signal (RST). If this process is performed, the next data coming in successively is lost.

In order to solve this problem, it is possible to use one and the same time comparison delay line in parallel and operate alternately one bit at a time. In other words, the time comparison delay line circuit 300 of the parallel structure according to an embodiment may be configured as a circuit of two time comparison delay lines 310 and 320 configured in parallel. At this time, switch circuits for driving the two time comparison delay lines 310 and 320 alternately can be configured.

The values output through the two time comparison delay lines 310 and 320 may be summed through a multiplexer (MUX) 330. At this time, the multiplexer 330 can use a signal obtained by dividing the falling edge of the pulse width modulation data by 2 with the selection signal 331 without using the reference signal.

Thereafter, the inverter 340 inverts the output value of the multiplexer 330 to restore NRZ (non-return-to-zero) data.

4 is a diagram for explaining a parallel structure time comparison delay line according to an embodiment.

4A is a diagram illustrating a switch circuit and a reset signal for driving a parallel structure time comparison delay line according to an exemplary embodiment.

Referring to FIG. 4A, the switch signals and the reset signals for alternately driving two time comparison delay lines are shown. The switch signals include pulse width modulation (PWM) data having a rising edge divided by two and a falling edge 2 can be made by combining signals.

신호를 조합하여 만들 수 있다. More specifically, the signals of the first switch SW1, the second switch SW2, the third switch SW3 and the fourth switch SW4 are pulse width modulation (PWM) data obtained by dividing the rising edge by 2 into D / 2 signal and falling edge divided by 2

Signals can be combined.

The first switch SW1 and the second switch SW2 are the switches of the first time comparison delay line and the third switch SW3 and the fourth switch SW4 signal are the switches of the second time comparison delay line.

4B is a diagram illustrating operation of a time comparison delay line according to one embodiment.

Referring to FIG. 4B, the waveforms of the switch signal and the first time comparison delay line are represented by n1 to n7, which represent respective nodes of the first time comparison delay line.

신호를 사용할 수 있다.
The non-return-to-zero (NRZ) data can be recovered by combining and inverting the outputs Q1 and Q2 from the two time comparison delay lines using a multiplexer (MUX). At this time, the selection signal of the multiplexer (MUX) divides the falling edge having the clock information of the pulse width modulation (PWM) data by 2

Signal can be used.

FIG. 5 is a diagram showing an overall block diagram of a pulse width modulation (PWM) data recovery circuit according to an embodiment.

5, a low-power pulse-width-modulated data recovery circuit 500 using a time comparison delay line according to an embodiment includes a first time comparison delay line 530, a second time comparison delay line 531, And a control unit 520. The low-power pulse-width-modulated data restoring circuit 500 using the time comparison delay line may further include a multiplexer 540 and an inverter 550 according to the embodiment. The entire block diagram of the pulse width modulation (PWM) data recovery circuit 500 according to this embodiment does not use the reference signal and is an open loop circuit.

The first time comparison delay line 530 may be coupled to a plurality of buffers to which pulse-width modulation (PWM) data is applied and the delay is the same.

The second time comparison delay line 531 may be connected to a plurality of buffers to which pulse-width modulation (PWM) data is applied and the delay is the same.

Here, the first time comparison delay line 530 and the second time comparison delay line 531 are connected in series with the buffers having the same delay in the upper side and the lower side, respectively, and the upper and lower buffers are connected to the input node A dummy buffer may be formed at the upper side, and a D flip-flop may be formed at the lower side. Here, the D flip-flop can be designed to have the same input capacitance as the buffer, reducing the delay error.

The second time comparison delay line 531 may be connected in parallel with the first time comparison delay line 530. In order for the time comparison delay line to work correctly, all nodes must be reset to ground (GND) initially. When one bit of operation is completed, all nodes can be reset by using the reset signal (RST). If this process is performed, the next data coming in successively is lost. In order to solve this problem, it is possible to use one and the same time comparison delay line in parallel and operate alternately one bit at a time.

The first time comparison delay line 530 and the second time comparison delay line 531 are arranged between the buffers serially connected on the upper side of the low-level period of the pulse width modulation data signal And a second switch disposed between the first switch and the buffers serially connected to the lower side of the high-level section of the pulse-width-modulated data signal.

During one bit of the pulse width modulation data, each node may be filled with VDD values from left to right via the upper route, and each node may be reset to the GND value from the right to the left via the lower route. Here, the D flip-flop can be designed to have the same input capacitance as the buffer, reducing the delay error.

The switch control unit 520 may alternately drive the first time comparison delay line 530 and the second time comparison delay line 531. [

The switch control unit 520 can generate the switch signals by combining the signal 510 obtained by dividing the rising edge of the applied pulse width modulation data by 2 and the signal 511 obtained by dividing the falling edge of the pulse width modulation data by 2.

신호(511)를 조합하여 만들 수 있다. For example, the switch control unit 520 may include a first switch SW1, a second switch SW2, a third switch SW3, and a third switch SW3 disposed in the first time comparison delay line 530 and the second time comparison delay line 531, The first switch SW1, the second switch SW2, the third switch SW3 and the fourth switch SW4 can be controlled by pulse width modulation (PWM) The D / 2 signal 510 dividing the rising edge of the data by 2 and the falling edge divided by 2

Signal 511 may be combined.

At this time, the first switch SW1 and the second switch SW2 are the switches of the first time comparison delay line 530, and the third switch SW3 and the fourth switch SW4 are the switches of the second time comparison delay line 530, Can be a switch on line 531. [

A multiplexer (MUX) 540 may sum the values output through the first time comparison delay line 530 and the second time comparison delay line 531. At this time, the multiplexer 540 can use a signal obtained by dividing the falling edge of the pulse width modulation data by 2 with the selection signal, without using the reference signal.

The inverter 550 may reverse the output value of the multiplexer 540 to restore NRZ (non-return-to-zero) data.

6 is a flowchart illustrating a method for recovering low-power pulse-width-modulated data using a time comparison delay line according to an exemplary embodiment.

Referring to FIG. 6, a method for recovering low-power pulse-width modulation data using a time comparison delay line according to an embodiment includes a signal obtained by dividing the rising edge of applied pulse-width modulation (PWM) A first time comparison delay line in which a plurality of buffers having the same delay are connected, and a second time comparison delay line connected in parallel with the first time comparison delay line, A time comparison delay line is alternately driven by a switch signal to pass pulse width modulation data, a step 620 for passing the value output through the first time comparison delay line and the second time comparison delay line to a multiplexer, (Step 630), and the output value of the multiplexer is inverted using an inverter to restore non-return-to-zero (NRZ) data Step 640 may be included.

Hereinafter, a method for restoring low-power pulse width modulation data using a time comparison delay line according to an embodiment will be described in more detail with an example.

The low-power pulse-width modulated data restoring method using the time comparison delay line according to one embodiment can be more specifically explained using the low-power pulse-width modulated data restoring circuit using the time comparison delay line according to the embodiment described with reference to FIG. have. The low-power pulse-width-modulated data recovery circuit using the time comparison delay line according to an exemplary embodiment may include a first time comparison delay line and a first time comparison delay line, a switch controller, a multiplexer, and an inverter.

In step 610, the switch control unit combines a signal obtained by dividing the rising edge of the applied pulse width modulation (PWM) data by two and a signal obtained by dividing the falling edge of the pulse width modulation data by two, Can be generated.

Accordingly, the switch control unit can alternately drive the first time comparison delay line and the second time comparison delay line.

In step 620, the first time comparison delay line and the first time comparison delay line are alternately driven by the switch signal to pass the pulse width modulation data.

Here, the first time comparison delay line and the first time comparison delay line may be connected in series with a plurality of buffers having the same delay, and may be connected in parallel with the first time comparison delay line and the first time comparison delay line.

In step 630, the multiplexer (MUX) may sum the values output through the first time comparison delay line and the second time comparison delay line. At this time, the multiplexer can use a signal obtained by dividing the falling edge of the pulse width modulation data by 2 with the selection signal, without using the reference signal.

In step 640, the inverter may restore the non-return-to-zero (NRZ) data by inverting the output of the multiplexer.

Embodiments can provide a low-power pulse-width-modulated data restoration circuit and a restoration method that do not use a reference signal using a time comparison delay line that does not require a reference signal but is implemented as an open loop and quickly restores data.

In addition, according to the embodiments, a plurality of time comparison delay lines are connected in parallel and are alternately operated, so that data can be restored without a time margin, and a small area and low power consumption can be achieved.

7 is a diagram showing an operation waveform of a pulse width modulation (PWM) data recovery circuit according to an embodiment.

신호의 하이 레벨(High-level)이 끝난 뒤에 출력된 Q1이 그 다음의 하이 레벨(High-level)에서 멀티플렉서(Multiplexer, MUX)의 출력으로 나오므로 입력된 펄스 폭 변조(PWM) 데이터는 2 clock +

(logic delay) 뒤에 복원된다고 할 수 있다. Referring to FIG. 7, in the case of the first time comparison delay line,

After the high-level signal is output, Q1 is output from the next high level to the output of the multiplexer (MUX), so that the input pulse width modulation (PWM) data is 2 clocks +

(logic delay).

Unlike conventional clock and data recovery (CDR) circuits that have the problem of time margins using D flip-flops, low power pulses that do not use a reference signal using a time comparison delay line according to one embodiment The width modulation data restoration circuit does not have a time margin problem since the input is already determined before the selection signal of the multiplexer (MUX) is inputted.

8 is a diagram showing waveforms of post-layout simulation results of a pulse width modulation (PWM) data restoration circuit according to an embodiment. And FIG. 9 is a diagram illustrating an eye-diagram of reconstructed data according to an exemplary embodiment of the present invention.

8 and 9, a low power pulse width modulation data recovery circuit that does not use a reference signal using a time comparison delay line according to an embodiment uses a 110 nm CMOS process and is designed for a data transmission rate of 1 Gbps . At this time, the jitter may appear at 8.55 ps.

As shown in FIG. 8, a post-layout simulation result of the low-power pulse-width-modulated data restoring circuit using no reference signal using the time comparison delay line according to one embodiment can be confirmed.

의 낮은 전력 소모를 가진다.The low-power pulse-width-modulated data recovery circuit that does not use a reference signal using the time comparison delay line according to the embodiment can recover data without a time margin problem, and has a small area of 0.0039 mm ² at a data rate of 1 Gbps and a low-

Of low power consumption.

Unlike conventional clock and data recovery (CDR) circuits, which do not require a reference signal, they can be quickly restored because they do not require a phase-locked loop (PLL) .

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. For example, it is to be understood that the techniques described may be performed in a different order than the described methods, and / or that components of the described systems, structures, devices, circuits, Lt; / RTI > or equivalents, even if it is replaced or replaced.

Therefore, other implementations, other embodiments, and equivalents to the claims are also within the scope of the following claims.

Claims (7)

A first time comparison delay line to which a plurality of buffers having the same delay and to which pulse-width modulation (PWM) data is applied are connected;
A second time comparison delay line connected in parallel with the first time comparison delay line, the second time comparison delay line being connected to the plurality of buffers to which the pulse width modulation data is applied and having the same delay;
A switch controller for alternately driving the first time comparison delay line and the second time comparison delay line;
A multiplexer (MUX) for summing the values output through the first time comparison delay line and the second time comparison delay line; And
An inverter for inverting NRZ (non-return-to-zero) data by inverting an output value of the multiplexer
Lt; / RTI >
Wherein the first time comparison delay line and the second time comparison delay line comprise:
The same buffers are connected in series on the upper and lower sides, and the upper and lower buffers share a pair of input nodes, respectively, and each node is separated using a switch, and a dummy buffer is formed on the upper side And a D flip-flop having the same input capacitance as the dummy buffer is formed at the other end of the dummy buffer, thereby reducing a delay error,
The switch control unit,
Generates a switch signal by combining a signal obtained by dividing the rising edge of the applied pulse width modulation data by 2 and a signal obtained by dividing the falling edge of the pulse width modulation data by 2,
The multiplexer comprising:
A signal obtained by dividing the falling edge of the pulse width modulation data by 2 is used as a selection signal without using an external reference clock as a reference signal and an input is already determined before the selection signal is input for time margin,
And for restoring the pulse width modulated data input using the values output through the first time comparison delay line and the second time comparison delay line, and in the case of the first time comparison delay line, Since the output value after the high level of the signal obtained by dividing the rising edge by 2 is output from the next high level to the output of the multiplexer, the inputted pulse width modulation data is 2 clocks + logic delay logic delay of the low-power pulse width modulated data. delete The method according to claim 1,
Wherein the first time comparison delay line and the second time comparison delay line comprise:
A first switch disposed between the buffers connected in series on the upper side which is turned on in the low-level period of the pulse-width modulated data signal, and
And a second switch disposed between buffers connected in series at the lower side of the high-level section of the pulse-width modulated data signal,
Lt; / RTI >
The VDD value is filled from left to right through the upper route during one bit of the pulse width modulation data and each node is reset to the GND value from the right side to the left side via the lower route
A low-power pulse-width-modulated data recovery circuit using a time comparison delay line. delete delete delete Generating switch signals by combining a signal obtained by dividing a rising edge of applied pulse width modulation (PWM) data by two and a signal obtained by dividing a falling edge of the pulse width modulation data by two;
A first time comparison delay line in which a plurality of buffers having the same delay are connected and a second time comparison delay line connected in parallel with the first time comparison delay line are alternately driven by the switch signal to pass the pulse width modulation data ;
Summing the values output through the first time comparison delay line and the second time comparison delay line using a multiplexer (MUX); And
Inverting the output value of the multiplexer using an inverter to restore non-return-to-zero (NRZ) data
Lt; / RTI >
Wherein the first time comparison delay line and the second time comparison delay line comprise:
The same buffers are connected in series on the upper and lower sides, and the upper and lower buffers share a pair of input nodes, respectively, and each node is separated using a switch, and a dummy buffer is formed on the upper side And a D flip-flop having the same input capacitance as the dummy buffer is formed at the other end of the dummy buffer, thereby reducing a delay error,
The multiplexer comprising:
A signal obtained by dividing the falling edge of the pulse width modulation data by 2 is used as a selection signal without using an external reference clock as a reference signal and an input is already determined before the selection signal is input for time margin,
And for restoring the pulse width modulated data input using the values output through the first time comparison delay line and the second time comparison delay line, and in the case of the first time comparison delay line, Since the output value after the high level of the signal obtained by dividing the rising edge by 2 is outputted from the next high level to the output of the multiplexer, the inputted pulse width modulation data is outputted as 2 clock + logic delay logic delay of the low-power pulse width modulated data.

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