KR101849944B1 - Duty-cycle corrector - Google Patents

Abstract

Duty cycle calibration circuit is disclosed. The present invention relates to a clock signal generator for generating an input clock signal, an input clock signal generating unit for generating a pre-calibration clock signal corresponding to the input clock signal, a plurality of rising edge control units And a rising edge slope and a falling edge slope of the pre-calibration clock signal in response to the falling edge control signal and the falling edge control signal of the pre-correction clock signal, And a global clock driver that calibrates the absolute value of the falling edge slope to the device fixed slope value and outputs a calibration clock signal.

Description

DUTY CYCLE CORRECTOR {DUTY-CYCLE CORRECTOR}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a duty cycle correction circuit, and more particularly, to a duty cycle correction circuit capable of duty cycle correction in a wide frequency range.

1 shows a duty change of a clock signal according to a configuration and a condition of a clock generating unit for generating and outputting a conventional clock signal.

FIG. 1 (a) shows a configuration of a conventional clock generating unit and a waveform of an output clock signal. FIG. 2 (b) shows a waveform diagram of a process, a supply voltage and a temperature And a duty change due to the capacitance (LC) variation.

As shown in FIG. 1 (a), a conventional clock generator generates a clock signal generated by a clock generator (CG) and a clock generator (CG), which generates a clock signal having a predetermined period and duty, And a global clock driver (GCD) for transferring data to other circuits in the chip.

The clock generator CG may generate a clock signal using a voltage controlled oscillator (VCO) or a phase locked loop (PLL), and may use a VCO and a PLL together.

However, the clock signal generated by the clock generator CG may include a duty error. Generally, the clock generator (CG) is designed to generate a clock signal having a duty of 50% at a designated frequency, but in reality, there is often an error in frequency and duty depending on the PVT change of the clock generator (CG).

On the other hand, when the clock signal generated in the clock generator (CG) in the integrated circuit chip is used in another circuit in the chip, a global clock driver (GCD) is provided to compensate for distortion that may occur during transmission of the clock signal . As shown in FIG. 1, the global clock driver (GCD) is implemented as a kind of buffer composed of an inverter chain and buffers and transmits a clock signal. However, a plurality of NMOS transistors and PMOS transistors of the buffer constituting the global clock driver (GCD) may cause a difference in the pull-up and pull-down capacities as the PVT changes, like the clock generator CG. have. The difference in pull-up and pull-down capability results in an error in the duty of the clock signal output from the buffer. That is, a power clock driver (GCD) provided to compensate for the distortion of the clock signal transmitted to other circuits may cause a problem that the duty of the clock signal is distorted. Also, the duty of the clock signal may be distorted by the load capacitance LC as shown in (b).

Since the clock signal is used as a reference for determining the operation timing of various circuits, the circuits receiving the clock signal are also designed based on the clock signal having the duty of 50%, so that the error of the duty may cause a malfunction of the circuit There is a problem. In particular, in the case of a digital circuit with a multi data rate (MDR) structure that implements a double or quadruple data rate using both rising and falling edges from a several GHz clock source, The duty of the duty must be calibrated since it may cause a serious error in the circuit operation because both the rising and falling edges of the duty cycle are used.

Also, even if the distortion of the duty does not cause a direct error, it must be corrected because it causes a timing imbalance in the pipelined architecture that is currently applied in digital circuits and limits the timing margin.

Korean Patent Publication No. 10-2003-0003361 (published on Jan. 10, 2003)

It is an object of the present invention to provide a duty cycle correction circuit capable of quickly calibrating a wide range of duty errors for a high frequency clock signal.

According to an aspect of the present invention, there is provided a duty cycle correcting circuit including: a clock signal generator for generating an input clock signal; A plurality of rising edge control signals and a plurality of falling edge control signals applied in response to the duty of the calibration clock signal, A duty cycle calibration unit for varying a rising edge slope and a falling edge slope of the pre-calibration clock signal; And a global clock driver for receiving and buffering the pre-calibration clock signal and outputting a calibration clock signal by calibrating an absolute value of a rising edge slope and a falling edge slope of the pre-calibration clock signal to be a device-fixed slope value; .

Wherein the duty cycle calibration unit is connected between a power supply voltage and a pre-calibration node to which the pre-calibration clock signal is output, and varies a rising edge slope of the pre-calibration clock signal in response to the plurality of rising edge control signals, A rising edge adjuster for pulling up the pre-calibration clock signal according to the rising rising edge slope when the voltage level of the signal is lower than a predetermined first reference level; And a control unit coupled between the pre-calibration node and a ground power source, for varying a falling edge slope of the pre-calibration clock signal in response to the plurality of falling edge control signals, wherein the voltage level of the input clock signal is a second reference level A rising edge adjusting unit for pulling down the pre-calibration clock signal according to the slope of the falling edge; And a control unit.

Wherein the rising edge control unit is connected in parallel between the power supply voltage and the pre-correction node and is activated in response to a corresponding rising edge control signal of the plurality of rising edge control signals, and the voltage level of the input clock signal is A plurality of pull-up drivers for pulling up the pre-calibration clock signal if the first reference level is lower than the first reference level; And a control unit.

Wherein each of the plurality of pull-up drivers includes a PMOS transistor connected in series between the power supply voltage and the pre-calibration node, a pull-up activating switch and a pull-up resistor, the PMOS transistor receiving the input clock signal as a gate, And the activation switch is turned on in response to a corresponding rising edge control signal of the plurality of rising edge control signals.

Wherein the falling edge control unit is connected in parallel to each other between the pre-calibration node and the ground power supply and is activated in response to a corresponding falling edge control signal of the plurality of falling edge control signals, A plurality of pull-down drivers for pulling down the pre-calibration clock signal if the second reference level is greater than or equal to the second reference level; And a control unit.

Wherein each of the plurality of pull-down drivers includes a pull-down resistor and a pull-down enable switch and an NMOS transistor connected in series between the pre-calibration node and the ground power source, the NMOS transistor receives the input clock signal as a gate, And the activation switch is turned on in response to a corresponding falling edge control signal of the plurality of falling edge control signals.

Wherein the duty cycle correction circuit receives the calibration clock signal and measures a timing ratio between a rising edge and a falling edge of the calibration clock signal and outputs the rising edge control signal and the plurality of rising edge control signals corresponding to the measured timing ratio, An edge control loop circuit for outputting a falling edge control signal; And further comprising:

Wherein the edge control loop circuit portion increases the number of rising edge signals having a signal level that turns on the pull-up enable switch among the plurality of rising edge signals if the duty of the calibration clock signal is determined to be less than 50% Wherein when the duty of the calibration clock signal is determined to be greater than 50% of the rising edge signal, the number of the falling edge signals having the signal level for turning on the pull- The number of falling edge signals having a signal level for turning on the pull-up enable switch is decreased and the number of falling edge signals having a signal level for turning on the pull-down enable switch among the plurality of falling edge signals is increased and outputted do.

And the global clock driver is implemented as an inverter chain buffering the pre-calibration clock signal.

Accordingly, the duty cycle correction circuit of the present invention can correct the duty for a wide duty error range of a high frequency clock signal by calibrating the duty using a plurality of PMOS transistors and NMOS transistors, The duty error can be adaptively corrected. A clock signal of a stable duty can be supplied to each circuit in the chip while occupying a very small area.

1 shows a duty change of a clock signal according to a configuration and a condition of a clock generating unit for generating and outputting a conventional clock signal.
Fig. 2 shows a configuration of a duty cycle correction circuit of the present invention.
3 shows waveform changes of the pre-calibration clock signal and the calibration clock signal with respect to the input clock signal.
4 shows the slope change of the pre-calibration clock signal according to the rising edge signal and the falling edge signal.

In order to fully understand the present invention, operational advantages of the present invention, and objects achieved by the practice of the present invention, reference should be made to the accompanying drawings and the accompanying drawings which illustrate preferred embodiments of the present invention.

Hereinafter, the present invention will be described in detail with reference to the preferred embodiments of the present invention with reference to the accompanying drawings. However, the present invention can be implemented in various different forms, and is not limited to the embodiments described. In order to clearly describe the present invention, parts that are not related to the description are omitted, and the same reference numerals in the drawings denote the same members.

Throughout the specification, when an element is referred to as "including" an element, it does not exclude other elements unless specifically stated to the contrary. The terms "part", "unit", "module", "block", and the like described in the specification mean units for processing at least one function or operation, And a combination of software.

FIG. 2 shows the configuration of the duty cycle correction circuit of the present invention, and FIG. 3 shows waveform changes of the input clock signal versus the pre-calibration clock signal and the calibration clock signal.

Referring to FIG. 2, the duty cycle correction circuit of the present invention includes a duty cycle correcting unit (DCC), a global clock driver (GCD), and an edge control loop circuit (ECL).

The duty cycle correcting unit DCC includes a rising edge adjusting unit PEC and a falling edge adjusting unit NEC which are connected in series between the power supply voltage VDD and the ground power supply VSS. The rising edge control unit PEC and the falling edge control unit NEC are respectively connected to the rising edge control signals UCS1 to UCSn and the falling edge control signals DCS1 to DCSn, (NPC) between the rising edge adjusting part (PEC) and the falling edge adjusting part (NEC) by adjusting the slope of the rising edge and the slope of the falling edge according to the duty of the input clock signal (ICS) And outputs a pre-calibration clock signal (PCC) whose edge slope has been corrected.

The rising edge adjusting unit PEC includes a plurality of pull-up driving units FUD1 to FUDn connected in parallel between the power supply voltage VDD and the pre-calibration node NPC. The falling edge adjusting unit NEC includes a pre- And a plurality of pull-down driving units FDD1 to FDDn connected in parallel between an NPC and a ground power supply VSS. Each of the plurality of pull-up driving units FUD1 to FUDn includes a PMOS transistor Tp connected in series between the power supply voltage VDD and the pre-calibration node NPC, a pull-up activation switch SWp and a pull-up resistor Rp Each of the pull-down drivers FDD1 to FDDn includes an NMOS transistor Tn connected in series between the pre-calibration node NPC and the ground voltage VSS and a pull-down enable switch SWn and a pull-down resistor Rn do.

An input clock signal ICS is applied to the gates of the PMOS transistor Tp of each of the pull-up driving units FUD1 to FUDn and the NMOS transistor Tn of each of the pull-down driving units FDD1 to FDDn. Accordingly, the plurality of PMOS transistors Tp and the plurality of NMOS transistors Tn are turned on or off according to the voltage level of the input clock signal ICS applied to the gate.

Here, the input clock signal ICS may be a signal generated in the clock generator CG shown in Fig. The duty of the input clock signal ICS is preferably 50%, but as shown in Figures 3 (a) and 3 (b), the duty may actually be less than 50% or exceed 50% by PVT .

On the other hand, the plurality of pull-up activation switches SWp are turned on or turned off in response to the corresponding rising edge control signals of the plurality of rising edge control signals UCS1 to UCSn, And is turned on or off in response to a corresponding falling edge control signal of the control signals DCS1 to DCSn. Here, the plurality of rising edge control signals UCS1 to UCSn and the plurality of falling edge control signals DCS1 to DCSn are applied in the edge control loop circuit portion ECL as described above.

Accordingly, each of the plurality of pull-up driving units FUD1 to FUDn is activated when the corresponding pull-up activation switch SWp is turned on in response to the rising edge control signal, and the PMOS transistor Tp of the activated pull-up driving units FUD1 to FUDn is activated And when the voltage level of the clock signal ICS is lower than the predetermined first reference level, the voltage level of the pre-calibration clock signal PCC output to the pre-calibration node NPC is pulled up. The rising edge control unit PEC includes a plurality of pull-up driving units FUD1 to FUDn and each of the PMOS transistors Tp of the pull-up driving units FUD1 to FUDn commonly receives the input clock signal ICS as a gate The performance of pulling up the pre-calibration clock signal PCC by the rising edge control unit PEC is limited to the number of the pull-up driving units FUD1 to FUDn activated in response to the plurality of rising edge control signals UCS1 to UCSn It is proportional. At this time, it is assumed that the pull-up performance of each of the plurality of pull-up driving units FUD1 to FUDn is the same.

Each of the pulldown driving units FDD1 to FDDn is activated when the corresponding pulldown activation switch SWn is turned on in response to the falling edge control signal and the NMOS transistor Tn of the activated pulldown driving units FDD1 to FDDn is activated When the voltage level of the clock signal ICS is equal to or higher than a predetermined second reference level, it is turned on and pulls down the voltage level of the pre-calibration clock signal PCC output to the pre-calibration node NPC. The falling edge control unit NEC includes a plurality of pulldown driving units FDD1 to FDDn and each of the NMOS transistors Tn of the pull down driving units FDD1 to FDDn commonly receives the input clock signal ICS as a gate The ability of the falling edge controller NEC to pull down the pre-calibration clock signal PCC is determined by the number of the pull-down drivers FDD1 to FDDn activated in response to the plurality of falling edge control signals DCS1 to DCSn It is proportional. At this time, it is assumed that the pull-down performances of the plurality of pull-down drivers FDD1 to FDDn are equal to each other. The first reference level and the second reference level may be set to be different from each other, but it is preferable that the first reference level and the second reference level are set to the same reference level, and the reference level set at this time is set to VDD / 2.

As a result, the duty cycle correcting unit DCC controls the pull-up and pull-down performance in accordance with the plurality of rising edge control signals UCS1 to UCSn and the plurality of falling edge control signals DCS1 to DCSn applied from the edge control loop circuit ECL And the slope of the rising edge and the falling edge of the input clock signal ICS with the pull-up and pull-down performance varied in response to the voltage level of the input clock signal ICS, as shown in Fig. 3 (b) And outputs a pre-calibration clock signal (PCC) to the pre-calibration node (NPC).

3 (a) and 3 (b), the duty cycle correcting unit DCC may be configured such that the duty of the input clock signal ISC is less than 50% or the duty of the input clock signal ISC is 50% If it exceeds, the slope of the rising and falling edges is adjusted to output the pre-calibration clock signal (PCC). However, the pre-calibration clock signal PCC may be output in such a manner that the slopes of the rising edge and the falling edge are different from each other, as shown in (c) and (d) of FIG. In addition, the edge control loop circuit portion ECL described later reflects not only the duty error of the input clock signal ICS but also the duty distortion due to the PVT change of the global clock driver (GCD) Since the control signals UCS1 to UCSn and the plurality of falling edge control signals DCS1 to DCSn are applied to the duty cycle correcting unit DCC, the duty of the pre-calibration clock signal PCC may not be 50%.

The global clock driver GCD is connected between the pre-calibration node NPC and the calibration output node NDO to buffer and receive the pre-calibration clock signal PCC from the pre-calibration node NPC to generate a calibration clock signal CC) to the calibration output node (NDO). The global clock driver (GCD) is implemented as a kind of buffer composed of an inverter chain as in the conventional global clock driver (GCD) shown in FIG. 1, and as shown in FIG. 3 (e) The calibration clock signal PCC is buffered so that the absolute values of the slopes of the rising edge and the falling edge of the calibration clock signal CC are equal to each other and output to the calibration output node NDO. The calibration clock signal (CC) output to the calibration output node (NDO) is then supplied to other circuits in the integrated circuit. That is, the calibration clock signal CC is an output signal of the duty cycle correction circuit that is output by calibrating the duty cycle of the input clock signal ICS.

3 (a) and 3 (b) show waveforms when the duty ratio of the input clock signal ICS is 50% and 50%, respectively, and FIGS. 3 (d) and 3 (E) to (h) show waveforms of the pre-calibration clock signal PCC in which the slope of the rising edge and the slope of the falling edge are adjusted and outputted in the duty cycle correcting unit DCC, And the waveform of the calibration clock signal CC output from the global clock driver (GCD) receiving the signal PCC.

3 (a), when the duty of the input clock signal ICS is less than 50%, the rising edge control unit PEC of the duty cycle calibration unit DCC, as shown in (c) In response to the plurality of rising edge control signals UCS1 to UCSn, maintains or slightly reduces the absolute value of the rising edge slope of the pre-calibration clock signal PCC, while the falling edge adjusting unit NEC has a falling edge slope The absolute value is relatively reduced so that the slope of the falling edge has a gentle slope rather than the slope of the rising edge. As shown in (e), the global clock driver (GCD) adjusts the rising edge slope of the modified pre-calibration clock signal PCC to have a predetermined slope corresponding to the pull-up performance of the global clock driver (GCD) Adjusts the falling edge slope of the modified pre-calibration clock signal PCC to have a predetermined slope corresponding to the pull-down performance of the global clock driver GCD, and outputs the calibration clock signal CC.

3 (b), when the duty of the input clock signal ICS exceeds 50%, as shown in (d), the rising edge of the duty cycle correcting unit DCC The falling edge control unit PEC responds to the plurality of rising edge control signals UCS1 to UCSn to greatly reduce the absolute value of the rising edge slope of the pre-calibration clock signal PCC while the falling edge adjusting unit NEC has a falling edge slope Reduce the absolute value relatively, so that the slope of the rising edge has a gentle slope than the slope of the falling edge. As shown in (g) and (h), the global clock driver (GCD) determines whether the rising edge slope and the falling edge slope of the modified pre-calibration clock signal PCC are equal to the pull-up and pull-down performance of the global clock driver Adjusts it to have a corresponding pre-designated slope, and outputs the calibration clock signal CC.

(E) to (h) of FIG. 3 show separate processes for adjusting the slope of the rising edge and the falling edge for convenience of understanding the operation of the global clock driver (GCD), but the global clock driver (GCD) The slope of the rising edge and the falling edge are all adjusted so that the calibration clock signal CC is actually combined with the rising edge shown in (e) and (g) and the falling edge shown in (f) and (h) So that the calibration clock signal CC is corrected while outputting the distortion of the duty.

2, the edge control loop circuit ECL receives the calibration clock signal CC output from the calibration output node NDO, analyzes the duty cycle of the calibration clock signal CC, A plurality of rising edge control signals UCS1 to UCSn and a plurality of falling edge control signals DCS1 to DCSn for controlling the pull-up and pull-down performance of the rising edge adjusting portion PEC and the falling edge adjusting portion NEC of the DCC, ).

The edge control loop circuit ECL counts the number of rising edge signals having the activation level among the plurality of rising edge control signals UCS1 to UCSn according to the duty of the analyzed calibration clock signal CC and the number of the falling edge control signals DCS1 ≪ / RTI > < RTI ID = 0.0 > DCSn). ≪ / RTI > That is, the edge control loop circuit part ECL determines the number of pull-up driving parts to be activated among the plurality of pull-up driving parts FUD1 to FUDn of the rising edge adjusting part PEC and controls the pull- The pull-up performance of the rising edge adjusting unit PEC and the pull-down performance of the falling edge adjusting unit NEC are controlled by determining the number of pulldown driving units to be activated among the FDDs FDD1 to FDDn.

The calibration clock signal (CC) output at the calibration output node (NDO) may not be 50% duty at the beginning of the duty cycle calibration circuit. This is because the edge control loop circuit part ECL detects the duty of the calibration clock signal CC which is the output of the global clock driver GCD and outputs a plurality of rising edge control signals UCS1 To UCSn and a plurality of falling edge control signals DCS1 to DCSn to the generating duty cycle controller DCC. However, since the calibration clock signal CC is fed back from the edge control loop circuit ECL while the plurality of rising edge control signals UCS1 to UCSn and the plurality of falling edge control signals DCS1 to DCSn are varied, The clock signal CC can be adjusted and output to have a duty ratio of 50%.

The edge control loop circuit portion ECL increases the number of rising edge signals having an activation level while decreasing the number of falling edge signals having an activation level when the duty is determined to be less than 50% The absolute value of the slope at the rising edge of the calibration clock signal CC is made smaller while the absolute value of the slope at the descending edge is reduced so that the timing at which the rising edge and the falling edge of the calibration clock signal CC cross the VDD / .

On the other hand, if it is determined that the duty exceeds 50%, the edge control loop circuit portion ECL decreases the number of rising edge signals having an activation level, while increasing the number of falling edge signals having an activation level, The absolute value of the slope at the rising edge of the signal PCC decreases while the absolute value of the slope at the falling edge increases so that the rising edge and falling edge of the calibration clock signal CC cross the VDD / Adjust the timing so that the timing becomes uniform.

The edge control loop circuit ECL receives the calibration clock signal CC and measures the ratio of the timing at which the rising edge and the falling edge cross the level of VDD / 2 to determine the number of pulses corresponding to the number of the pull-up drivers FUD1 to FUDn (n is a natural number) bits of the rising edge control signals UCS1 to UCSn and n-bit falling edge control signals DCS1 to DCSn corresponding to the number of pulldown driving units FDD1 to FDDn Can be implemented.

The edge control loop circuit ECL generates the plurality of rising edge control signals UCS1 to UCSn and the plurality of falling edge control signals DCS1 to DCSn separately. May be configured to generate a common edge control signal and apply it in common to the rising edge adjusting unit (PEC) and the falling edge adjusting unit (NEC).

4 shows the slope change of the pre-calibration clock signal according to the rising edge signal and the falling edge signal.

4, (a) shows a case in which all of the falling edge signals DCS1 to DCSn are fixed to have the activation level and the number of the rising edge control signals having the activation level among the plurality of rising edge control signals UCS1 to UCSn is 1 (PCC) when the number of clocks is increased from n to n. the slope of the falling edge of the pre-calibration clock signal PCC is fixed at the maximum slope, while the rising edge control having the activation level If the number of signals is one, the slope of the rising edge is formed very gently. However, if the number of rising edge control signals having an activation level is increased to n, the slope of the rising edge becomes the maximum slope and has a very sharp rising edge.

Here, the activation level is a level at which the pull-up activation switch SWp and the pull-down activation switch SWn are turned on, for example, can be set to the VDD level.

(B) show that the number of falling edge control signals having an active level among the plurality of falling edge control signals DCS1 to DCSn is n (n), while the plurality of rising edge control signals UCS1 to UCSn are all set to have an active level, (PCC) in the case where the number of clocks is reduced from one to one.

(b), since the plurality of rising edge control signals UCS1 to UCSn are all set to have the activation level, the slope of the falling edge of the pre-calibration clock signal PCC is fixed at the maximum slope. On the other hand, as the number of falling edge control signals having the activation level is reduced from n to 1, it can be seen that the slope of the falling edge of the pre-correction clock signal PCC having the maximum slope becomes gentle.

only one rising edge control signal (for example, UCS1) of the plurality of rising edge control signals UCS1 to UCSn has an activation level and the activation level of the plurality of falling edge control signals DCS1 to DCSn is (PCC) when the number of the falling edge control signals is reduced from n to one.

Since only one rising edge control signal UCS1 has an activation level, the slope of the rising edge of the pre-calibration clock signal PCC is formed very slowly, while the number of falling edge control signals having an activation level is n The slope of the falling edge of the pre-calibration clock signal PCC having the maximum slope becomes gentle.

Finally, (d) shows that only one rising edge control signal (for example, DCS1) of the plurality of falling edge signals DCS1 to DCSn has an active level and the activation level of the plurality of rising edge control signals UCS1 to UCSn The number of rising edge control signals is increased from 1 to n. Only the rising edge control signal DCS1 of one of the plurality of falling edge signals DCS1 to DCSn has the activation level so that the falling edge slope of the pre-calibration clock signal PCC has a gentle slope While the rising edge slope is transformed into a shape having a steep slope as the number of rising edge control signals having an activation level is increased.

As a result, as shown in Figs. 4A to 4D, the edge control loop circuit ECL includes a plurality of rising edge control signals UCS1 to UCSn applied to the duty cycle correcting unit DCC, The rising edge and the falling edge inclination of the pre-calibration clock signal PCC output from the duty cycle calibration unit DCC can be easily adjusted by adjusting the edge control signals DCS1 to DCSn.

Meanwhile, in FIG. 3, for convenience of explanation, the duty cycle correcting unit DCC is controlled so that the cycles passing the VDD / 2 level at the rising and falling edges of the pre-calibration clock signal PCC become equal to each other.

However, as described above, a plurality of NMOS transistors and PMOS transistors of a global clock driver (GCD) implemented as an inverter chain may also have different pull-up and pull-down performance depending on PVT changes. That is, in the process of adjusting the slope of the rising edge and the falling edge of the pre-calibration clock signal PCC, the duty may be further distorted.

In the duty cycle correction circuit of the present invention, however, the edge control loop circuit part ECL includes a plurality of rising edge control signals UCS1 to UCSn and a plurality of rising edge control signals UCS1 to UCSn in response to the calibration clock signal CC output from the global clock driver GCD. And generates falling edge control signals DCS1 to DCSn. The duty cycle correcting unit DCC controls the pull-up and pull-down performance in accordance with the plurality of rising edge control signals UCS1 to UCSn and the plurality of falling edge control signals DCS1 to DCSn applied from the edge control loop circuit ECL. do. Therefore, the duty cycle correcting unit DCC does not simply adjust the periods passing through the VDD / 2 level at the rising and falling edges of the pre-calibration clock signal PCC to be equal to each other, but buffering the pre-calibration clock signal PCC The inclination of the rising edge and the falling edge of the pre-calibration clock signal PCC is adjusted and output such that the duty of the calibration clock signal CC is finally 50% by reflecting the PVT change of the global clock driver (GCD).

Since the detailed circuit configuration of the edge control loop circuit part (ECL) can be designed in various forms, detailed circuit is not shown in the present invention.

It has been confirmed through simulation that the duty cycle correction circuit of the present invention can calibrate a wide range duty error of 17% to 80% to 5.9 ps within a convergence time of 172 ns for an input clock signal (ICS) of 8.1 GHz, It consumes low power and can calibrate the duty error adaptively to various PVT changes. The area occupied by the duty correction circuit (DCC) in a 45nm CMOS process also may be configured to supply a clock signal of, yet occupy a very small area to 0.032mm ² levels stable duty to each circuit in the chip.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is evident that many alternatives, modifications and variations will be apparent to those skilled in the art.

Accordingly, the true scope of the present invention should be determined by the technical idea of the appended claims.

Claims (9)

A clock signal generator for generating an input clock signal;
A plurality of rising edge control signals and a plurality of falling edge control signals applied in response to the duty of the calibration clock signal, A duty cycle calibration unit for varying a rising edge slope and a falling edge slope of the pre-calibration clock signal; And
A global clock driver for receiving and correcting the pre-calibration clock signal and outputting a calibration clock signal by calibrating an absolute value of a rising edge slope and a falling edge slope of the pre-calibration clock signal to a predetermined slope value; Lt; / RTI >
The duty cycle calibration unit
A power supply voltage and a pre-calibration clock signal are output in parallel with each other and activated in response to a corresponding rising edge control signal of the plurality of rising edge control signals, and the voltage level of the input clock signal And a plurality of pull-up drivers for pulling up the pre-calibration clock signal if the pre-calibration clock signal is lower than a predetermined first reference level, the pull-up edge adjusting unit pulling up the pre-calibration clock signal according to a variable rising edge slope; And
And a plurality of falling edge control signals which are activated in response to a corresponding falling edge control signal, wherein the voltage level of the input clock signal is higher than a predetermined second reference level A falling edge controller for pulling down the pre-calibration clock signal according to a variable falling edge slope, and a plurality of pull-down drivers for pulling down the pre-calibration clock signal; The duty cycle correction circuit comprising: delete delete 2. The image pickup apparatus according to claim 1, wherein each of the plurality of pull-
A PMOS transistor connected in series between the power supply voltage and the pre-calibration node, a pull-up activating switch and a pull-up resistor, the PMOS transistor receiving the input clock signal as a gate, Edge control signal is turned on in response to a corresponding rising edge control signal of the edge control signal. delete 5. The apparatus of claim 4, wherein each of the plurality of pull-
A pull-down resistor connected in series between the pre-calibration node and the ground, and a pull-down enable switch and an NMOS transistor, the NMOS transistor receiving the input clock signal as a gate, and the pull- And is turned on in response to a corresponding falling edge control signal of the edge control signal. 7. The apparatus of claim 6, wherein the duty cycle correction circuit
And a control circuit for receiving the calibration clock signal to measure a timing ratio between a rising edge and a falling edge of the calibration clock signal and outputting the plurality of rising edge control signals and the falling edge control signals corresponding to the measured timing ratio An edge control loop circuit portion; The duty cycle correction circuit further comprising: 8. The apparatus of claim 7, wherein the edge control loop circuitry
Wherein when the duty of the calibration clock signal is determined to be less than 50%, the number of rising edge signals having a signal level to turn on the pull-up enable switch among the plurality of rising edge signals is increased, The number of falling edge signals having a signal level for turning on the activation switch is reduced and output,
Wherein when the duty of the calibration clock signal is determined to be greater than 50%, the number of rising edge signals having a signal level to turn on the pull-up enable switch among the plurality of rising edge signals is decreased, Wherein the number of falling edge signals having a signal level for turning on the pull-down enable switch is increased and output. 2. The method of claim 1, wherein the global clock driver
And an inverter chain for buffering the pre-calibration clock signal.

Images