KR101848510B1 - Semiconductor memory device and operating method thereof - Google Patents

Abstract

The present invention relates to a storage device, and more particularly to a semiconductor memory device. A method of operating a semiconductor memory device according to an embodiment of the present invention includes performing an erase operation on a memory block, applying a verify voltage to at least one selected word line after performing an erase operation, And performing an erase verify operation. At this time, the word lines are divided into a plurality of word line groups, and the unselected word lines of the first word line group and the unselected word of the second one of the plurality of word line groups Different levels of pass voltages are applied to the lines.

Description

Technical Field [0001] The present invention relates to a semiconductor memory device and a method of operating the same,

The present invention relates to a storage device, and more particularly to a semiconductor memory device.

A semiconductor memory device is a memory device implemented using semiconductors such as silicon (Si), germanium (Ge), gallium arsenide (GaAs), indium phosphide (InP) to be. Semiconductor memory devices are classified into a volatile memory device and a nonvolatile memory device.

The volatile memory device is a memory device in which data stored in the volatile memory device is lost when power supply is interrupted. Volatile memory devices include static RAM (SRAM), dynamic RAM (DRAM), and synchronous DRAM (SDRAM). A nonvolatile memory device is a memory device that retains data that has been stored even when power is turned off. A nonvolatile memory device includes a ROM (Read Only Memory), a PROM (Programmable ROM), an EPROM (Electrically Programmable ROM), an EEPROM (Electrically Erasable and Programmable ROM), a flash memory, a PRAM , RRAM (Resistive RAM), and FRAM (Ferroelectric RAM). Flash memory is divided into NOR type and NOR type.

Semiconductor memory devices, such as flash memory devices, are gradually degraded as the number of program / erase (P / E) times increases. This deterioration reduces the reliability of the semiconductor memory device.

An embodiment of the present invention is to provide a semiconductor memory device and an operation method thereof that provide improved reliability.

A method of operating a semiconductor memory device according to an embodiment of the present invention includes performing an erase operation on a memory block; After performing the erase operation, a verify voltage is applied to at least one selected word line of the word lines connected to the memory block, and pass voltages are applied to unselected word lines of the word lines to perform an erase verify operation . Wherein the word lines are divided into a plurality of word line groups and the non-selected word lines of the first word line group of the plurality of word line groups and the non-selected word lines of the second word line group of the plurality of word line groups Different levels of pass voltages are applied to the word lines.

As an example, different pass voltages may be applied to unselected word lines of different word line groups.

As an embodiment, the same pass voltage may be applied to unselected word lines of the same word line group.

In an embodiment, the memory block is connected to a source select line and a drain select line, and the word lines may be disposed between the source select line and the drain select line.

In an embodiment, the second word line group is disposed adjacent to the drain select line than the first word line group, and the pass voltage applied to the unselected word lines of the second word line group is less than the first word May be higher than the unselected word lines of the line group.

In an embodiment, the memory block is connected to a dummy word line disposed between the word lines and the drain select line, and a voltage applied to the dummy word line is applied to unselected word lines of the second word line group May be higher than or equal to the applied pass voltage.

In an embodiment, the first word line group is disposed adjacent to the source select line than the second word line group, and the memory block is connected to a dummy word line disposed between the source select line and the word lines. And a voltage applied to the dummy word line may be higher than or equal to a pass voltage applied to unselected word lines of the first word line group.

As an embodiment, the memory block may be further coupled to a first dummy word line disposed between the source select line and the word lines, and a second dummy word line disposed between the word lines and the drain select line. have. At this time, the voltage applied to the second dummy word line may be higher than or equal to the voltage applied to the first dummy word line.

In an embodiment, a voltage applied to the drain select line may be higher than or equal to a voltage applied to the source select line.

In an embodiment, the first word line group is disposed adjacent to the source select line than the second word line group and the third one of the plurality of word line groups is connected to the drain And may be disposed adjacent to the selection line. At this time, the pass voltage applied to the unselected word lines of the first word line group is lower than that of the unselected word lines of the second word line group, and is applied to the unselected word lines of the third word line group The pass voltage may be lower than the unselected word lines of the second word line group.

In one embodiment, the voltage applied to the source select line is less than or equal to the pass voltage applied to the unselected word lines of the first word line group, and the voltage applied to the drain select line is less than the voltage applied to the third word line group Of the unselected word lines.

In an embodiment, the memory block may be coupled to a dummy word line disposed between the source select line and the word lines. Wherein a dummy word line voltage applied to the dummy word line is less than or equal to a pass voltage applied to unselected word lines of the first word line group and a voltage applied to the source select line is less than the dummy word line voltage Or the same.

In an embodiment, the memory block may be coupled to the drain select line and a dummy word line disposed between the word lines. At this time, the voltage applied to the dummy word line is lower than or equal to the pass voltage applied to the unselected word lines of the third word line group, the voltage applied to the drain select line is lower than the dummy word line voltage Can be the same.

A method of operating a semiconductor memory device according to an embodiment of the present invention includes performing an erase operation on the memory block; Perform a first erase verify operation based on data read through the first bit lines; And performing a second erase verify operation based on data read through the second bit lines. The word lines connected to the memory block are divided into a plurality of word line groups. When each of the first and second erase verify operations is performed, non-selected word lines of the first word line group and the second word line of the plurality of word line groups Different levels of pass voltages are applied to the unselected word lines of the group.

As an embodiment, the word line groups identified during the first erase verify operation and the word line groups identified during the second erase verify operation may be different.

As an embodiment, the word line groups identified during the first erase verify operation and the word line groups identified during the second erase verify operation may be the same.

In an embodiment, the first bit lines and the second bit lines may be alternately arranged.

Another aspect of the present invention relates to a semiconductor memory device. A semiconductor memory device according to an embodiment of the present invention includes a memory cell array including at least one memory block connected to word lines; And a peripheral circuit configured to apply a verify voltage to at least one selected word line of the word lines and to apply an erase verify operation by applying a plurality of pass voltages to unselected word lines of the word lines . The word lines are divided into a plurality of word line groups. Wherein the peripheral circuitry is operable to write to non-selected word lines of a first word line group of the plurality of word line groups and non-selected word lines of a second word line group of the plurality of word line groups And are configured to apply different levels of pass voltages.

As an example, different pass voltages may be applied to unselected word lines of different word line groups.

As an embodiment, the same pass voltage may be applied to unselected word lines of the same word line group.

According to an embodiment of the present invention, a semiconductor memory device and an operation method thereof, which provide improved reliability, are provided.

1 is a block diagram showing a semiconductor memory device according to an embodiment of the present invention.
FIG. 2 is a block diagram showing one of the memory blocks of FIG. 1 and a read and write circuit. FIG.
3 is a diagram showing threshold voltage distribution of memory cells of a memory block.
4 is a table illustrating an exemplary method of dividing word lines into a plurality of word line groups.
5 is a flowchart illustrating an operation method of a semiconductor memory device according to an embodiment of the present invention.
6 is a table showing voltages applied to word line groups and select lines.
7 is a table showing another embodiment of a method of dividing word lines into a plurality of word line groups.
FIG. 8 is a circuit diagram showing another embodiment of any one of the memory blocks of FIG. 1. FIG.
FIG. 9 is a table showing voltages applied to word line groups, select lines, and dummy word lines.
10 is a block diagram illustrating another embodiment of one of the memory blocks of FIG. 1 and a read and write circuit.
FIG. 11 is a table illustrating a method of dividing word lines into a plurality of word line groups when performing even sensing and od sensing.
12 is a block diagram showing a memory system including a semiconductor memory device.
13 is a block diagram illustrating a computing system including the memory system of FIG.

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention, and how to accomplish it, will be described with reference to the embodiments described in detail below with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein but may be embodied in other forms. The embodiments are provided so that those skilled in the art can easily carry out the technical idea of the present invention to those skilled in the art.

Throughout the specification, when a part is referred to as being "connected" to another part, it includes not only "directly connected" but also "indirectly connected" . Throughout the specification, when an element is referred to as "comprising ", it means that it can include other elements as well, without excluding other elements unless specifically stated otherwise.

1 is a block diagram showing a semiconductor memory device 100 according to an embodiment of the present invention.

Referring to FIG. 1, a semiconductor memory device 100 includes a memory cell array 110, a peripheral circuit 120, and a voltage generator 130.

The memory cell array 110 is connected to the address decoder 121 of the peripheral circuit 120 through the row lines RL and is connected to the read and write circuit 122 of the peripheral circuit 120 via the bit lines BL .

The memory cell array 110 includes a plurality of memory blocks BLK1 to BLKz. The plurality of memory blocks BLK1 to BLKz include a plurality of memory cells. In an exemplary embodiment, the plurality of memory cells may be non-volatile memory cells.

The memory cells arranged in the row direction are connected to the word lines among the row lines RL. The memory cells arranged in the column direction are connected to the bit lines BL. For example, memory cells arranged in one column form one cell string, and each cell string will be connected to each bit line.

The erase operation of the semiconductor memory device 100 may be performed on a memory block basis. The program operation and the read operation of the semiconductor memory device 100 may be performed in units of memory cells connected to one word line.

The peripheral circuit 120 includes an address decoder 121, a read and write circuit 122 and control logic 123.

The address decoder 121 is connected to the memory cell array 110 via the row lines RL. The address decoder 121 is configured to operate in response to control of the control logic 123. The address decoder 121 receives an address ADDR from an input / output buffer (not shown) in the external or semiconductor memory device 100.

The address decoder 121 is configured to decode the block address of the received address ADDR. The address decoder 121 will select at least one memory block according to the decoded block address.

The address decoder 121 receives a plurality of pass voltages Vpass, a drain select line voltage Vdsl and a source select line voltage Vssl from the voltage generator 130 when the erase verify operation is performed. The address decoder 121 will control the voltages of the row lines RL. The address decoder 121 will apply the voltages received from the voltage generator 130 to the row lines RL. The drain select line voltage Vdsl will be applied to the drain select line among the row lines RL. The source select line voltage Vssl will be applied to the source select line among the row lines RL. A verify voltage (e.g., ground voltage) will be applied to the selected one of the row lines RL. Then, the non-selected word lines among the row lines RL will be applied with the pass voltages Vpass.

In a program operation or a read operation, the address decoder 121 is configured to decode the row address of the received address ADDR. The address decoder 121 will control the voltages of the row lines RL according to the decoded row address. The address decoder 121 will decode the column address of the received address ADDR and transmit the decoded column address Yi to the read and write circuit 122, for example during a read operation.

In an exemplary embodiment, the address decoder 121 may include a block decoder, a row decoder, a column decoder, an address buffer, and so on.

The read and write circuitry 122 is coupled to the memory cell array 110 via bit lines BL. The read and write circuit 122 operates in response to control of the control logic 123. During the erase verify operation, the read and write circuit 122 senses data from the memory cells of the selected word line through the bit lines BL and determines the path or fail based on the sensed data (DATA).

During a program operation or a read operation, the read and write circuit 122 exchanges data with external or input / output buffers (not shown). At the time of programming, the read and write circuitry 122 receives the data (DATA) and programs the received data (DATA) into the memory cells of the selected word line. In a read operation, the read and write circuit 122 reads data from the memory cells of the selected word line and outputs data (DATA) corresponding to the decoded column address Yi in the read data.

Illustratively, the read and write circuitry 122 may include page buffers (or page registers), column select circuitry, and the like.

The control logic 123 is electrically coupled to the address decoder 121, the read and write circuitry 122 and the voltage generator 130. The control logic 123 is configured to control all operations of the semiconductor memory device 100. In response to the control signal CTRL, the control logic 123 will be configured to control the dress decoder 121, the read and write circuitry 122, and the voltage generator 130.

In an erase verify operation, the control logic 123 receives a signal from the read and write circuit 122 indicating a path or a fail. Based on the received signal, the control logic 123 controls the peripheral circuitry 120 and the voltage generator 130 to redo the erase operation on the selected memory block.

The voltage generator 130 is configured to generate a plurality of voltages using a power supply voltage supplied to the semiconductor memory device 100. [ In the erase verify operation, the voltage generator 130 generates a plurality of pass voltages Vpass, a source select line voltage Vssl, and a drain select line voltage Vdsl. The voltage generator 130 may further generate an erase voltage to be applied to the substrate of the memory cell array 110 during the erase operation. When an erase voltage is applied to the substrate, the address decoder 121 provides a ground voltage to the row lines RL connected to the selected memory block and flaoting the row lines RL connected to the unselected memory block. .

The semiconductor memory device 100 may further include an input / output circuit (not shown). The I / O circuitry will operate in response to control of the control logic 123. The input and output circuit will receive the control signal CTRL and address ADDR from the outside and deliver the received control signal CTRL and address ADDR to the control logic 123 and the address decoder 121 respectively. The input / output circuit may be configured to transfer data (DATA) from the outside to the read / write circuit 122 and to transfer data (DATA) from the read / write circuit 122 to the outside.

In an exemplary embodiment, the semiconductor memory device 100 may be a flash memory.

FIG. 2 is a block diagram showing one of the memory blocks BLK1 to BLKz (BLK1) and the read and write circuit 122 of FIG. 3 is a diagram showing a threshold voltage distribution of memory cells of the memory block BLK1.

Referring to FIGS. 1 and 2, the memory block BLK1 is connected to the read and write circuit 122 through first through m-th bit lines BL1 through BLm. The memory block BLK1 is connected to the address decoder 121 through the common source line CSL, the source select line SSL, the first to the nth word lines WL1 to WLn, and the drain select line DSL. Lt; / RTI > The row lines RL in Fig. 1 include a common source line CSL, a source select line SSL, first to nth word lines WL1 to WLn, and a drain select line DSL.

The memory block BLK1 includes a plurality of memory cells. The memory cells arranged in the column direction are included in one cell string. For example, the first to n-th memory cells M1 to Mn connected to the first bit line BL1 together with the source select transistor SST and the drain select transistor DST constitute one cell string.

Referring to FIG. 3, each of the memory cells of the memory block BLK1 is one of a first state 11 and a second state 12, assuming that each memory cell is a single level cell. By repeatedly applying an erase voltage to the substrate of the memory cell array 110, the memory cells in the second state 12 can be changed to the first state 11.

Every time an erase voltage is applied, an erase verify operation will be performed. 1 and 2, when the erase verify operation is performed, a high-pass voltage Vp is applied to unselected word lines among the first to nth word lines WL1 to WLn, It is assumed that a verify voltage (e.g., ground voltage) is applied. It is assumed that low voltages are applied to the source select line SSL and the drain select line DSL, respectively, so that the source select transistor SST and the drain select transistor DST are turned on. To the common source line CSL, for example, a ground voltage having a low voltage may be applied.

When the high pass voltage Vp is applied to the unselected word lines, the potentials of the body regions of the memory cells M1 to Mn will rise. The source selection transistor SST and the region corresponding to the memory cell adjacent to the source selection transistor SST are driven by a hot carrier in accordance with the lateral electric field between the high potential of the body regions of the memory cells M1 to Mn and the low voltage of the common source line CSL. ) May be generated. Hot carriers can also be generated in accordance with the vertical electric field between the high potential of the body regions of the memory cells M1 to Mn and the low voltage of the source select line SSL. The generated hot carriers are trapped in the insulator of the source select transistor SST and the insulator of the memory cell (for example, MC1 and DM1 in FIG. 8) adjacent thereto and the source select transistor SST and the threshold voltage Unexpectedly.

It is assumed that a low voltage is applied to the first bit line BL1 when the erase verify operation is performed. The drain select transistor DST and the memory cells adjacent thereto (for example, Mn and Fig. 8 (b)) are set in accordance with the lateral electric field between the higher potential of the body regions of the memory cells M1 to Mn and the lower voltage of the first bit line BL1 A hot carrier may be generated in an area corresponding to the DM2 of the second transistor M2. In accordance with the vertical electric field between the raised potential of the body regions of the memory cells M1 to Mn and the low voltage of the drain select line DSL, a hot carrier is applied to the region corresponding to the drain select transistor DST and the memory cell adjacent thereto Lt; / RTI > This hot carrier unintentionally varies the drain select transistor DST and the threshold voltages of the memory cells adjacent thereto.

4 is a table showing an exemplary method of dividing the word lines WL1 to WLn into a plurality of word line groups WLG1 to WLGx. Referring to FIG. 4, the word line WL1 adjacent to the source select line SSL is defined as a first word line group WLG1. The word line WLn adjacent to the drain select line DSL is defined as the xth word line group WLGx. The second to (n-1) th word lines WL2 to WLn-1 are defined as a plurality of word line groups WLG2 to WLGx-1. It will be understood that the manner in which the word lines WL1 to WLn are distinguished is not limited to the embodiment of FIG.

According to an embodiment of the present invention, pass voltages are applied to unselected word lines based on each word line group. This is described in more detail with reference to FIG.

5 is a flowchart showing a method of operating the semiconductor memory device 100 according to an embodiment of the present invention.

1, 2 and 5, in step S110, an erase operation is performed. An erase voltage will be applied to the substrate of the memory cell array 110. [ A ground voltage, for example, will be applied to the word lines WL1 to WLn of the selected memory block (for example, BLK1). The word lines WL1 to WLn of the non-selected memory blocks BLK2 to BLKz will be floated, for example.

In step S120, an erase verify operation may first be performed on memory cells connected to odd word lines (e.g., WL1 and WL3, etc.). At this time, the odd word lines are the selected word lines, and the even word lines (e.g., WL2 and WL4, etc.) will be the unselected word lines. A verify voltage is applied to the selected word lines, pass voltages are applied to the unselected word lines, and an erase verify operation will be performed. Step S120 includes steps S121 and S122.

In step S121, pass voltages set on a word line group basis are applied to unselected word lines (i.e., even word lines), and a verify voltage is applied to selected word lines (i.e., odd word lines) Is performed. That is, different levels of pass voltages are applied to unselected word lines of any one of the plurality of word line groups WLG2 to WLGx-1 and unselected word lines of another word line group Will be. The same pass voltage is applied to the unselected word lines of the same word line group. In an exemplary embodiment, different pass voltages may be applied to unselected word lines of different word line groups.

If it is determined in step S122 that all of the memory cells connected to the selected word lines do not have threshold voltages lower than the verify voltage as a result of sensing through the bit lines BL1 to BLm, step S110 will be performed. Steps S110 and S120 will be repeated until all of the memory cells connected to the selected word lines have threshold voltages lower than the verify voltage.

The erase verify operation for the memory cells connected to the even word lines is performed in the same manner as in step S120. At this time, the even word lines are the selected word lines, and the odd word lines are the unselected word lines. Step S130 includes steps S131 and S132.

In step S131, pass voltages set on a word line group basis are applied to unselected word lines (i.e., odd word lines), and a verify voltage is applied to selected word lines (i.e., even word lines) Is performed.

In step S132, if all the memory cells connected to the selected word lines do not have threshold voltages lower than the verify voltage, step S140 will be performed.

In the description with reference to FIG. 5, it has been described that the erase verify operation for memory cells connected to odd word lines and the erase verify operation for memory cells connected to even word lines are performed sequentially. However, it is to be understood that the present invention is not limited thereto and that the technical idea of the present invention is not limited thereto. That is, for each verify operation, at least one word line is selected and the memory cells coupled to the selected word line will be determined to have threshold voltages lower than the verify voltage. Then, the erase operation will be performed according to the determination result.

According to the embodiment of the present invention, the vertical electric field and the lateral electric field of the region adjacent to the source selection transistor (SST) can be adjusted according to the unselected word lines of the pass voltages set in units of the word line group. As a result, the occurrence of hot carriers in the region adjacent to the source select transistor SST is reduced, and the deterioration phenomenon of the source select transistor SST and memory cells adjacent thereto can be reduced.

In addition, the intensity of the vertical electric field and the side electric field generated in the region adjacent to the drain selection transistor DST can be adjusted. Therefore, generation of hot carriers in the region adjacent to the drain select transistor DST is reduced, and deterioration phenomenon of the drain select transistor DST and memory cells adjacent thereto can be reduced.

Accordingly, a semiconductor memory device 100 that provides improved reliability and a method of operation thereof are provided.

6 is a table showing voltages applied to the word line groups WLG1 to WLGx and the selection lines Vssl and Vdsl.

Referring to FIG. 6, the source select line SSL is applied with the source select line voltage Vssl. A drain select line voltage (Vdsl) is applied to the drain select line (DSL). Then, a ground voltage is applied to selected word lines of each word line group.

The pass voltages applied to the unselected word lines may be divided into word line groups. The same pass voltage will be applied to the unselected word lines of the same word line group. The first pass voltage Vpass1 is applied to the unselected word lines of the first word line group WLG1. And the second pass voltage Vpass2 is applied to the unselected word lines of the second word line group WLG2. And the third pass voltage Vpass3 is applied to the unselected word lines of the third word line group WLG3. The non-selected word lines of the (x-1) th word line group WLGx-1 are applied with the (x-1) th pass voltage Vpassx-1. The non-selected word lines of the xth word line group WLGx are applied with the xth pass voltage Vpassx.

In an exemplary embodiment, the applied pass voltage is higher for a word line group remote from the source select line SSL and the drain select line DSL, lower for a word line group adjacent to the source select line SSL, The word line group adjacent to the DSL may be defined to be lower. In an exemplary embodiment, the source select line voltage Vssl may be less than or equal to the pass voltage (e.g., Vpass1) corresponding to a word line group (e.g., WLG1) adjacent to the source select line SSL . The drain select line voltage Vdsl may be lower than or equal to the pass voltage (e.g., Vpassx) corresponding to the word line group (e.g., WLGx) adjacent to the drain select line DSL. Thus, generation of hot carriers in the region adjacent to the source select transistor SST is reduced, and therefore deterioration of the source select transistor SST and memory cells adjacent thereto can be reduced. In addition, generation of hot carriers in the region adjacent to the drain select transistor DST is reduced, and therefore deterioration phenomenon of the drain select transistor DST and memory cells adjacent thereto can be reduced.

On the other hand, a back pattern defendancy (BPD) effect can be exhibited on the drain select line (DSL) side due to the resistance represented by the memory cells on the source select line (SSL) side. At this time, the current flowing through each cell string may not be stably secured. In order to prevent this, according to another embodiment of the present invention, the applied pass voltage may be defined to be higher for the word line group adjacent to the drain select line (DSL). In addition, by increasing the source selection line voltage Vssl and the drain selection line voltage Vgsl, the current flowing through each cell string can be stably secured. In addition, unselected word lines of the word line group (e.g., WLG1) adjacent to the source select line (SSL) and unselected word lines of the word line group (e.g., WLGx) adjacent to the drain select line (DSL) Lt; / RTI > can be increased.

The memory cells of the word line adjacent to the source select line Vssl can be more easily deteriorated than the memory cells of the word line adjacent to the drain select line Vdsl. For example, if the program operations for the first memory block BLK1 are sequentially performed for the first to nth word lines WL1 to WLn, as the number of times of P / E is increased, More program operations will be performed on adjacent word lines. As a result, the memory cells of the word line adjacent to the source select line Vssl will quickly deteriorate. As a result, the threshold voltages of the memory cells of the word line adjacent to the source select line Vssl can rise. According to an embodiment of the present invention, the drain select line voltage Vdsl may be higher than or equal to the voltage applied to the source select line voltage Vssl. Therefore, the operation performance of the source select transistor SST and the drain select transistor DST in the erase verify operation will be improved.

7 is a table showing another embodiment of a method of dividing the word lines WL1 to WLn into a plurality of word line groups WLG1 to WLGx.

The word lines WL1 to WLn may be classified according to various methods. Referring to FIG. 7, the first to nth word lines WL1 to WLn are divided into first to qth word line groups WLG1 to WLGq in units of three word lines.

FIG. 8 is a circuit diagram showing another embodiment (BLK1 ') of any one of the memory blocks BLK1 to BLKz of FIG.

Referring to FIG. 8, each cell string of the memory block BLK1 'includes first and second dummy memory cells DM1 and DM2. The first dummy memory cell DM1 is disposed between the source select transistor SST and the plurality of memory cells M1 to Mn. The first dummy word line DWL1 for controlling the first dummy memory cell DM1 will be disposed between the source select line SSL and the word lines WL1 to WLn. The second dummy memory cell DM2 is disposed between the plurality of memory cells M1 to Mn and the drain select transistor DST. The second dummy word line DWL2 for controlling the second dummy memory cell DM2 will be disposed between the word lines WL1 to WLn and the drain select line DSL.

9 is a table showing voltages applied to the word line groups WLG1 to WLGx and the selection lines Vssl and Vdsl and the dummy word lines DWL1 and DWL2.

Referring to FIG. 9, first and second dummy word line voltages Vdwl1 and Vdwl2 are applied to the first and second dummy word lines DWL1 and DWL2, respectively.

As described with reference to Fig. 6, the pass voltage is higher for the word line group far from the source select line SSL and the drain select line DSL, lower for the word line group adjacent to the source select line SSL, The word line group adjacent to the selected line (DSL) may be set lower. Additionally, the first dummy word line voltage Vdwl1 may be less than or equal to the pass voltage (e.g., Vpassl) corresponding to the word line group (e.g., WLGl) adjacent to the first dummy word line DWLl . The second dummy word line voltage Vdwl2 may be less than or equal to the pass voltage (e.g., Vpassx) corresponding to the word line group (e.g., WLGx) adjacent to the second dummy word line DWL2. At this time, the source select line voltage Vssl may be lower than or equal to the first dummy word line voltage Vdwl1. The drain select line voltage Vdsl may be lower than or equal to the second dummy word line voltage Vdwl2. Accordingly, generation of hot carriers in the regions adjacent to the source selection transistor (SST) and the drain selection transistor will be reduced. Therefore, deterioration phenomenon of the memory cells adjacent to the source selection transistor (SST), the first dummy memory cell (DM1) and the first dummy memory cell (DM1) will be reduced. The deterioration phenomenon of the memory cells adjacent to the drain select transistor DST, the second dummy memory cell DM2 and the first dummy memory cell DM1 will be reduced.

As another embodiment, the first and second dummy word line voltages Vdwl1 and Vdwl2 may be increased to stably secure the current flowing through each cell string. For example, the first dummy word line voltage (Vdwl1) is higher than the pass voltage corresponding to the word line group adjacent to the first dummy word line (DWL1) and the second dummy word line voltage (Vdwl2) May be higher than the pass voltage corresponding to the word line group adjacent to the word line DWL2. In an exemplary embodiment, the second dummy word line voltage (Vdwl2) may be higher than or equal to the first dummy word line voltage (Vdwl1).

10 is a block diagram showing one of the memory blocks BLK1 to BLKz of FIG. 1 (BLK1) and another embodiment 122 'of the read and write circuit 122. FIG.

Referring to FIG. 10, the memory block BLK1 is connected to the read and write circuit 122 'through even bit lines EBL1 to EBLr and odd bit lines OBL1 to OBLr. The read and write circuit 122 'includes first through r page buffers PB1 through PBr.

The erase verify operation for the memory cells connected to the odd word lines is performed by the first erase verify operation based on the data sensed through the even bit lines EBL1 to EBLr and the odd bit lines OBL1 to OBLr (Hereinafter, referred to as " odd sensing ") through the second erase verify operation. In the first erase verify operation, it is determined whether a pass or a fail occurs based on the data that is sensed at the even moment, and the erase operation will be performed again according to the determination result. In the second erase verify operation, whether or not a pass or a fail is determined based on the data sensed by the odd operation, and the erase operation will be performed again according to the determination result. In each of the first and second erase verify operations, a verify voltage is applied to the odd word lines and pass voltages are applied to the even word lines.

The erase verify operation for memory cells connected to odd word lines will also be performed in the same manner as the erase verify operation for memory cells connected to odd word lines.

11 is a table showing an exemplary method of dividing the word lines WL1 to WLn into a plurality of word line groups WLG1 to WLGx when the even sensing and the odd sensing are performed, respectively.

Referring to FIG. 11, when the even sensing and the odd sensing are respectively performed, the word lines WL1 to WLn are divided into a plurality of word line groups WLG1 to WLGx or WLG1 to WLGq. The grouping of the word lines WL1 to WLn at the time of even sensing and the grouping of the word lines WL1 to WLn at the time of the odd sensing may be different. That is, word line groups WLG1 to WLGx classified during even sensing and word line groups WLG1 to WLGq classified during od sensing may be different. In another embodiment, the word lines WL1 to WLn may be separated into the same word line groups in even sensing and odd sensing, respectively.

5 to 9, when each sensing operation is performed, a path voltage Vs applied to unselected word lines of any one of the word line groups WLG1 to WLGx or WLG1 to WLGq And the non-selected word lines of the other word line group will be different from each other.

12 is a block diagram illustrating a memory system 1000 that includes a semiconductor memory device 1100. In FIG.

12, the memory system 1000 includes a semiconductor memory device 1100 and a controller 1200. [

The semiconductor memory device 1100 will be configured and operated similarly to the semiconductor memory device 100 described with reference to Figs.

The controller 1200 is connected to the host (Host) and the semiconductor memory device 1100. In response to a request from the host (Host), the controller 1200 is configured to access the semiconductor memory device 1100. For example, the controller 1200 is configured to control the read, write, erase, and background operations of the semiconductor memory device 1100. The controller 1200 is configured to provide an interface between the semiconductor memory device 1100 and the host. The controller 1200 is configured to drive firmware for controlling the semiconductor memory device 1100.

Illustratively, the controller 1200 includes components such as a random access memory (RAM), a processing unit, a host interface, and a memory interface.

The RAM is used as at least one of an operation memory of the processing unit, a cache memory between the semiconductor memory device 1100 and the host, and a buffer memory between the semiconductor memory device 1100 and the host.

The processing unit controls all operations of the controller 1200.

The host interface includes a protocol for performing data exchange between the host (Host) and the controller 1200. Illustratively, the controller 1200 may be implemented using any of a variety of communication protocols, such as a Universal Serial Bus (USB) protocol, a multimedia card (MMC) protocol, a peripheral component interconnection (PCI) protocol, a PCI- (Host) interface through at least one of various interface protocols such as a Serial-ATA protocol, a Parallel-ATA protocol, a small computer small interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, . The memory interface interfaces with the semiconductor memory device 1100. For example, the memory interface includes a NAND interface or a NOR interface.

The memory system 1000 may be further configured to include error correction blocks. The error correction block is configured to detect and correct errors in data read from the semiconductor memory device 1100 using an error correction code (ECC). Illustratively, the error correction block is provided as a component of the controller 1200. As another example, the error correction block may be provided as a component of the semiconductor memory device 1100.

The controller 1200 and semiconductor memory device 1100 may be integrated into one semiconductor device. Illustratively, the controller 1200 and semiconductor memory device 1100 may be integrated into one semiconductor device to form a memory card. For example, the controller 1200 and the semiconductor memory device 1100 may be integrated into a single semiconductor device and may be a PC card (PCMCIA), a compact flash card (CF), a smart media card (SM, SMC ), A memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), and a universal flash memory device (UFS).

The controller 1200 and the semiconductor memory device 1100 may be integrated into a single semiconductor device to form a solid state drive (SSD). A semiconductor drive (SSD) includes a storage device configured to store data in a semiconductor memory. When the memory system 1000 is used as a semiconductor drive (SSD), the operating speed of the host connected to the memory system 1000 is dramatically improved.

As another example, the memory system 1000 may be a computer, a UMPC (Ultra Mobile PC), a workstation, a netbook, a PDA (Personal Digital Assistants), a portable computer, a web tablet, A mobile phone, a smart phone, an e-book, a portable multimedia player (PMP), a portable game machine, a navigation device, a black box A digital camera, a digital camera, a 3-dimensional television, a digital audio recorder, a digital audio player, a digital picture recorder, a digital picture player, a digital video recorder, a digital video player, a device capable of transmitting and receiving information in a wireless environment, one of various electronic devices constituting a home network, Ha Is provided as one of various components of an electronic device, such as one of a variety of electronic devices, one of various electronic devices that make up a telematics network, an RFID device, or one of various components that make up a computing system.

Illustratively, semiconductor memory device 1100 or memory system 1000 may be implemented in various types of packages. For example, the semiconductor memory device 1100 or the memory system 1000 may include a package on package (PoP), ball grid arrays (BGAs), chip scale packages (CSPs), plastic leaded chip carriers (PDIP), Die in Waffle Pack, Die in Wafer Form, Chip On Board (COB), Ceramic Dual In Line Package (CERDIP), Plastic Metric Quad Flat Pack (MQFP), Thin Quad Flatpack SOIC), Shrink Small Outline Package (SSOP), Thin Small Outline (TSOP), Thin Quad Flatpack (TQFP), System In Package (SIP), Multi Chip Package (MCP), Wafer-level Fabricated Package Level Processed Stack Package (WSP) or the like.

FIG. 13 is a block diagram illustrating a computing system 2000 including the memory system 1000 of FIG.

13, a computing system 2000 includes a central processing unit 2100, a random access memory (RAM) 2200, a user interface 2300, a power supply 2400, and a memory system 1000 .

The memory system 1000 is electrically coupled to the central processing unit 2100, the RAM 2200, the user interface 2300, and the power source 2400 via the system bus 2500. Data that is provided through the user interface 2300 or processed by the central processing unit 2100 is stored in the memory system 1000.

13, the semiconductor memory device 1100 is shown connected to the system bus 2500 through a controller 1200. However, the semiconductor memory device 1100 can be configured to be connected directly to the system bus 2500. At this time, the function of the controller 1200 will be performed by the central processing unit 2100.

While the invention has been shown and described with reference to certain preferred embodiments thereof, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention. Therefore, the scope of the present invention should not be limited to the above-described embodiments, but should be determined by the equivalents of the claims of the present invention as well as the claims of the following.

110: memory cell array
120: peripheral circuit
130: Voltage generator
WL1 to WLn: word lines
WLG1 to WLGx, WLG1 to WLGq: word line groups

Claims (20)

Performing an erase operation on the memory block;
After performing the erase operation, a verify voltage is applied to at least one selected word line of the word lines connected to the memory block, and pass voltages are applied to unselected word lines of the word lines to perform an erase verify operation However,
Wherein the word lines are divided into a plurality of word line groups and the non-selected word lines of the first word line group of the plurality of word line groups and the non-selected word lines of the second word line group of the plurality of word line groups And different levels of pass voltages are applied to the word lines. The method according to claim 1,
Wherein different pass voltages are applied to non-selected word lines of different word line groups. The method according to claim 1,
And the same pass voltage is applied to non-selected word lines of the same word line group. The method according to claim 1,
The memory block is connected to a source select line and a drain select line,
Wherein the word lines are disposed between the source select line and the drain select line. 5. The method of claim 4,
The second word line group being disposed adjacent to the drain select line than the first word line group,
Wherein a pass voltage applied to unselected word lines of the second word line group is higher than unselected word lines of the first word line group. 6. The method of claim 5,
Wherein the memory block is coupled to a dummy word line disposed between the word lines and the drain select line,
Wherein a voltage applied to the dummy word line is higher than or equal to a pass voltage applied to unselected word lines of the second word line group. 5. The method of claim 4,
The first word line group being disposed adjacent to the source select line than the second word line group,
The memory block being connected to a dummy word line disposed between the source select line and the word lines,
Wherein a voltage applied to the dummy word line is higher than or equal to a pass voltage applied to unselected word lines of the first word line group. 5. The method of claim 4,
Wherein the memory block is further connected to a first dummy word line disposed between the source select line and the word lines and a second dummy word line disposed between the word lines and the drain select line,
Wherein a voltage applied to the second dummy word line is higher than a voltage applied to the first dummy word line. 5. The method of claim 4,
Wherein a voltage applied to the drain select line is higher than or equal to a voltage applied to the source select line. 5. The method of claim 4,
The first word line group being disposed adjacent to the source select line than the second word line group,
Wherein a third word line group of the plurality of word line groups is disposed adjacent to the drain select line than the second word line group,
The pass voltage applied to the unselected word lines of the first word line group is lower than the unselected word lines of the second word line group,
Wherein a pass voltage applied to unselected word lines of the third word line group is lower than unselected word lines of the second word line group. 11. The method of claim 10,
Wherein a voltage applied to the source select line is equal to or lower than a pass voltage applied to unselected word lines of the first word line group,
Wherein a voltage applied to the drain select line is lower than a pass voltage applied to unselected word lines of the third word line group. 11. The method of claim 10,
The memory block being connected to a dummy word line disposed between the source select line and the word lines,
Wherein a dummy word line voltage applied to the dummy word line is equal to or lower than a pass voltage applied to unselected word lines of the first word line group,
Wherein a voltage applied to the source select line is lower than or equal to the dummy word line voltage. 11. The method of claim 10,
Wherein the memory block is coupled to the drain select line and a dummy word line disposed between the word lines,
Wherein a voltage applied to the dummy word line is equal to or lower than a pass voltage applied to unselected word lines of the third word line group,
Wherein a voltage applied to the drain select line is lower than or equal to the dummy word line voltage. A method of operating a semiconductor memory device comprising a memory block coupled to first and second bit lines, the method comprising:
Performing an erase operation on the memory block;
Perform a first erase verify operation based on data read through the first bit lines;
And performing a second erase verify operation based on data read through the second bit lines,
The word lines connected to the memory block are divided into a plurality of word line groups,
Wherein when each of the first and second erase verify operations is performed, the non-selected word lines of the first word line group and the second word line group of the plurality of word line groups of the plurality of word line groups And pass voltages of different levels are applied to the unselected word lines. 15. The method of claim 14,
Wherein the word line groups separated during the first erase verify operation and the word line groups separated during the second erase verify operation are different. 15. The method of claim 14,
Wherein the word line groups separated during the first erase verify operation and the word line groups separated during the second erase verify operation are the same. 15. The method of claim 14,
Wherein the first bit lines and the second bit lines are alternately arranged. A memory cell array including at least one memory block coupled to word lines; And
A peripheral circuit configured to apply a verify voltage to at least one selected word line of the word lines and to apply an erase verify operation by applying a plurality of pass voltages to unselected word lines of the word lines,
The word lines are divided into a plurality of word line groups,
Wherein the peripheral circuitry is operable to write to non-selected word lines of a first word line group of the plurality of word line groups and non-selected word lines of a second word line group of the plurality of word line groups And to apply different levels of pass voltages. 19. The method of claim 18,
Wherein different pass voltages are applied to non-selected word lines of different word line groups. 19. The method of claim 18,
And the same pass voltage is applied to the unselected word lines of the same word line group.

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