KR101844927B1 - Digital delay-locked loop using a lock-in pre-search algorithm and method for controlling the same - Google Patents

Abstract

The present invention relates to a digital delay-locked loop circuit using a lock-in pre-search (LSP) algorithm and a control method thereof. The circuit comprises: a digital control delay line consisting of a coarse delay line and a fine delay line and reducing a phase error between an input clock signal and an output clock signal to within a predetermined delay resolution; and a control logic for a digital control delay line controlling a digital delay line to operate the digital delay-locked loop circuit in one of an LSP mode, a binary search (BS) mode, and a sequential search mode. Moreover, the LSP mode searches for a proximity locking point while monotonically increasing delay of the coarse delay line.

Description

[0001] The present invention relates to a digital delay locked loop circuit using a lock-in pre-search search algorithm and a control method thereof,

The present invention relates to a digital delay locked loop circuit and a control method thereof, and more particularly, to a low-cost broadband full digital delay locked loop circuit and its control method that can be used for both DDR3 and DDR4 SDRAMs by using a lock-in pre- ≪ / RTI >

In the case of high-speed integrated circuits such as DRAMs, microprocessors, and communication chips, a delay locked loop (DLL) or phase locked loop (I / O) interface is used between the chip and the chip to improve power consumption and data transmission speed PLL: Phase Locked Loop). The delay locked loop circuit is generally divided into two types, an analog delay locked loop circuit and a digital delay locked loop circuit, depending on the type of feedback loop that adjusts the delay amount. The analog delay locked loop circuit uses a method of storing control information for adjusting the delay amount in a capacitor of the feedback loop. In general, the analog delay locked loop circuit has a simple structure, accurate delay control capability and good jitter characteristics. However, due to its sensitivity to process changes in analog circuits, it is not portable easily due to its low portability and is sensitive to control signal noise. Moreover, it is difficult to have a wide operating frequency due to a long locking time.

On the other hand, since the digital delay locked loop circuit uses the method of storing the delay amount adjustment control information as digital bits through the finite state machine in the feedback loop, it is resistant to the control signal noise and insensitive to the digital block process change, . In addition, it can have a relatively fast locking time and a wide operating frequency characteristic as compared with the analog method. However, unlike the analog delay locked loop circuit which uses continuous analog control information, since the discrete digital control information is used, the resolution of the adjustable delay amount is low and the accurate delay adjustment is impossible.

Recently, DDR3 and DDR4 SDRAMs are widely used as low-cost main memory solutions for personal computers, servers and other embedded system applications. One of the key challenges in DDR3 and DDR4 SDRAM designs is to implement a low cost, fully digital delay locked loop circuit capable of operating in the 0.3 GHz to 1.6 GHz wideband frequency range. DDR3 and DDR4 delay locked loop circuits (DLLs) require less than 512 clock cycles of fast locking time and supply voltages of 1.2 V or less, while meeting the small footprint, low power consumption and low jitter characteristics required.

Although many digital delay locked loop circuits have been introduced for DDR3 and DDR4, only a few delay locked loop circuits can simultaneously satisfy the frequency ranges of DDR3 and DDR4. Since the DDRx SDRAM has a long clock distribution network (CDN), which is connected to the output drivers DQs of the SDRAM, the replica clock path (RCP) located in the feedback path of the delay locked loop circuit path) must be considered in the design of a delay locked loop circuit for skew destruction. Unfortunately, many delay locked loop circuits do not consider RCP overhead in architectural design. Moreover, the harmonic lock problem must be eliminated to reduce power consumption and clock jitter.

Korean Patent No. 10054391

SUMMARY OF THE INVENTION It is an object of the present invention to provide a low-cost wideband full digital delay locked loop circuit which can be used for both DDR3 and DDR4 SDRAMs using a lock-in pre-search search algorithm, And to provide a control method thereof.

According to an exemplary embodiment of the present invention, a digital control delay line, consisting of a coarse delay line and a fine delay line, for reducing a phase error between an input clock signal and an output clock signal to within a predetermined delay resolution; And a digital control delay line control logic for controlling the digital delay line to operate the digital delay locked loop circuit in either a lock-in pre-search (LSP) mode, a binary search (BS) mode or a sequential search mode , And the lock-in pre-search (LSP) mode provides a digital delay locked loop circuit using a pre-search search algorithm that is a lock for searching for a near-lock point while monotonically increasing the delay of the co-

The coarse delay line is composed of a plurality of delay elements, and the lock-in pre-search mode changes the number of active delay elements of the coarse delay line to monotonously increase the delay of the coarse delay line to search for a near lock point.

Wherein the digital control delay control logic comprises: a ring counter for applying a control signal to the successive approximation register to control operation of a lock-in pre-search mode for retrieving a proximity lock point; And a successive approximation register that performs the function of operating the coarse delay line in a lock-in pre-search mode or in a binary search mode after a lock-in pre-search mode.

The successive approximation register is converted to a sequential counter after the locking to perform sequential retrieval.

The successive approximation register compares the output signal of the frequency divider with the phase comparison signal of the phase detector and then generates a binary search mode enable signal for switching from the lock-in pre-search mode to the binary search mode, And further includes a mode control block for applying to the approximate register.

Wherein the successive approximation register further comprises a decoder for converting the output digital bits of the successive approximation register into a code applied to the coarse delay line, wherein the output signal of the decoder controls the number of active delay elements of the coarse delay line Function.

Wherein the binary search (BS) mode, after completion of the lock-in pre-search mode, performs a binary search on the successive approximation register to remove phase errors of the input clock signal and the output clock signal within a second reference resolution, Performs a sequential search by converting the successive approximation register to a sequential counter after the binary search mode.

The digital delay locked loop circuit using the lock-in pre-search search algorithm further includes a frequency divider that divides the frequency of the input clock signal and applies the divided clock signal to the ring counter of the digital control delay line control logic.

The digital delay locked loop circuit using the lock-in pre-search search algorithm further includes a phase detector for comparing the phase between the input clock signal and the output clock signal to generate a phase comparison signal, Register, and controls the output digital bits of the successive approximation register.

According to another aspect of the present invention, the operation of the lock-in pre-search mode is started and the phase error of the input clock signal and the output clock signal is removed to within the first reference resolution while monotonically increasing the delay of the co- ; Determining whether a phase error between an input clock signal and an output clock signal is eliminated within a first reference delay resolution; And if it is determined that the phase error between the input clock signal and the output clock signal has been eliminated within the first reference delay resolution, the phase error in the input clock signal and the output clock signal goes to the binary reference mode, And returning to the lock-in pre-search mode if the lock-in pre-search is not performed within the lock-in pre-search mode.

The control method comprising: after the successive approximation register performs a binary search, determining whether a phase error between an input clock signal and an output clock signal is eliminated within a second reference delay resolution; And if it is determined that the phase error between the input clock signal and the output clock signal is not eliminated within the second reference delay resolution, the successive approximation register is converted to a sequential counter to perform the sequential search.

The coarse delay line is composed of a plurality of delay elements, and changes the number of active delay elements to monotonously increase the delay of the coarse delay line while searching for a near-lock point.

According to the present invention using the lock-in pre-search algorithm, a broadband frequency range and high-speed locking capability can be obtained without a hanock lock problem, and thus a low-cost wideband full digital delay locked loop circuit that can be used for both DDR3 and DDR4 SDRAM is provided .

The lock-in pre-search algorithm proposed in the present invention is simple, robust against noise, and has an effect of being able to search for a near-locking point very easily.

1 is a schematic block diagram of a digital delay locked loop circuit using a lock-in pre-search search algorithm according to an embodiment of the present invention.
2 shows an initial locking process of a digital delay locked loop circuit according to this embodiment using a lock-in pre-search (LPS) and a binary search (BS) mode.
3 is a diagram showing in more detail the operation of the lock-in pre-search (LPS) mode.
Figures 4 and 5 show the measured locking process of the delay locked loop circuit.
6 is a flowchart illustrating a method of controlling a digital delay locked loop circuit using a lock-in pre-search search algorithm according to the present invention.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a schematic block diagram of a digital delay locked loop circuit using a lock-in pre-search search algorithm according to an embodiment of the present invention.

Referring to FIG. 1, a digital delay locked loop circuit using a lock-in pre-search search algorithm according to the present embodiment includes a digitally controlled delay line (DCDL) 100, a digital control delay line control logic 200, A frequency divider 300, and a phase detector 400.

A digitally controlled delay line (DCDL) (100) is a function of the input clock signal (CLK _IN) to the input received, reduced to within a phase error between the input clock signal (CLK _IN) and an output clock signal (CLK _OUT) predetermined delay resolution .

The digital control delay line (DCDL) 100 is composed of a coarse delay line (CDL) 110 and a fine delay line (FDL)

The coarse delay line (CDL) 110 is composed of a plurality of delay elements. The coarse delay line (CDL) 110 changes the number of active delay elements to monotonously increase the delay of the coarse delay line while searching for a near lock point.

The fine delay line (FDL) 120 is provided at the subsequent stage of the coarse delay line (CDL) 110 and has a relatively small unit delay time as compared with the unit delay time of the coarse delay line.

The frequency divider 300 divides the frequency of the input clock signal CLK _IN and applies the divided clock signal to the ring counter of the digital control delay line control logic. In this embodiment, the frequency divider 300 uses a 1/4 frequency divider, and the output clock CLK ₄ of the frequency divider is applied to the ring counter.

The phase detector 400 compares the phase between the input clock signal CLK _IN and the output clock signal CLK _OUT to generate a phase comparison signal Comp. This phase comparison signal (Comp) is input to the successive approximation register and controls the output digital bit of the successive approximation register.

The digital control delay line control logic 200 has the function of controlling the digital control delay line so that the digital delay locked loop circuit operates in either a lock-in pre-search (LSP) mode, a binary search (BS) .

The lock-in pre-search (LSP) mode is a mode for searching for a near-lock point by removing the phase error between the input clock signal and the output clock signal within the first reference resolution while monotonically increasing the delay of the co-

The binary search (BS) mode is a mode in which, after completion of the lock-in pre-search mode, the successive approximation register performs a binary search to remove the phase error of the input clock signal and the output clock signal within the second reference resolution.

The sequential search mode is a mode for performing a sequential search by converting a successive approximation register to a sequential counter after the binary search mode.

The digital control delay line control logic 200 includes a ring counter 210, a successive approximation register (SAR) 220, a mode control block 230 and a decoder 240.

The ring counter 210 applies a control signal to the successive approximation register 220 to control the operation of the lock-in pre-search mode for searching for a near-lock point.

In this embodiment, the ring counter 210 uses a 4-bit ring counter, but the number of bits is not limited thereto. In the case of the present embodiment, the 4-bit ring counter controls R [3: 0] in five steps from [0000] to [1000] so as to search for a near lock point.

The successive approximation register 220 has a function of operating the coarse delay line in the lock-in pre-search mode according to the ring counter control signal, or in the binary search mode according to the control signal of the mode control block after the lock- . Then, after locking, the successive approximation register is converted into a sequential counter to perform sequential retrieval.

In the present embodiment, the successive approximation register is described as using a 9-bit successive approximation register, but the number of bits is not limited thereto.

Mode control block 230 is compared to the phase comparison signal (Comp) of the output clock signal (CLK ₄₎ and the phase detector 400 of the frequency divider 300, the phase error of the input clock signal and the output clock signal of claim 1, The binary search mode enable signal BSM _EN for terminating the lock-in pre-search mode and switching to the binary search mode is generated and applied to the successive approximation register.

The decoder 240 functions to convert the output digital bits of the successive approximation register 220 into a code suitable for the coarse delay line. In this embodiment, a 5-to-32 thermometer decoder is used as a decoder. The output signal of the decoder 240 controls the number of active delay elements of the coarse delay line.

According to the present invention using the lock-in pre-search algorithm, a broadband frequency range and high-speed locking capability can be obtained without a hanock lock problem, and thus a low-cost wideband full digital delay locked loop circuit that can be used for both DDR3 and DDR4 SDRAM is provided .

2 shows an initial locking process of a digital delay locked loop circuit according to this embodiment using a lock-in pre-search (LPS) and a binary search (BS) mode.

When the digital delay locked loop circuit starts to operate, the lock-in pre-search (LPS) mode is executed first. The DCDL control logic searches for a proximity locking point by changing R [3: 0] in five steps from a [0000] to a [1000] 4-bit ring-counter as shown in FIG.

The R [3: 0] code bit is set to 4 MSB, S [8: 5] of the 9-bit successive approximation register (SAR), at every rising edge of CLK ₄ with the 1/4 frequency of the input clock (CLK _IN ) Lt; / RTI > Then, the 5 MSB of the successive approximation register (SAR), S [8: 4] is converted to the thermometer code C [31: 0] by a 5-to- 32 decoder having an initial value of S [ .

3 is a diagram showing in more detail the operation of the lock-in pre-search (LPS) mode.

The coarse delay line is composed of 32 cascaded NAND-based delay elements (DE), and the C [31: 0] bits are used to control the number of active delay elements. According to the C [31: 0] bits, the number of active delay elements changes from 1 (step 1) to 16 (step 5). The lock-in pre-search (LPS) algorithm is simple and insensitive to supply noise. Using this algorithm, the harmonic locking problem can be avoided because the coarse delay line (CDL) delay monotonically increases within five steps before normal operation, thereby finding the locking point.

Referring to FIGS. 2 and 3, a delay locked loop circuit (DLL) is configured to have one active delay when the control codes codes R [3: 0] = [0000] and S [8: 4] = [00001] And starts with the element DE (# 1).

In step 1, the position of the output clock (CLK _OUT ) is the A point as shown in Fig. Since the output clock CLK _OUT leads the input clock CLK _IN at this point A, the output signal Comp of the phase detector PD maintains a low, which means that the delay locked loop circuit (DLL) , It is necessary to increase the delay of the digital control delay line (DCDL). Thus, the ring-counter has the following sequence by increasing the number of active delay elements to 2 (# 1 and # 2) with R [3: 0] = [0001] and S [8: 4] = [00010] 2, and as a result, the position of the output clock (CLK _OUT ) is shifted to point B.

The LPS mode shifts to step 3 (S [8: 4] = [00100]) since the output signal Comp of the phase detector PD is still held low in step 2, The number of elements is 4 (# 1 to # 4), and the position of the output clock (CLK _OUT ) is the C point.

Lock the pre-search (LPS) mode are eight active delay elements (# 1 to # 8) to have Step 4: when moved to (S [8 4] = [ 01000]), location of the output clock (CLK _OUT) is D, and the output signal Comp of the phase detector PD is high. This means that the output clock (CLK _OUT ) lags the input clock (CLK _IN ) and the appropriate locking point is located between C and D.

Then, the binary search mode enable (BSM _EN ) signal goes high, which causes clock CLK ₄ (LPS) mode is completed by resetting the S [8: 4] bits at the rising edge of the lock-in pre-search (LPS) to the previous state (= Step 3 with S [8: 4] = [00100])) And executes the search (BS) mode.

Since S [k] is "1" and k = 7, only 6 LSB, S [5: 0] are used to control binary search. After the binary search mode, the 9-bit successive approximation register (SAR) is converted to a sequential counter, the delay locked loop circuit performs a sequential search and maintains a closed loop to maintain fine phase lock. The variable transfer delay of the fine delay line (FDL) is controlled by the 4 LSB, S [3: 0] of the successive approximation register (SAR).

To support the DDR3 and DDR4 frequency bands (0.3 to 1.6 GHz), the delay of the programmable delay locked loop circuit needs to be in the range of 0.625 ns to 3.33 ns. When the propagation delay value of the delay element is ( t _DE ), the programmable delay amount of the fine delay line is 1, resulting in a small delay resolution of t _DE / 2 ⁴ .

The lock-in pre-search (LPS) mode allows up to 5 CLK ₄ Cycle, and binary search (BS) mode requires up to 8 CLK ₄ Cycle is required.

Figure 4 shows the measured locking process of the delay locked loop circuit, where the lock-in pre-search (LPS) mode takes 4 input clock cycles and the binary search (BS) mode takes 4 cycles.

After locking, the delay locked loop circuit maintains a lock-in state in sequential mode.

As shown in FIG. 5, the measured peak-to-peak output clock jitter is 7.0 ps at 2.2 GHz.

Compared to the prior art DDR3 / DDR4 delay locked loop circuit as shown in Table 1, the proposed delay locked loop circuit maintains a fast locking time of 52 cycles without harmonic lock problems, And consumes a low level of power.

Conventional 1 Conventional 2 Conventional 3 Conventional 4 Invention Application DDR3 DDR3 DDR4 DDR
3 & 4 DDR
3 & 4 Process & Supply 45nm
1.1V 65nm
1.1V 30 nm
1.14V 65nm
1.2V 130nm
1.2V Active area (mm ² ) 0.01 0.017 N / A 0.04 0.046 Frequency range (GHz) 0.4-0.8 0.4-0.8 1.65 0.12-2.0 0.15-2.2 Locking time (cycles) N / A 41 500 N / A 52 Anti-harmonic Lock O O X O O pp jitter (ps)
@ GHz 17.8
@ 0.8 26.1
@ 0.8 <50 ps
@ 1.3 14
@2 7
@ 2.2 Power (mW @ GHz) 3.3
@ 0.8 3.52
@ 0.8 N / A 6.6
@2 3.1
@One

6 is a flowchart illustrating a method of controlling a digital delay locked loop circuit using a lock-in pre-search search algorithm according to the present invention.

The digital delay locked loop circuit according to the present embodiment operates in a lock-in pre-search mode, a binary search mode, and a sequential search mode.

First, the operation in the lock-in pre-search mode is started (S110).

(S120) a step of removing the phase error of the input clock signal and the output clock signal within the first reference resolution and searching for the near-lock point while monotonously increasing the delay of the coarse delay line. At this time, the coarse delay line is composed of a plurality of delay elements, and performs a function of changing the number of active delay elements to monotonously increase the delay of the coarse delay line while searching for the nearer locking point.

In operation S130, it is determined whether the search of the near lock point is completed, that is, the phase error between the input clock signal and the output clock signal is eliminated within the first reference delay resolution.

As a result of the determination, if the phase error between the input clock signal and the output clock signal is removed within the first reference delay resolution, that is, when the operation of the lock-in pre-search mode is completed, the binary search mode is advanced (S140). The successive approximation register performs a binary search to remove phase errors of the input clock signal and the output clock signal within a second reference resolution.

On the other hand, if the phase error between the input clock signal and the output clock signal is not eliminated within the first reference delay resolution, the operation returns to step S120, i.e., the lock-in pre-search mode operation step to execute the lock-in pre-search mode.

After step S140, a process of determining whether the phase error between the input clock signal and the output clock signal is eliminated within the second reference delay resolution is performed (S150).

As a result of the determination, if the phase error between the input clock signal and the output clock signal is not eliminated within the second reference delay resolution, the successive approximation register is converted into a sequential counter to perform sequential search (S160).

The delay locked loop circuit according to the present invention adopts a new lock-in pre-search (LPS) mode, so that the delay locked loop circuit can obtain a broadband operating frequency without causing a harmonic lock problem. The proposed lock-in pre-search (LPS) algorithm is very simple, effective for searching for near-lock points before normal binary search tracking, robust to noise, harmonic lock avoidance and broadband frequency operation.

As a result, the proposed fully digital delay locked loop circuit can be easily applied to DDR3 and DDR4 SDRAMs.

The above description is only an exemplary embodiment of the digital delay locked loop circuit and the control method thereof using the lock-in pre-search search algorithm according to the present invention, and the present invention is not limited to the above- It will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined in the appended claims.

100: Digital Control Delay Line (DCDL)
200: Digital control delay line control logic
210: Ring Counter
220: successive approximation register (SAR)
230: Mode control block
240: decoder
300: frequency divider
400: phase detector

Claims (12)

A digital control delay line consisting of a coarse delay line and a fine delay line for reducing a phase error between an input clock signal and an output clock signal to within a predetermined delay resolution; And
And digital control delay line control logic for controlling the digital delay line to operate the digital delay locked loop circuit in either a lock-in-pre-search (LSP) mode, a binary search (BS) mode or a sequential search mode,
Wherein the digital control delay line control logic comprises:
The phase of the input clock signal and the phase of the output clock signal is removed to within the first reference resolution to search for the near lock point to perform the lock-in pre-search mode operation while monotonously increasing the delay of the co-
The phase error between the input clock signal and the output clock signal is eliminated within the first reference delay resolution and the binary search mode is entered when the operation of the lock-in pre-search mode is completed,
Wherein if the phase error is not eliminated within the first reference delay resolution, control is returned to a lock-in pre-search mode operation step to execute a lock-in pre-search mode. Loop circuit.
The method according to claim 1,
The coarse delay line is composed of a plurality of delay elements. The lock-in pre-search mode changes the number of active delay elements of the coarse delay line to monotonously increase the delay of the coarse delay line, A digital delay locked loop circuit using a lock-in pre-search search algorithm.
The method according to claim 1,
Wherein the digital control delay line control logic comprises:
A ring counter for applying a control signal to the successive approximation register to control operation of a lock-in pre-search mode for searching for a proximity locking point; And
And a successive approximation register that performs a function of operating the coarse delay line in a lock-in pre-search mode or in a binary search mode after a lock-in pre-search mode. Digital delay locked loop circuit using.
The method of claim 3,
Wherein the successive approximation register is converted into a sequential counter after locking to perform sequential retrieval. The digital delay locked loop circuit using the lock-in pre-search search algorithm.
The method of claim 3,
Wherein the successive approximation register comprises:
After the output signal of the frequency divider is compared with the phase comparison signal of the phase detector, a binary search mode enable signal for switching the binary search mode to the lock-in pre-search mode is generated and applied to the successive approximation register And a mode control block. The digital delay locked loop circuit uses a lock-in pre-search search algorithm.
The method of claim 3,
Wherein the successive approximation register comprises:
And a decoder for converting the output digital bits of the successive approximation register into a code applied to the coarse delay line, wherein the output signal of the decoder controls a change in the number of active delay elements of the coarse delay line A digital delay locked loop circuit using a lock-in pre-search search algorithm.
The method according to claim 1,
The binary search (BS) mode, after completion of the lock-in pre-search mode, the successive approximation register performs a binary search to remove phase errors of the input clock signal and the output clock signal within a second reference resolution,
Wherein the sequential search mode is a sequential search mode in which a successive approximation register is converted into a sequential counter after a binary search mode to perform a sequential search.
The method of claim 3,
The digital delay locked loop circuit using the lock-in pre-
Further comprising a frequency divider that divides the frequency of the input clock signal and applies the divided clock signal to the ring counter of the digital control delay line control logic. .
The method of claim 3,
The digital delay locked loop circuit using the lock-in pre-
Further comprising a phase detector for comparing the phase between the input clock signal and the output clock signal to generate a phase comparison signal, the phase comparison signal being input to the successive approximation register, the output digital bit of the successive approximation register being controlled A digital delay locked loop circuit using a lock-in pre-search search algorithm.
A control method of a digital delay locked loop circuit using a lock-in pre-search search algorithm according to any one of claims 1 to 9,
The operation of the lock-in pre-search mode is initiated and the phase error of the input clock signal and the output clock signal is removed to within the first reference resolution while monotonically increasing the delay of the coarse delay line, thereby searching for a near-lock point;
Determining whether a phase error between an input clock signal and an output clock signal is eliminated within a first reference delay resolution; And
If it is determined that the phase error between the input clock signal and the output clock signal is eliminated within the first reference delay resolution, the process proceeds to the binary search mode,
And returning to the locked-in pre-search mode when the phase error between the input clock signal and the output clock signal is not eliminated within the first reference delay resolution.
11. The method of claim 10,
In the control method,
Determining whether a phase error between an input clock signal and an output clock signal is removed within a second reference delay resolution after the successive approximation register performs a binary search; And
And if the phase error between the input clock signal and the output clock signal is not eliminated within the second reference delay resolution as a result of the determination, the successive approximation register is converted to a sequential counter to perform a sequential search Way.
11. The method of claim 10,
Wherein the coarse delay line comprises a plurality of delay elements and changes the number of active delay elements to monotonously increase the delay of the coarse delay line while searching for a near lock point.

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