KR101840686B1 - Device for changing the sensing time of sense amplifier for memory device - Google Patents

Abstract

The present invention relates to a sensing time-varying device of a sensing amplifier (10) which is configured by connecting two P-type metal-oxide-semiconductor (PMOS) transistors (PMOS1, PMOS2) and two N-type metal-oxide-semiconductor (NMOS) transistors (NMOS1, NMOS2) in a cross-coupled latch form. The sensing time-varying device includes a varying means which makes magnitudes of turn-on voltages of the two different NMOS transistors which are different from each other, and determines levels of input signals input to the sensing amplifier (10) from a selected memory cell among the multiple memory cells. Either one of the two NMOS transistors (NMOS1, NMOS2) is configured to have multiple NMOS transistors (NM11 to NM15) with different turn-on voltages. The varying means can select any one among the NMOS transistors (NM11 to NM15) with reference to output values of the output ports (OUT, OUTB) of the sensing amplifier (10) as well as using the selected NMOS transistor to configure the sensing amplifier (10).

Description

TECHNICAL FIELD [0001] The present invention relates to a device for sensing time of a sense amplifier for a memory device,

The present invention relates to a sensing time variable device for a sense amplifier for a memory device that changes the sensing time for determining whether data to be read to a sense amplifier at reading data from a memory device is 0 (low) or 1 (high).

A sense amplifier is used as a circuit for amplifying a very small voltage of about a few hundreds of bits output from a bit line to a level that can be handled at a digital level in a semiconductor memory device made up of a capacitor of minute size. For example, the technique described in Patent Document 1.

In the conventional sense amplifier including the Patent Document 1, the chip enable signal (CEN) is generally activated, and the clock signal (CLK) is then activated to select the memory cell to read data through the word line and the bit line The data stored in the selected memory cell is amplified and outputted through the sense amplifier.

During the data amplification process, the sense amplifier determines whether the level of data stored in the selected memory cell, that is, whether the data stored in the selected memory cell is 0 (low) or 1 (high) It is called the sensing time.

The determination of whether the data stored in the memory cell is 0 (low) or 1 (high) is normally performed on the basis of the input voltage (voltage) input to one of the input terminals of the sense amplifier, And the reference voltage Vref input to the other input terminal. The sensing time is a time required for the sense amplifier to discharge the input voltage VDD to the reference voltage Vref. In general, the reference voltage Vref is set to VDD / 2.

For example, when the data value stored in the selected memory cell is 0 (low), the input signal input to the sense amplifier from the selected memory cell starts discharging from the input voltage (VDD) The sense amplifier determines that the output of the selected memory cell is 0 (low) when the input signal becomes smaller than the reference voltage (Vref) value of VDD / 2, and outputs a 0 (low) signal to the output terminal. Therefore, if the reference voltage Vref is VDD / 2, the detection time is required for the total time indicated by the dotted line and the solid line in FIG.

Conversely, for example, when the value stored in the selected memory cell is 1 (high), a signal input to the sense amplifier from the selected memory cell likewise starts discharging from the input voltage (VDD) value but remains at the VDD value If it is still greater than the reference voltage Vref after a predetermined time (the same time as the detection time at the time of determination of 0 (low)), the sense amplifier judges this signal to be 1 (high) high signal.

However, it is required to increase the read time in accordance with the increase in the speed of the memory device.

If the reference voltage (Vref) is too low, the output of the memory cell is 0 (low) or 1 (Vref) due to the noise because the input signal input to the sense amplifier from the selected memory cell contains a lot of noise. high) may not be judged.

For this reason, depending on the environment in which the memory device is used, the sense time of the sense amplifier determining whether the data stored in the selected memory cell is 0 (low) or 1 (high) is made longer than VDD / However, the applicant of the present invention has not been able to confirm the prior art that can change the sensing time of the sense amplifier.

[Patent Document 1] JP-A-10-2006-0082942 (published on July 20, 2006)

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems of the prior art, and it is an object of the present invention to provide a sense amplifier which senses whether data stored in a selected memory cell is 0 (low) or 1 (high) It is another object of the present invention to provide a sensing time variable device for a sense amplifier for a memory device which can be shortened or adjusted in a short time.

According to an aspect of the present invention, there is provided a sensing time varying apparatus for a sense amplifier for a memory device, comprising: a sense amplifier having two PMOS transistors and two NMOS transistors connected in a cross- Variable means for varying a sensing time for determining the level of an input signal to be input to the sense amplifier from a selected one of the plurality of memory cells by making the turn-on voltages of the two NMOS transistors different from each other, Respectively.

According to the present invention, since a sense amplifier can be configured by selecting an NMOS transistor that can minimize the sense time of a sense amplifier among a plurality of NMOS transistors, the reference voltage of the sense amplifier can be set to VDD / 2 + DELTA V by DELTA V, there is an effect that the sensing time can be shortened as compared with the conventional case, which leads to an increase in the operation speed of the memory.

According to another aspect of the present invention, by making the reference voltage of the sense amplifier small by? V with VDD / 2 -? V smaller than the conventional VDD / 2, erroneous operation of the sense amplifier due to noise can be prevented.

BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a block diagram of a sense-time variable device of a sense amplifier according to a preferred embodiment of the present invention,
FIG. 2 is a detailed configuration diagram of the NMOS transistor NM1 of FIG. 1,
3 is a diagram showing the operation timing of the sensing time variable device of the prior art and sense amplifier of FIG.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a circuit diagram of a sensing time variable device of a sense amplifier according to a preferred embodiment of the present invention, and FIG. 2 is a detailed configuration diagram of the NMOS transistor NM1 of FIG.

As shown in Figs. 1 and 2, the sense amplifier 100 according to the present embodiment basically includes, in the same manner as a known sense amplifier, two so-called PMOS transistors PM1 and PM2 and two NMOS transistors NM1 and NM2 In the present embodiment, the NMOS transistor NM1 of the two NMOS transistors NM1 and NM2 at the input terminal of the cross-coupled latch type sense amplifier is connected to the input terminal of the sense amplifier of the cross-coupled latch type, NM15, and NM15 having different turn-on voltages of the NMOS transistors NM11, NM12, ..., and NM15, and the selection section 110 may include a plurality of NMOS transistors NM11, NM12, ..., And the sense amplifier 100 is operated by the selected transistor.

Therefore, in the present specification, the known configuration and operation of the sense amplifier will be described only in the range necessary for the description of the present invention, and the other parts are omitted.

In this embodiment, the sizes of the two NMOS transistors NM1 and NM2 of the cross-coupled latch constituting the sense amplifier 100 are made different from each other, and the turn-on voltage is made different. More specifically, (The turn-on voltage of the NMOS transistor NM1 <the turn-on voltage of the NMOS transistor NM2) smaller than the turn-on voltage of the NMOS transistor NM2 to set the positive feedback level of the sense amplifier 100 to VDD / 2 + DELTA V, that is, the positive feedback level of the sense amplifier 100 is made larger by DELTA V than VDD / 2.

The reason why the positive feedback level of the sense amplifier 100 becomes VDD / 2 + DELTA V when the relation of the turn-on voltage of the NMOS transistor NM1 and the turn-on voltage of the NMOS transistor NM2 is as follows: The gate-source voltage Vgs of the NMOS transistor NM2 gradually changes from the high level to the low level due to the time delay when the signal of the bus DB is changed from the low level to the high level The drain terminal of the NMOS transistor NM2 is changed from the low level to the high level so that the gate-source voltage Vgs of the NMOS transistor NM1 transits from the low level to the high level, The turn-on voltage of the transistor NM1 is smaller than the turn-on voltage of the NMOS transistor NM2 so that the threshold voltage at which the NMOS transistor NM1 is turned on is smaller than the NMOS transistor NM2, 100) to VDD / 2 The NMOS transistor NM1 is turned on and the NMOS transistor NM2 is turned off through the positive feedback even if the voltage is not lowered.

NMOS transistors NM11, NM12, ..., and NM15 are formed of five NMOS transistors in the present embodiment. The turn-on voltages of the NMOS transistors NM11, NM12, ..., NM15 are VDD / 2 The NMOS transistor NM12 is 6VDD / 10, the NMOS transistor NM13 is 7VDD / 10, the NMOS transistor NM14 is 8VDD / 10, and the NMOS transistor NM15 is 9VDD / The turn-on voltage starts from VDD / 2 and gradually decreases.

NM15 are shown in a rectangular shape in FIG. 2, the NMOS transistors NM11, NM12, ..., and NM15 have a rectangular shape, The source terminal is commonly connected to the drain and the source terminal of the NMOS transistor NM1 and the gate terminal is connected to the selection switch 110a under the control of the selector 110 to select one of the plurality of NMOS transistors NM11, The gates g1, g2, ..., and g5 of the sense amplifier NM15 are selected to configure the sense amplifier 100. [

One end of the selector 110 is connected to one of the output terminals OUT of the output terminals OUT and OUTB of the sense amplifier 100 and the other end of the selector 110 is connected to the selector switch 110a, NM15, ..., and NM15 to configure the sense amplifier 100 by controlling the NMOS transistors NM11, NM12, ..., NM15.

The memory 111 is constituted by, for example, a nonvolatile memory such as an EEPROM, and stores a value of VDD / 2 as a reference for judging the detection time.

The other NMOS transistor NM2 of the two NMOS transistors NM1 and NM2 at the input terminal of the sense amplifier 100 has the same configuration as the conventional one.

Next, the operation of the sense amplifier 100 according to the preferred embodiment of the present invention will be described with reference to FIG.

A method for selecting an appropriate NMOS transistor among the plurality of NMOS transistors NM11, NM12, ..., NM15 is as follows. First, the selection unit 110 controls the selection switch 110a so that the selection switch 110a is at VDD / The chip enable signal CEN is activated and the clock signal CLK is activated in the state where the sense amplifier is configured by using the NMOS transistor NM11 to select the data And stores the output value (one of 0 or 1) of the output terminals OUT and OUTB of the sense amplifier 100.

Next, the selection unit 110 controls the selection switch 110a so that the turn-on voltage of the NMOS transistors among the plurality of NMOS transistors NM11, NM12, ..., NM15 is one NMOS transistor that is one step smaller than the NMOS transistor NM11 The NMOS transistor NM12 is selected to constitute a sense amplifier and the chip enable signal CEN and the clock signal CLK are activated to select a memory cell from which data is to be read and the output terminals OUT, The output value of the sense amplifier 100 when the sense amplifier is constituted by the NMOS transistor NM11 having the reference voltage Vref of VDD / 2 is compared with the output value of the sense amplifier 100, Check whether the output value is fluctuated.

If the output value of the sense amplifier 100 does not fluctuate, the selection unit 110 controls the selection switch 110a so that the turn-on voltage of the NMOS transistor among the plurality of NMOS transistors NM11, NM12, ..., NM15 The operation of selecting the NMOS transistor NM13 as the NMOS transistor NM13 which is one step smaller than the NMOS transistor NM12 to constitute the sense amplifier and repeating the same operation to check whether the output value of the sense amplifier 100 fluctuates is called the NMOS transistor (NM15).

If the output value of the sense amplifier 100 fluctuates as a result of the check, the NMOS transistor at the stage before the fluctuation of the output value of the sense amplifier 100 occurs is selected and the selection operation is terminated.

Through this process, the sense amplifier 100 can be configured by selecting an NMOS transistor that can minimize the sense time of the sense amplifier among the plurality of NMOS transistors NM11, NM12, ..., NM15, 3, the reference voltage of the sense amplifier for determining whether the data output from the selected memory cell is 0 or 1 is set to VDD / 2, which is a value larger than the conventional VDD / 2, 2 + DELTA V, it is possible to discharge only VDD / 2 + DELTA V without discharging to VDD / 2 as in the prior art for determination of the data level. Therefore, Therefore, there is an effect that the detection time can be shortened by the dotted line compared with the conventional case.

<Modifications>

In the above embodiment, the NMOS transistor NM1 of the two NMOS transistors NM1 and NM2 constituting the sense amplifier 100 is turned on (the turn-on voltage of the NMOS transistor NM1 <the turn-on voltage of the NMOS transistor NM2) The reference voltage Vref is increased to VDD / 2 + DELTA V by configuring the sense amplifier 100 with the NMOS transistors selected among the plurality of NMOS transistors NM11, NM12, And the detection time was shortened.

In this modification, the sizes of the two NMOS transistors NM1 and NM2 of the cross-coupled latch constituting the sense amplifier 100 are made different from each other, and the turn-on voltage of the NMOS transistor NM1 is set to the NMOS (The turn-on voltage of the NMOS transistor NM1> the turn-on voltage of the NMOS transistor NM2) larger than the turn-on voltage of the transistor NM2 to set the positive feedback level of the sense amplifier 100 to VDD / 2- , That is, the positive feedback level of the sense amplifier 100 is made smaller by? V than VDD / 2.

4, each of the NMOS transistors NM21, NM22, ..., and NM25 is composed of five NMOS transistors. The turn-on voltage of each NMOS transistor NM21 is VDD / 2 (= 5VDD / 10), NMOS transistor NM22 is 4VDD / 10, NMOS transistor NM23 is 3VDD / 10, NMOS transistor NM24 is 2VDD / 10, and NMOS transistor NM25 is 1VDD / The turn-on voltage starts at VDD / 2 and gradually increases.

In this modification, the method of selecting the NMOS transistor among the plurality of NMOS transistors NM21, NM22, ..., and NM25 to configure the sense amplifier 100 is the same as that of the above-described embodiment, and thus a detailed description thereof will be omitted.

According to the present modification, since the reference voltage Vref is VDD / 2 - DELTA V, the sensing time is relatively longer than that of the prior art. However, when the input voltage VDD input from the selected memory cell to the sense amplifier is large It is possible to prevent the sense amplifier from malfunctioning due to noise by lowering the level of the reference voltage Vref even when noise is mixed.

While the present invention has been described with reference to the preferred embodiments and modifications, it is to be understood that the present invention is not limited to the exemplary embodiments and modifications, and various changes and modifications can be made without departing from the scope of the claims.

The NMOS transistor NM1 of the two NMOS transistors NM1 and NM2 constituting the sense amplifier may be a NMOS transistor selected from among a plurality of NMOS transistors whose turn-on voltages are different from each other, However, the NMOS transistor NM2 may be a NMOS transistor selected from among a plurality of NMOS transistors having different turn-on voltages to constitute a sense amplifier.

In the embodiment and the modification, the drain and source terminals of the plurality of NMOS transistors NM11, NM12, ..., NM15 or the plurality of NMOS transistors NM21, NM22, ..., NM25 are common, The gate terminal of the NMOS transistor 110a is selectively connected to any one of the plurality of NMOS transistors. However, the present invention is not limited thereto, and two of the three stages of the NMOS transistor may be common, and the other one may be selected.

100 sense amplifier (100)
110 selector 110,
110a selection switch 110a,
PM1, PM2 PMOS transistors
NM1, NM2 NMOS transistors
Vref reference voltage
DB data bus
OUT, OUTB Output stage

Claims (4)

A sensing time variable device for a sense amplifier for a memory device, wherein two PMOS transistors and two NMOS transistors are connected in the form of a cross coupled latch,
And variable means for varying a sensing time for determining the level of an input signal to be input to the sense amplifier from a selected one of the plurality of memory cells by making the magnitudes of the turn-on voltages of the two NMOS transistors different from each other,
Wherein one of the two NMOS transistors is composed of a plurality of NMOS transistors having different turn-on voltages,
The variable means may comprise a plurality of NMOS transistors each having a different turn-on voltage from the NMOS transistor having the largest turn-on voltage to the NMOS transistor having a smaller turn-on voltage, The sense amplifier is constructed by using the NMOS transistor having the turn-on voltage before the variation of the output value, as a result of checking whether the output value of the output terminal of each of the composed sense amplifiers fluctuates, Wherein the sensing time is varied to reduce the sensing time. delete delete A sensing time variable device for a sense amplifier for a memory device, wherein two PMOS transistors and two NMOS transistors are connected in the form of a cross coupled latch,
And variable means for varying a sensing time for determining the level of an input signal to be input to the sense amplifier from a selected one of the plurality of memory cells by making the magnitudes of the turn-on voltages of the two NMOS transistors different from each other,
Wherein one of the two NMOS transistors is composed of a plurality of NMOS transistors having different turn-on voltages,
Wherein the variable means comprises a plurality of NMOS transistors each having a different turn-on voltage from the NMOS transistor having the smallest turn-on voltage to the NMOS transistor having the smallest turn-on voltage, The sense amplifier is constructed by using the NMOS transistor having the turn-on voltage before the variation of the output value, as a result of checking whether the output value of the output terminal of each of the composed sense amplifiers fluctuates, Wherein the sensing time is varied to increase the sensing time.

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