KR101834975B1 - Split monotonic successive approximation register analog to digital converter - Google Patents

Abstract

The present invention relates to a split monotonic successive approximation register analog-to-digital converter. According to the present invention, the split monotonic successive approximation register analog-to-digital converter comprises: a sample hold unit to correspond to a switching control by a successive approximation register (SAR) control logic, to receive input from a first input signal (V_ip) and a second input signal (V_in), which are input signals, and to perform a sample motion and hold motion; a capacitor array in a two-step structure to generate a first output signal and second output signal, which are output voltage values corresponding to each of the first input signal and second input signal during a sample hold time and to determine an upper bit or a lower bit of a capacitor bridge (CB); a switch (S7) linked with the sample hold unit to determine an upper bit or a lower bit; a comparison unit to compare a size of the first output signal and a size of the second output signal and to output a digital value in accordance with the result of the comparison; and an SAR control logic to correspond to the digital value and to output a final digital code value as a result signal. According to the present invention, the present invention is able to reduce the number of capacitors by combining the split type and monotonic type to improve energy efficiency and to realize the desired size of capacitor, thereby improving accuracy.

Description

[0001] The present invention relates to a split monotonic successive approximation register (ADC) analog to digital converter

The present invention relates to analog-to-digital converters, and more particularly, to a discrete, fork-in-successive approximate analog-to-digital converter that combines separate techniques to reduce the number of capacitors in an energy efficient conventional forged successive approximation analog-to-digital converter.

A conventional monotonic successive approximation register analog to digital converter (MSAR ADC) requires a number of capacitors of 2 ^N-1 per bit (N). Therefore, it requires 512 capacitors for 10 bits, and the design area increases greatly as 1 bit increases. However, it has the advantage of being more energy efficient than conventional successive approximation analog-to-digital converters.

Meanwhile, a conventional split-successive analog-to-digital converter (Split SAR ADC) is capable of high-resolution analog-to-digital conversion with a small number of capacitors through a bridge capacitance. However, since it is difficult to precisely control the size (capacitance size) of the bridge capacitor, there is a problem that the error in the lower bit area becomes larger. For example, in a 10-bit, discrete successive approximation analog-to-digital converter, setting the basic capacitor size to 100 fF results in a bridge capacitor ... fF, which is impossible to accurately implement in the present process. Therefore, the accuracy of the low-order bits is determined according to the process error range of the bridge capacitor, and a correction circuit must be added to improve the accuracy at the low-order bits.

Korean Patent Laid-Open Publication No. 2013-0045803 (Publication date 2013.05.06.), "Multi-bit successive approximation analog-to-digital conversion"

SUMMARY OF THE INVENTION It is therefore an object of the present invention to solve the problem of a separate type technique and to reduce the number of capacitors by combining separate types of techniques in which the size of an added bridge capacitor is implemented in a natural number Analog-to-digital converters, which are capable of providing a continuous approximate analog to digital converter.

According to an aspect of the present invention, there is provided a discrete forged successive approximation analog-to-digital converter including a first approximation register (SAR) control logic for controlling a first input signal, V _ip , A sample hold unit that receives a signal V _in and performs a sample operation and a hold operation; And generates a first output signal and a second output signal, which are output voltage values corresponding to the first input signal and the second input signal, respectively, during a sample hold time, and determine the upper or lower bit of the bridge capacitor (C _B ) A capacitor array in which a capacitor array is formed in a two-stage structure; A switch (S7) interlocked with the sample hold section to determine the upper bit or the lower bit; A comparator for comparing the magnitudes of the first output signal and the second output signal and outputting a digital value according to a comparison result; And successive approximation register control logic for outputting the final digital code value as a result signal corresponding to the digital value.

At this time, the capacitor array includes an upper capacitor array and a lower capacitor array determined by the bridge capacitor C _B and the switch S7. Each of the upper capacitor array and the lower capacitor array includes a first capacitor portion for determining an upper bit and a second capacitor portion for determining a lower bit. Each of the first capacitor portion and the second capacitor portion includes a plurality of capacitors connected in parallel, and the plurality of capacitors have one end connected to a reference voltage or a bottom switch grounded, and the other end connected to a comparator. Wherein the ratio of the first capacitor unit to the second capacitor unit is N: N, N: N-1, N: N-2, , And N: 1. Each of the bridge capacitor C _B , the first capacitor unit and the second capacitor unit has a drain relation.

The switch S7 is connected at one end to the bridge capacitor C _B and is connected to the reference or ground at the upper bit and is opened at the lower bit.

As described above, according to the separating-type forged successive approximation analog-to-digital converter according to the present invention, the size of the added bridge capacitor is implemented as a natural number to solve the problem of the separating technique, and at the same time, the overall number of capacitors It is possible to improve the energy efficiency and reduce the design area.

In addition, the size of the capacitor can be accurately implemented in the current process, and the accuracy can be improved without the need for an additional correction circuit.

That is, the present invention can be expected to reduce the number of capacitors, improve energy efficiency, realize a capacitor size, and improve accuracy by combining a separation type and a forging.

1 is a circuit diagram of a conventional forged successive approximation analog-to-digital converter.
2 is a waveform diagram illustrating the operation of a conventional monotonic successive approximation analog-to-digital converter.
3 is a circuit diagram of a conventional detachable successive approximation analog-to-digital converter.
4 is a circuit diagram of a discrete forged successive approximation analog-to-digital converter according to an embodiment of the present invention.
5 is a circuit diagram of a higher bit of the present invention.
6 is a waveform diagram of an upper bit operation of the present invention.
7 is a low bit operation state diagram of the present invention.
FIG. 8 is a conceptual diagram illustrating a process of changing a top plate voltage according to a voltage change of a lower plate of the bridge capacitor of the present invention.
FIG. 9 is a conceptual diagram illustrating the process of changing the voltage of the lower plate of the bridge capacitor of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT Hereinafter, the present invention will be described in detail with reference to preferred embodiments of the present invention and the accompanying drawings, wherein like reference numerals refer to like elements.

As described above, in the conventional forged successive approximation analog-to-digital converter, the number of capacitors increases with a bit increase, and the design area increases. On the other hand, in the separate-type successive approximation analog-to-digital converter, the size of the bridge capacitor can not be accurately implemented by the current process technology, and there is a problem that an error occurs in the lower bits according to the process error of the bridge capacitor.

Accordingly, in the present invention, the bridge capacitor and the monotonic technique are combined to make the value of the bridge capacitor a natural number, thereby improving the energy efficiency and reducing the number of capacitors. That is, the present invention combines a separate type technique for reducing the number of capacitors for a conventional energy-efficient forged successive approximation analog-to-digital converter. By implementing the added size of the bridge capacitor in a natural number, it solves the problem of the separating technique and at the same time reduces the total number of capacitors of the forged consecutive analog-to-digital converter. As a result, the energy efficiency can be improved and the design area can be reduced. In addition, the capacitor size can be accurately implemented in the current process, and the accuracy can be improved without the need for an additional correction circuit.

First, after explaining the existing technique, the separated single forged successive approximation analog-to-digital converter of the present invention will be described.

1 is a circuit diagram of a conventional forged successive approximation analog-to-digital converter.

Referring to FIG. 1, a conventional forged successive approximation analog-to-digital converter is illustrated with 10 bits.

Conventional forged successive approximation analog digital converters consist of a comparator, a capacitor, and a sampling hold switch (SH). The bottom switches (D _p0 to D _p8 , D _n0 to D _n8 ) formed at one end of the capacitor are connected to V _REF or GND (ground). The capacitors have 256 (2 ^N-2 ) capacitors at the non-inverting terminal (+) and inverting terminal (-) of the comparator, respectively, and a total of 512 (2 ^N-1 ) capacitors of 10 bits are required. If you increase 1 bit here, that is, make 11 bits, a total of 1024 capacitors will be needed.

2 is a waveform diagram illustrating the operation of a conventional monotonic successive approximation analog-to-digital converter.

Referring to FIG. 2, bottom switches (D _p0 to D _p8 , D _n0 to D _n8 ) formed at one end of the capacitor during the sampling hold (SH) time are all connected to V _REF and inverted The terminals (-) are charged with V _{IN_P} and V _{IN_N} , respectively. After the noninverting terminal (+) and inverting terminal (-) of the comparator are charged, the comparator compares the two values and stores the result ('1') in D9. Since the voltage of the non-inverting terminal (+) of the comparator is larger than the voltage of the inverting terminal (-), the D _p8 switch is connected to GND and the voltage of the non-inverting terminal (+) of the comparator is V _REF / 2 . And the comparator compares the two values. As a result, D8 stores '1' because the voltage of the non-inverting terminal (+) of the comparator is larger than the voltage of the inverting terminal (-). The D _p7 switch is then connected to GND and the voltage at the non-inverting terminal (+) of the comparator is reduced by V _REF / 2 ² and the comparator compares the two values. Next, since the voltage of the non-inverting terminal (+) of the comparator is greater than the voltage of the inverting terminal (-), a value of '0' is stored in D ₇ , the D _n6 switch is connected to GND, -) is reduced by V _REF / 2 ³ . Calculate up to D0 in the same way. In this way, the voltage of the non-inverting terminal (+) or inverting terminal (-) of the comparator moves in one direction decreasing. This analog-to-digital converter is called a forged successive approximation analog-to-digital converter.

3 is a circuit diagram of a conventional detachable successive approximation analog-to-digital converter.

Referring to FIG. 3, a conventional discrete successive approximation analog-to-digital converter is illustrated with 10 bits.

In the conventional separable successive approximation analog-to-digital converter, 5 bits of the MSB and 5 bits of the LSB are separated into a bridge capacitance, and 5 bits (LSB) (D0-D4) and 5 bits (D5-D9) of the upper bits (MSB). At this time, the most important thing is the size (capacity size) of the bridge capacitor that separates the two regions. As shown in FIG. 1, the size of the total capacitors in the lower bit region viewed from the upper bit region should be 1C. When the size of the bridge capacitor is C _B ,

가 된다. 따라서 공정으로 정확히 구현하기가 불가능하며, 브릿지 커패시터의 공정오차에 따라 하위비트에서의 오차가 발생하게 된다.And,

. Therefore, it is impossible to accurately implement the process, and an error occurs in the lower bit according to the process error of the bridge capacitor.

4 is a circuit diagram of a discrete forged successive approximation analog-to-digital converter according to an embodiment of the present invention.

Referring to FIG. 4, the separated forged successive approximation analog-to-digital converter of the present invention includes a first input signal V _ip and a second input signal V _ip corresponding to the switching control by consecutive approximate register (SAR) control logic, (SH) for receiving a first input signal (V _in ) and a second input signal (V _in ) and performing a sample operation and a hold operation, A capacitor array CA having a two-stage capacitor array for generating a first output signal and a second output signal having voltage values and determining an upper bit or a lower bit using the bridge capacitor C _B ; A switch (S7) for interlocking with the sample hold part (SH) to determine the upper bit or the lower bit, a comparator (S7) for comparing the magnitudes of the first output signal and the second output signal, (Comp), Dig And SAR control logic for outputting the final digital code value as a result signal in response to the hair value.

At this time, the capacitor array CA includes a capacitor array CAp and a lower capacitor array CAn, which are determined by the bridge capacitor C _B and the switch S7.

Further, each of the capacitor array CAp and the lower capacitor array CAn includes a first capacitor portion for determining an upper bit and a second capacitor portion for determining a lower bit. In this case, each of the first capacitor portion and the second capacitor portion includes a plurality of capacitors connected in parallel, and the plurality of capacitors have one end connected to a reference voltage or a ground switch to be grounded, and the other end connected to a comparator (Comp).

As an example, the first capacitor portion (upper bit) may be composed of six capacitors, and the second capacitor portion (lower bit) may be composed of four capacitors. At this time, the bridge capacitor C _B is 2 ³ C. That is, the capacitance value of the bridge capacitor C _B is a natural number. On the other hand, the ratio of the first capacitor unit to the second capacitor unit is N: N, N: N-1, N: N-2, , And N: 1 can be selected. At this time, each of the bridge capacitor C _B , the first capacitor portion and the second capacitor portion maintains a drain relation. Accordingly, the capacitance of the bridge capacitor C _B can be any one of natural numbers.

On the other hand, the switch S7 is connected at one end to the bridge capacitor C _B , connected to the reference or ground at the upper bit, and opened at the lower bit.

In the separated forging successive approximation analog-to-digital converter of the present invention configured as described above, the upper bit determining part and the lower bit determining part are divided through the bridge capacitor C _B and the S7 switch. When the S7 switch is closed, it becomes a successive approximate analog-to-digital converter that determines the upper bit, and when the S7 switch is opened, it becomes a successive approximate analog-to-digital converter that determines the lower bit.

Hereinafter, the operation of the separable forging successive approximation analog-to-digital converter configured as described above will be described.

5 is a circuit diagram of a higher bit of the present invention.

Referring to FIG. 5, when the S7 switch of FIG. 4 is connected to V _REF or GND (closed), it is a circuit diagram of upper bits. The result is shown in Fig. 5, which is a circuit diagram for determining the upper bits of the separable forged successive approximation analog-to-digital converter.

6 is a waveform diagram of an upper bit operation of the present invention.

Referring to FIG. 6, when the SH switch is initially closed, <S _4p : S _9p > = <000000> and <S _4n : S _9n > = <000000> are all connected to V _REF . Then, the input voltages V _{IN_n} and V _{IN_p} are sampled on the capacitor top plate C_top. When the input voltage is sampled on the capacitor, only the SH switch is opened. Thereafter, the voltage of the non-inverting terminal (+) of the comparator (Comp) is compared with the voltage of the inverting terminal (-). Since the voltage of the non-inverting terminal (+) of the comparator (Comp) is larger than the voltage of the inverting terminal (-), <D _9p > = <1> The voltage decreases by V _REF / 2. <D _9n> = doeseo as connected to the V _REF <0>, inverting terminal of the comparator (Comp) (-) voltage is maintained. Then, since the voltage of the non-inverting terminal (+) of the comparator (Comp) is larger than the voltage of the inverting terminal (-), <D _8p > = <1> is connected to GND, (+) Voltage decreases by V _REF / 2 ² . <D _8n> = doeseo as connected to the V _REF <0>, inverting terminal of the comparator (Comp) (-) voltage is maintained. Next, since the voltage of the inverting terminal (-) of the comparator (Comp) is larger than the voltage of the non-inverting terminal (+), <D _7n > = <1> is connected to GND, -) decreases by V _REF / 2 ³ . _<7p D> = doeseo as connected to the V _REF <0>, the voltage of the comparator (Comp) a non-inverting terminal (+) of is maintained. In this way, the remaining bits are also determined. As a result, <D _4p : D _p9 > = <110010> and <D _4n : D _n9 > = <001101>. When the upper 6 bits are determined, both S _7n and S _7p are connected to OPEN.

7 is a low bit operation state diagram of the present invention.

Referring to Fig. 7, when both the S7 switch and the SH switch are opened in Fig. 4, a circuit diagram of lower bits is obtained. The switches S ₉ , S ₈ , S ₆ , S ₅ , and S ₄ of the upper bits are connected to GND as a result of FIG. It is a circuit diagram for determining the lower bits thereof.

FIG. 8 is a conceptual diagram illustrating a process of changing a top plate voltage according to a voltage change of a lower plate of the bridge capacitor of the present invention.

Referring to FIG. 8, the change of the top plate voltage (C _MSB ) according to the change of the bridge plate lower plate voltage (C _LSB ) of the present invention is described. The sum of the capacitors in C _MSB is 56C and the value of C _B is 8C. Thus, by the law of charge distribution

가 된다.do. Also, if we calculate the sum of the capacitors looking at C _LSB

.

FIG. 9 is a conceptual diagram illustrating the process of changing the voltage of the lower plate of the bridge capacitor of the present invention.

만큼 변하게 된다. 그 후 브릿지 커패시터(C_B)에 의해서 전압이

만큼 감소하게 된다. 그 결과 C_MSB의 전압이

가 만들어지면서 하위비트 D₃가 결정된다. 그 후 D₂, D₁은 커패시터 값이 1/2 만큼 감소하기 때문에, 각각

,

이 만들어 진다. 따라서 하위비트 3비트가 결정된다.Referring to FIG. 9, as a description of the lower bit operation of the present invention, when explaining the upper bits in FIG. 6, upper bits 7 bits are determined up to V _REF / 2 ⁶ . Therefore, if the determination is made from V _REF / 2 ⁷ to V _REF / 2 ⁹ in the lower bit, the lower 3 bits are determined. When the value of the lower bit D ₃ is changed from '1' to '0', the voltage changes by ΔV _REF , and the voltage of C _LSB becomes

. Thereafter, a voltage is applied by the bridge capacitor C _B

. As a result, the voltage of C _MSB

And the lower bit D ₃ is determined. Since D ₂ and D ₁ then decrease the capacitor value by 1/2,

,

. Therefore, the lower 3 bits are determined.

The description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features presented herein.

SH: Sample hold section (SH switch)
CA: capacitor array
Comp: Comparator

Claims (7)

A sample hold unit for receiving a first input signal V _ip and a second input signal V _{in as} input signals in response to a switching control by a consecutive approximation register (SAR) control logic and performing a sample operation and a hold operation;
And generates a first output signal and a second output signal which are output voltage values corresponding to the first input signal and the second input signal during the sample hold time, and outputs the upper bit or the lower bit by the bridge capacitor C _B A capacitor array in which a capacitor array for determination is formed in a two-stage structure;
A switch (S7) interlocked with the sample hold unit to determine the upper bit or the lower bit, and to make the capacitance value of the bridge capacitor be an integral multiple;
A comparator for comparing the magnitudes of the first output signal and the second output signal and outputting a digital value according to a comparison result; And
And successive approximation register control logic for outputting the final digital code value as a result signal in response to the digital value,
Characterized in that the capacitor array comprises an upper capacitor array and a lower capacitor array determined by the bridge capacitor (C _B ) and the switch (S7).
delete The method according to claim 1,
Wherein each of the upper capacitor array and the lower capacitor array includes a first capacitor portion for determining an upper bit and a second capacitor portion for determining a lower bit.
The method of claim 3,
Wherein each of the first capacitor portion and the second capacitor portion includes a plurality of capacitors connected in parallel and the plurality of capacitors are connected to a reference switch or ground switch to which one end is connected and the other end is connected to a comparator, converter.
5. The method of claim 4,
Wherein the ratio of the first capacitor unit to the second capacitor unit is N: N, N: N-1, N: N-2, , And N: 1, respectively.
The method of claim 3,
Wherein the bridge capacitor (C _B ), the first capacitor portion and the second capacitor portion each have a drain relationship.
The method according to claim 1,
The switch S7 is connected at one end to the bridge capacitor C _B , connected to the reference or ground at the upper bit, and opened at the lower bit.

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