KR101824067B1 - Method of interfacing between host and semiconductor storage device for throttling performance of the semiconductor storage device, and apparatus there-of - Google Patents

Abstract

A method and apparatus for interfacing between a semiconductor storage device and a host for controlling performance of a semiconductor storage device are disclosed. The interface method includes receiving a setup request command from the host; The semiconductor storage device in response to the configuration request command setting a requested performance control parameter to a specific value; And transmitting a setting response signal indicating that the semiconductor storage device has completed setting the performance adjustment parameter to the host.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor storage device and a host interface method for controlling performance of a semiconductor storage device,

The present invention relates to an interface between a data storage device and a host, and more particularly, to an interface method and apparatus for controlling the performance of the semiconductor storage device between a semiconductor storage device and a host that store data in a nonvolatile memory.

Semiconductor storage devices are devices that store data using semiconductors (particularly, nonvolatile memory), and are faster in speed and stronger in physical shock than disk storage media (hard disk drives), which have hitherto been widely used as mass storage devices It has less heat and noise, and can be miniaturized. An example of a semiconductor storage device is a solid state drive (SSD).

On the other hand, semiconductor storage devices may have a limited service life. For example, NAND flash memory is a typical example. In a NAND flash memory, a memory element is divided into block units, and a plurality of pages exist in one block. The user first uses the NAND flash memory by erasing the block and sequentially programming the pages in the block with specific data. To program all pages as new data with programmed blocks, the corresponding block must be erased again. This sequence of processes is called the program-erase cycle (PE-cycle), and in the case of NAND flash memory, the number of PE cycles that a block can withstand is limited. This is called the endurance of the NAND flash memory.

If the number of PE-cycles experienced by one block exceeds the endurance limit, then the block has a higher probability of malfunctioning in the future. Causes of malfunction of the memory include read operation, natural charge loss, and the like in addition to the program and erase operations described above. As the probability of malfunction increases, it should no longer be used for data integrity of semiconductor storage devices. For this reason, semiconductor storage devices employing NAND flash memory have a limitation in their lifetime.

In the above example, when an excessive workload is applied to the semiconductor storage device, for example, a write operation, an erase operation, a read operation, or the like, the life of the semiconductor storage device may be shortened or the expected life may not be guaranteed. Therefore, in order to ensure the expected lifetime of the semiconductor storage device, the processing capacity of the semiconductor storage device needs to be adjusted depending on the strength or amount of the workload applied to the semiconductor storage device.

This case can be found in a solid state drive (SSD) composed of a multi-level cell (MLC) NAND flash memory for a server application. Server-oriented storage devices require high performance, that is, high I / O per second (I / O), as well as a large change in the amount of workload applied to the storage device. Application of MLC NAND flash memory with limited endurance limitations to such applications has difficulties in guaranteeing the lifetime of the SSD.

However, the storage device to which the life is to be guaranteed is not limited to the above-described server-oriented storage device, and the lifetime of a storage device to be applied to a PC (personal computer), a notebook computer,

In addition to the NAND flash memory described above, examples of the memory having the limit of the degree of freedom include PRAM (Phase Change Memory), MRAM (Magnetic Random Access Memory), ReRAM (Resistive RAM), FeRAM (Ferroelectric RAM, Ferroelectric RAM ) And the like. In addition, NAND flash memory with the limit of the limit includes a NAND flash memory using a floating gate and a NAND flash memory based on a charge trap flash (CTF) method.

Thus, it is necessary to adjust the performance of the semiconductor storage device in order to extend the lifetime of the semiconductor storage device using the nonvolatile memory having the endurance limit, or to ensure the expected lifetime.

SUMMARY OF THE INVENTION Accordingly, the present invention has been made in view of the above problems, and it is an object of the present invention to provide a method and apparatus for interfacing between a host and a semiconductor storage device for controlling the performance of a semiconductor storage device.

According to an aspect of the present invention, there is provided a method of interfacing a semiconductor storage device with a host for controlling performance of the semiconductor storage device. The method includes receiving a configuration request command from the host; The semiconductor storage device in response to the configuration request command setting a requested performance control parameter to a specific value; And transmitting a setting response signal indicating that the semiconductor storage device has completed setting the performance adjustment parameter to the host.

According to another aspect of the present invention, there is provided a method of interfacing a semiconductor storage device with a host for controlling performance of the semiconductor storage device. The method comprising: sending a configuration request command to the semiconductor storage device to set a performance control parameter required for performance control of the semiconductor storage device by the host to a specific value; And receiving a setting response signal from the semiconductor storage device in response to the setting request command indicating that the performance adjustment parameter is set to the specific value.

According to another aspect of the present invention, there is provided a method of interfacing a semiconductor storage device with a host for controlling performance of the semiconductor storage device. The method includes receiving an information request command from the host; And transmitting, by the semiconductor storage device, an information response signal including the requested performance control parameter to the host in response to the information request command.

According to another aspect of the present invention, there is provided a method of interfacing a semiconductor storage device with a host for controlling performance of the semiconductor storage device. Transmitting, by the host, an information request command to the semiconductor storage device requesting transmission of a performance adjustment parameter of the semiconductor storage device; And receiving an information response signal including the value of the performance adjustment parameter transmitted in response to the information request command from the semiconductor storage device.

According to another aspect of the present invention, there is provided a nonvolatile memory including: a nonvolatile memory; And a controller for controlling the nonvolatile memory in response to a request from a host, the controller receiving a configuration request command from the host, setting a requested performance control parameter in response to the configuration request command to a specific value, There is provided an apparatus for transmitting a setting response signal indicating that the semiconductor storage device has completed setting of the performance adjustment parameter to the host.

According to another aspect of the present invention, And sending a configuration request command to the semiconductor storage device to set a performance control parameter of the semiconductor storage device to a specific value under the control of the CPU, And an interface unit for receiving a setting response signal indicating that the specific value is set.

The device may be a host or a RAID controller card.

As described above, according to the present invention, various parameters required for performance control of the semiconductor storage device can be easily set by a host request or command, and performance control related information can be reported from the semiconductor storage device to the host have.

1 is a schematic block diagram of a data storage system in accordance with an embodiment of the present invention.
2 is a schematic block diagram of a controller according to an embodiment of the present invention.
FIG. 3 is a view schematically showing the structure of the nonvolatile memory device shown in FIG. 2. FIG.
4 is a schematic block diagram of a host according to an embodiment of the present invention.
5 is a flowchart illustrating a method of adjusting the performance of a semiconductor storage device according to an embodiment of the present invention.
FIG. 6 is a flowchart schematically illustrating a host-semiconductor storage device interface method for controlling performance of a semiconductor storage device according to an embodiment of the present invention.
FIG. 7 is a flowchart schematically illustrating a host-semiconductor storage device interface method for controlling performance of a semiconductor storage device according to another embodiment of the present invention.
FIG. 8 shows performance control parameters stored in a semiconductor storage device for a method of adjusting the performance of a semiconductor storage device according to an embodiment of the present invention.
FIG. 9 is a workload parameter used in a method of predicting a workload of a semiconductor storage device according to an embodiment of the present invention.
10 is a table showing a format of a setup request command according to an embodiment of the present invention.
11A and 11B are tables showing the format of a performance adjustment enable command and an information request command according to an embodiment of the present invention, respectively.
12 is a table showing the format of an information response command according to an embodiment of the present invention.
13 is a flowchart illustrating a method of interfacing a host and a semiconductor storage device according to an embodiment of the present invention.
14 is a block diagram of an electronic system including a semiconductor storage device according to an embodiment of the present invention.
15A and 15B are block diagrams of an electronic system according to another embodiment of the present invention, respectively.
16 is a block diagram of a computing system having a semiconductor storage device according to an embodiment of the present invention.

Specific structural and functional descriptions of embodiments according to the concepts of the present invention disclosed in this specification or application are merely illustrative for the purpose of illustrating embodiments in accordance with the concepts of the present invention, The examples may be embodied in various forms and should not be construed as limited to the embodiments set forth herein or in the application.

It is to be understood that when an element is referred to as being "connected" or "connected" to another element, it may be directly connected or connected to the other element, . On the other hand, when an element is referred to as being "directly connected" or "directly connected" to another element, it should be understood that there are no other elements in between.

 For example, when one component 'transmits or outputs' data or signals to another component, the component may 'transmit or output' the data or signal directly to the other component, and at least one Quot; means that the data or signal can be " transmitted or outputted " to another element through another element of the system.

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, the present invention will be described in detail with reference to the preferred embodiments of the present invention with reference to the accompanying drawings. Like reference symbols in the drawings denote like elements.

An embodiment of the present invention relates to a method for identifying and predicting a workload (i. E., The intensity and pattern of a workload) that a storage device will first experience before adjusting the performance of a semiconductor storage device. Knowing the strength and pattern of the workload can lead to optimal performance of the storage device in relation to the lifetime that the storage device must ensure and the endurance limit of the storage device.

1 is a schematic block diagram of a data storage system 1 according to an embodiment of the present invention. A data storage system 1 according to an embodiment of the present invention includes a semiconductor storage device 10 and a host 20. [ The semiconductor storage device 10 may include a controller 100 and a non-volatile memory device 200.

The host 20 is connected to a semiconductor device 20 using interface protocols such as peripheral component interconnect-express (PCI-E), advanced technology attachment (ATA), serial ATA (SATA), parallel ATA (PATA) And can communicate with the storage device 10. However, the interface protocols between the host 20 and the semiconductor storage device 10 are not limited to the above-described examples, and may be a USB (Universal Serial Bus), a multi-media card (MMC), an enhanced small disk interface (ESDI) (Integrated Drive Electronics), and the like.

The semiconductor storage device 10 according to the embodiment of the present invention may be a solid state drive (SSD) or a secure digital (SD) card, but is not limited thereto. In addition, non-volatile memory device 200 may be a flash memory device, but is not limited thereto, and may be a PRAM, MRAM, ReRAM, or FeRAM device. When the nonvolatile memory device 200 is a flash memory device, it may be a floating gate type NAND flash memory device or a CTF (Charge Trap Flash) type NAND flash memory device. The memory cell transistors of the nonvolatile memory device 200 may have a two-dimensionally arranged structure or a three-dimensionally arranged structure.

The controller 100 controls the overall operation of the semiconductor storage device 10 and also controls all data exchange between the host 20 and the nonvolatile memory device 200. For example, the controller 100 controls the nonvolatile memory device 200 at the request of the host 20 to write data or read data. In addition, the controller 100 controls a series of internal operations (e.g., performance adjustment, merge, wear leveling, etc.) necessary for the characteristics of the non-volatile memory and for efficient management of the non-volatile memory.

The nonvolatile memory device 200 is a storage area for storing data in a nonvolatile manner, and can store an operating system (OS), various programs, and various data.

2 is a schematic block diagram of a controller 100 according to one embodiment of the present invention. 2, the controller 100 includes a host interface 110, a DRAM 120, an SRAM 130, a memory interface 140, a CPU 150, a bus 160, a workload module 170, A timer 180, a performance adjustment module 190, and a clock generator 195.

The host interface 110 has an interface protocol as described above for communicating with the host 20. DRAM 120, and SRAM 130 volatile store data and / or programs, respectively. Non-volatile memory interface 140 interfaces with non-volatile memory device 200.

The CPU 150 performs all control operations for writing / reading data to and from the nonvolatile memory device 200. [

The workload module 170 may collect workload data associated with the workload being applied to the semiconductor storage device 10 and may predict the workload based on the collected workload data.

The performance adjustment module 190 determines the target performance level according to the workload predicted by the workload module 170 and adjusts the performance of the semiconductor storage device 10 by applying the determined performance level.

 The timer 180 provides time information to the CPU 150, the workload module 170, and the performance adjustment module 190. The workload module 170, the timer 180, and the performance adjustment module 190 may each be implemented as hardware, software, or a combination of hardware and software.

When the workload module 170, the timer 180 and the performance adjustment module 190 are implemented in software, the program is stored in the nonvolatile memory device 200, and when the semiconductor storage device 10 is powered on Volatile memory device 200 to the SRAM 130 and executed by the CPU 150. [

The clock generator 195 generates a clock signal necessary for the operation of the CPU 150, the DRAM 120, and the nonvolatile memory device 200, and provides the clock signal to the corresponding device. The speeds of the clock signals provided to the CPU 150, the DRAM 120, and the nonvolatile memory device 200 may be different from each other. The clock generator 195 adjusts the speed of the clock signal applied to the CPU 150, the DRAM 120, and the nonvolatile memory device 200, respectively, according to the performance level determined in the performance adjustment module 190, The performance of the storage device 10 can be adjusted.

Although not shown in the figure, the semiconductor storage device 10 includes a ROM (not shown) for storing code data to be executed upon power-on of the semiconductor storage device 10, a nonvolatile memory device 200, And an ECC engine (not shown) for encoding the data to be stored in the nonvolatile memory device 200 and decoding the data read from the nonvolatile memory device 200.

FIG. 3 schematically shows the structure of the nonvolatile memory device 200 shown in FIG. With reference thereto, the non-volatile memory device 200 may include a plurality of memory elements. In FIG. 3, a non-volatile memory device 200 having a 4-channel / 3-bank hardware structure is illustrated by way of example, but the present invention is not limited thereto.

In the semiconductor storage device 10 shown in FIG. 3, the controller 100 and the non-volatile memory device 200 are connected by four channels (Channels A, B, C, and D) The elements CA0 to CA2, CB0 to CB2, CC0 to CC2, and CD0 to CD2 are connected. However, it goes without saying that the number of channels and the number of banks are not limited thereto and can be changed.

In the semiconductor storage device 10 having such a structure, the performance control unit of the semiconductor storage device 10 is a unit in which the entire nonvolatile memory device 200, the individual memory devices (memory chips) of the nonvolatile memory device 200 May be a bus (channel) unit, a bank unit, or an individual device unit. Here, a bank is a group of memory elements located at the same offset on different channels.

4 is a schematic block diagram of a host 20 in accordance with one embodiment of the present invention. 4, the system includes a CPU 210, a memory 220, a bus 230, a storage device interface 240, a workload module 250, a timer 260, and a performance adjustment module 270 .

The storage interface 240 has an interface protocol for communicating with the semiconductor storage device 10.

The CPU 210 performs all control operations for writing / reading data to / from the semiconductor storage device 10.

The workload module 250 may collect workload data associated with the workload being applied to the semiconductor storage device 10 and may predict the workload based on the collected workload data.

The performance adjustment module 270 determines the target performance level according to the workload predicted by the workload module 250 and adjusts the performance of the semiconductor storage device 10 by applying the determined performance level.

 The timer 260 provides time information to the CPU 210, the workload module 250, and the performance adjustment module 270. The workload module 250, the timer 260, and the performance adjustment module 270 may be implemented as software, hardware, or a combination of software and hardware, respectively.

The workload module 250 and the performance adjustment module 270 are for controlling or controlling the performance of the semiconductor storage device 10 at the host 20 and the semiconductor storage device 10 The host 20 may not have the workload module 250 and the performance adjustment module 270 when the performance is adjusted by itself.

5 is a flowchart illustrating a method for adjusting the performance of the semiconductor storage device 10 according to an embodiment of the present invention. The method for controlling the performance of the semiconductor storage device 10 according to an embodiment of the present invention is a method for controlling the performance of the semiconductor storage device 10, the host 20 or the semiconductor storage device 10 and the host 20 .

The performance control method according to an embodiment of the present invention is described with reference to an example implemented in the semiconductor storage device 10, but the present invention is not limited thereto as described above.

Referring to FIG. 5, the controller 100 collects workload data related to a workload applied to the semiconductor storage device 10 (S100), and predicts a workload based on the collected workload data (S110). The controller 100 determines the target performance level according to the predicted workload (S120), and applies the determined performance level to the operation of the semiconductor storage device 10 (S130).

For methods (S100, S110) of collecting workload data related to the workload applied to the semiconductor storage device 10 and predicting the workload based on the collected workload data, Korean Patent Application No. 10-2010-0080697 The contents of which are incorporated herein by reference.

The method disclosed in Korean Patent Application No. 10-2010-0080699 refers to a method (S120) for determining a target performance level according to a predicted workload.

Reference is made to Korean Patent Application No. 10-2010-0080698 for a method of applying the determined performance level to the operation of the semiconductor storage device 10 (S130).

In order to implement the performance adjustment method according to the embodiment of the present invention, a protocol for controlling performance between the host 20 and the semiconductor storage device 10 is required. That is, a protocol for performance control is required for transmission of commands and information related to performance adjustment between the host 20 and the semiconductor storage device 10.

FIG. 6 is a flowchart schematically illustrating a host-semiconductor storage device interface method for controlling performance of a semiconductor storage device according to an embodiment of the present invention. Referring to FIG. 6, the host 20 may transmit a configuration request command for controlling performance to the semiconductor storage device 10 (S610). Upon receipt of the setting request command of the host 20, the semiconductor storage device 10 sets (i.e., stores) the corresponding performance control parameter value of the semiconductor storage device to a specific value included in the command and performs an operation . After completing the operation, the host 20 can transmit a setting response signal (S620).

The setting request command sets the following types of commands: performance control enable / disable command, adjusted performance (or performance level) setting command, type of performance controlled command (e.g., write command, read command, (Or a minimum performance level) setting command, a maximum performance (or maximum performance level) setting command, an initial performance (or a minimum performance level setting command), an instruction to set a duration The initial performance level setting command, the performance adjustment cycle setting command, the performance adjustment variation (or the number of variation levels) setting instruction, the performance adjustment reset instruction, the performance adjustment checkpoint setting instruction, and the virtual workload history setting instruction can do.

Upon receipt of the above-described setting request command from the host 20, the semiconductor storage device 10 stores the setting value included in the setting request command in the corresponding memory or the corresponding register.

FIG. 8 shows performance control parameters stored in a semiconductor storage device for a method of adjusting the performance of a semiconductor storage device according to an embodiment of the present invention. The performance adjustment parameters shown in FIG. 8 may be set in the semiconductor storage device 10 by a configuration request command of the host. Of course, the performance tuning parameters may be set in other ways than the configuration request command of the host.

The performance control enable / disable command is a command for enabling or disabling the performance control function of the semiconductor storage device 10, in which the host 20 is connected to the semiconductor storage device 10 according to an embodiment of the present invention When the performance control enable command is sent to the semiconductor storage device 10 to enable the performance control method, the semiconductor storage device 10 sets the performance control flag shown in FIG. 8 in response to the performance control enable command (For example, set to "1"), and can transmit the setting response signal to the host 20.

When the host 20 transmits a performance control disable command to the semiconductor storage device 10 to disable the performance adjustment method of the semiconductor storage device 10 according to an embodiment of the present invention, (E. G., Set to '0') and send a configuration response signal to the host 20 in response to the performance control disable command.

The command to set the adjusted performance (or performance level) is a command to inform the semiconductor storage device 10 of the performance adjusted by the host 20 when the host 20 adjusts the performance of the semiconductor storage device 10 . The semiconductor storage device 10 may set the corresponding performance control parameter (i.e., the performance of the semiconductor storage device) to the value included in the command in response to the adjusted performance (or performance level) setting command.

The instruction for setting the kind of performance-controlled instruction (for example, a write instruction, a read instruction, and the like) is an instruction for setting which performance of the semiconductor storage device 10 is to be adjusted. For example, the read performance of the semiconductor storage device 10 may be adjusted, the write performance may be adjusted, and both the read performance and the write performance may be adjusted.

The host 20 may determine the type of command to be performance-controlled and inform the semiconductor storage device 10 of the command.

The duration (or step) of the idle time refers to the length or step of the idle time inserted in the middle of operation of the semiconductor storage device 10 in order to control the performance of the semiconductor storage device 10. The idle time may be inserted using the timer 180 or may be inserted into the execution of a meaningless operation (for example, a NOP operation). The timer 180 may be implemented in hardware or software.

In order to effectively and decisively adjust the performance of the semiconductor storage device 10, an idle time may be generated in addition to the unit operation of the semiconductor storage device 10. [ For example, a program operation to the nonvolatile memory 200, a read operation from the nonvolatile memory 200, a read operation to the internal buffer (e.g., page buffer) of the nonvolatile memory 200, Write operation, a read / write operation to a controller buffer (for example, DRAM or SRAM), and a host interface read / write operation, idle time for a certain period of time or generation of idle time proportional to the amount of data to be processed .

The duration (or step) of the idle time may be determined in the semiconductor storage device 10 and reported to the host 20 or may be determined by the host 20 and informed to the semiconductor storage device 10.

The instruction to set the lowest performance (or lowest performance level), the instruction to set the maximum performance (or maximum performance level), and the initial performance (or initial performance level) are each set by the host 20 to the lowest performance, As shown in Fig.

The initial performance of the semiconductor storage device 10 is a performance applied during an initial operation period of the semiconductor storage device 10 (e.g., a predetermined period from the power-on time) Lower and upper limits of adjustable performance. The minimum performance, the maximum performance, and the initial performance of the semiconductor storage device 10 may be preset in the semiconductor storage device 10, but may be set by an instruction of the host 20.

The performance adjustment period setting command is a command for setting the performance adjustment period.

When the semiconductor storage device 10 receives the performance adjustment period setting command from the host 20, it sets the performance adjustment period to the value included in the instruction. The semiconductor storage device 10 may calculate a new performance level for each performance adjustment period, and apply the calculated new performance level to the semiconductor storage device 10. In this case, the applied performance level is maintained during the performance adjustment period, and a new performance level can be calculated and applied again at the end of the performance adjustment period. Here, the performance adjustment period may be a unit such as hour, day, week, month, and the like, but is not limited thereto. Also, the performance adjustment cycle may or may not match the performance prediction cycle. For example, the performance prediction is on a time-by-time basis, but performance tuning can be up once and vice versa.

The command for setting the performance adjustment range (or number of variation levels) is an instruction for setting the performance adjustment range. The performance tuning fluctuation is intended to limit the difference between the adjusted performance (the performance to be newly applied) and the performance just before adjustment. The performance tuning fluctuation can be expressed as an absolute value, a ratio before performance, a ratio with highest performance, or a number of discrete levels.

When adjusting the performance of the semiconductor storage device 10, the host 20 or the semiconductor storage device 10 may perform the performance immediately prior to the adjustment of the adjusted performance, (+/- 10%, 20%, and 5%, for example) of the variation (+/- x%) (or the maximum performance).

The discrete level number refers to the number of levels (steps) that can be changed at a time when the performance level is represented by a plurality of discrete levels (i.e., steps). For example, if the performance adjustment fluctuation is set to two discrete levels, the discrete level of the adjusted performance (newly applied performance) can be determined only within two levels of the discrete level immediately before the adjustment.

The virtual workload history setting command is a command for the host 20 to set the virtual workload history instead of setting the initial performance level in the semiconductor storage device 10. [ Setting the virtual workload history is to set the parameters corresponding to the virtual workload to a specific value, assuming that the semiconductor storage device 10 has undergone a virtual workload for a predetermined period before power on.

FIG. 7 is a flowchart schematically illustrating a host-semiconductor storage device interface method for controlling performance of a semiconductor storage device according to another embodiment of the present invention. Referring to this, the host 20 can transmit an information request command to the semiconductor storage device 10 (S710). When the semiconductor storage device 10 receives the information request command of the host 20, the semiconductor storage device 10 may transmit the performance adjustment information of the semiconductor storage device 10 to the host 20 (S720). To this end, the semiconductor storage device 10 may transmit an information response signal including performance adjustment information to the host 20 (S270).

The performance adjustment information may be performance control parameters stored in the memory or registers of the semiconductor storage device 10. The performance adjustment parameters have been described above with reference to FIG. 8, and a description thereof will be omitted here.

 The performance adjustment information may also include the workload data shown in FIG.

The workload data may be data that is collected to predict the workload and may be a workload parameter value that has been counted for a predetermined period of time. The workload parameters include the number of commands that the host 20 applies to the storage device 10 as shown in Figure 9, the number of write commands that the host 20 applies to the storage device 10, The number of read commands applied to the storage device 10 by the host device 20, the amount of data transferred to / from the host in response to the command, the amount of data received from the host in response to the write command, A data amount, a number of program operations performed within the semiconductor storage device, and a number of read operations performed within the semiconductor storage device.

The performance adjustment parameter values that are set and transmitted from the host 20 to the semiconductor storage device 10 may be transmitted to the semiconductor storage device 10 through respective individual instructions for the performance adjustment described above, More than one performance control parameter value may be sent to the semiconductor storage device 10. Likewise, performance adjustment information may also be reported to the host 20 from the semiconductor storage device 10, either individually or collectively.

10 is a table showing a format of a setup request command according to an embodiment of the present invention. The host 20 is configured with a feature field, a count field, a logic block address (LBA) field, a device field, and a command field as shown in FIG. 10 for setting performance control parameters of the semiconductor storage device 10 To the semiconductor storage device 10. [0033] FIG. Each field included in the instruction may be configured with a predetermined number of bits. For example, each of the command field, the device field, and the count field may be composed of 8 bits.

The command field may function to discriminate the type of the setting request command, and at least one of the feature field, the count field, and the LBA (Logic Block Address) field may be set to a value of the performance adjustment parameter .

11A and 11B are tables showing the format of the performance adjustment enable / disable command and information request command according to an embodiment of the present invention, respectively. The performance adjustment enable command shown in FIG. 11A is set such that the command field is set to a predetermined value (e.g., FAh), the feature field is set to '1', the least significant bit of the count field is set to '1' 0 ".

If the least significant bit of the count field is set to ' 1 ', the instruction becomes a performance control enable command and the least significant bit of the count field is set to ' 0 ' The semiconductor storage device 10 may set the performance adjustment flag shown in Figure 8 in response to the performance adjustment enable command and reset the performance adjustment flag shown in Figure 8 in response to the performance adjustment disable instruction can be set. The semiconductor storage device 10 may then send a performance enable / disable response signal to the host 20.

The information request command shown in Fig. 11B is set such that its command field is set to a predetermined value (e.g., FAh), its feature field is set to '2', and its count field is set to '1'. Here, the count field is a value for designating the amount of performance adjustment information to be received from the semiconductor storage device 10. Thus, in response to the information request command with the count field set to '1', the semiconductor storage device 10 may report the performance adjustment information of one sector to the host 20.

12 is a table showing the format of an information response command according to an embodiment of the present invention.

The host 20 can apply an information request command in a format similar to the format shown in Fig. 10 to the semiconductor storage device 10. [ Then, the semiconductor storage device 10 can transmit the performance adjustment parameter value or the collected workload data to the host 20 through the information response command in the format as shown in FIG. The information response command includes a response signal composed of a feature field, a count field, a logic block address (LBA) field, a device field, and a command field, and information data For example, one sector of information data).

13 is a flowchart illustrating a method of interfacing a host and a semiconductor storage device according to an embodiment of the present invention.

When the power of the semiconductor storage device 10 is powered on (S810), the host 20 may enable performance control of the semiconductor storage device 10 via the command (S820) . That is, the host 20 may apply the performance control enable command to the semiconductor storage device 10 in order to enable the performance adjustment of the semiconductor storage device 10.

Next, in steps S830 to S850, the host 20 sets various performance control parameters (e.g., initial performance level, type of performance control command, performance control cycle, etc.) necessary for performance adjustment of the semiconductor storage device 10 Can be set. When the performance adjustment parameters are set, the semiconductor storage device 10 collects workload data (S860). The semiconductor storage device 10 starts performance adjustment when sufficient workload data for performance adjustment is collected (S870).

In another embodiment of the present invention, the workload data collection of the semiconductor storage device 10 may be made by the host 20, unlike that shown in FIG. That is, the host 20 can collect workload data and start performance tuning according to the collected workload data. When a new performance level is determined based on the collected workload data, the host 20 can set the adjusted performance through the command to the semiconductor storage device 10. Alternatively, the host 20 may determine the idle time according to the new performance level and set it to the semiconductor storage device 10 through an instruction. Then, the semiconductor storage device 10 adjusts the performance according to the set performance or idle time.

Meanwhile, the host 20 may transmit the information request command to the semiconductor storage device 10 to obtain the performance adjustment information (S880). Then, the semiconductor storage device 10 may transmit an information response signal including performance adjustment information to the host 20 (S890).

14 and 15 are block diagrams of an electronic system having a semiconductor storage device according to an embodiment of the present invention, respectively.

14, an electronic system 900 according to an embodiment of the present invention includes a semiconductor storage device 10, a power supply 910, a central processing unit (CPU) 920 (RAM) 930, a user interface 940, and a system bus 950 for electrically connecting these components.

The CPU 920 controls the overall operation of the system 900 and the RAM 930 stores the information necessary for the operation of the system 900. The User Interface 940 controls the interface between the system 900 and the user Lt; / RTI > The power supply 910 supplies power to the internal components (i.e., CPU 920, RAM 930, user interface 940, memory system 500, etc.).

The CPU 920 may correspond to the host 20 described above and the semiconductor storage device 10 may store or read data in response to the command of the host 20. [

15A and 15B are block diagrams of an electronic system according to another embodiment of the present invention, respectively.

The electronic system 900 'shown in FIG. 15A has a configuration similar to that of the electronic system 900 shown in FIG. 14, so the differences are mainly described in order to avoid duplication of explanation.

The electronic system 900 'shown in FIG. 15A further includes a RAID controller card 960 as compared to the electronic system 900 shown in FIG. The semiconductor storage device 10 can be mounted on the RAID controller card 960 and can interface with the host via the RAID controller card 960 instead of directly interfacing with the host. At this time, a plurality of (two or more) semiconductor storage devices 10-1 to 10-k (k is an integer of 2 or more) may be mounted on the RAID controller card 960. [ The RAID controller card 960 of the electronic system 900 'shown in FIG. 15A is implemented as a separate product outside the semiconductor storage devices 10-1 to 10-k.

The electronic system 900 "shown in FIG. 15B has a similar configuration to the electronic system 900 'shown in FIG. 15A, and therefore focuses on differences to avoid duplication of description.

The RAID controller card 960 of the electronic system 900 'shown in FIG. 15B is implemented as a single product with the semiconductor storage devices 10-1 through 10-k, Gt; 900 '. ≪ / RTI >

When the RAID controller card 960 is provided as described above, the above-described interface method according to the embodiment of the present invention can be implemented in the RAID controller card 960.

16 is a block diagram of a computing system 1000 (PC) having a semiconductor storage device 10 according to an embodiment of the present invention. The computing system 1000 includes a central processing unit 1110, an accelerated graphics port 1120, a main memory 1130, a north bridge 1140, a semiconductor storage device An SSD 10, a keyboard controller 1160, a printer controller 1170, and a south bridge 1180, for example.

The computing system 1100 may also be a block of a personal computer or notebook computer that the SSD 10 uses as the primary storage device on behalf of the hard disk drive. However, the scope of the present invention is not limited thereto.

In the computing system 1000, the central processing unit 1110, the AGP unit 1120, and the main memory 1130 are connected to the north bridge 1140 and are connected to the SSD 10, the keyboard controller 1160, And various peripheral devices (not shown) are connected to the south bridge 180.

The north bridge 1140 is an integrated circuit on the socket of the central processing unit 1110 with respect to the center of the main board 1110 and generally refers to a system controller including a host interface for connecting to the central processing unit 1110 do. The south bridge 1180 is an integrated circuit on the peripheral component interconnect (PCI) slot in the center of the main board, and generally refers to a bridge from a host bus to a bus connected via a PCI bus.

AGP is a bus specification that enables rapid realization of 3D graphical representations. The AGP device 1120 may include a video card or the like for playing back a monitor image. The main memory 1130 may be implemented as a RAM (Random Access Memory), which is a volatile memory device, but the scope of the present invention is not limited thereto.

In the computing system 1100 according to an embodiment of the present invention, the SSD 10 may be connected to the south bridge 180, but the present invention is not limited thereto. The SSD 10 may be connected to the north bridge 1140 Or may be a structure directly connected to the CPU 1110.

While the present invention has been described with reference to exemplary embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the scope of the present invention. Accordingly, the true scope of the present invention should be determined by the technical idea of the appended claims.

Semiconductor storage: 10
Host: 20
Controller: 100
Nonvolatile memory device: 200
CPU: 150, 210
Host interface: 110
DRAM: 120
SRAM: 130
Memory interface: 140
Timers: 150, 260
Buses: 160, 230
Workload modules: 170, 250
Performance Control Modules: 190, 270
Clock Generator: 195
Storage interface: 240

Claims (20)

A method for interfacing between a semiconductor storage device and a host for controlling performance of a semiconductor storage device,
Receiving a configuration request command from the host;
The semiconductor storage device in response to the configuration request command setting a requested performance control parameter to a specific value; And
Sending a configuration response signal indicating that the semiconductor storage device has completed setting the performance tuning parameter to the host,
The setting request command
A feature field, a count field, a logic block address (LBA) field, a device field, and a command field,
The command field is set to a predetermined value for classifying the type of the setting request command,
Wherein at least one of the feature field, the count field, and the logic block address (LBA) field is set to a value of the performance adjustment parameter. A method for interfacing between a semiconductor storage device and a host for controlling performance of a semiconductor storage device,
Sending a configuration request command to the semiconductor storage device to set a performance control parameter required for performance control of the semiconductor storage device to a specific value by the host; And
Receiving a setup response signal from the semiconductor storage device in response to the setup request command, the setup response signal indicating that the performance adjustment parameter is set to the specific value;
The setting request command
A feature field, a count field, a logic block address (LBA) field, a device field, and a command field,
The command field is set to a predetermined value for classifying the type of the setting request command,
Wherein at least one of the feature field, the count field, and the logic block address (LBA) field is set to a value of the performance adjustment parameter. The method according to claim 1 or 2, wherein the setting request command
A performance adjustment enable / disable command, a controlled performance setting command, a command for setting the kind of performance-controlled command, a command for setting the duration of the idle time inserted for performance adjustment, a minimum performance setting command, A semiconductor storage device including at least one of a setting command, an initial performance setting command, a performance adjustment cycle setting command, a performance adjustment variable setting command, a performance adjustment reset command, a performance adjustment check point setting command, and a virtual workload history setting command, How to interface between hosts. 4. The semiconductor storage device according to claim 3, wherein the semiconductor storage device
And a memory or register for storing the performance control parameter. delete delete A method for interfacing between a semiconductor storage device and a host for controlling performance of a semiconductor storage device,
Receiving an information request command from the host; And
The semiconductor storage device sending an information response signal to the host in response to the information request command, the information response signal including a requested performance adjustment parameter,
The information request command
A feature field, a count field, a logic block address (LBA) field, a device field, and a command field,
The command field is set to a predetermined value to identify the type of the information request command,
Wherein at least one of the feature field, the count field, and the logic block address (LBA) field is set to a value of the performance adjustment parameter. A method for interfacing between a semiconductor storage device and a host for controlling performance of a semiconductor storage device,
Transmitting, by the host, an information request command to the semiconductor storage device requesting transmission of a performance adjustment parameter of the semiconductor storage device; And
Receiving an information response signal including a value of the performance adjustment parameter transmitted in response to the information request command from the semiconductor storage device,
The information request command
A feature field, a count field, a logic block address (LBA) field, a device field, and a command field,
The command field is set to a predetermined value to identify the type of the information request command,
Wherein at least one of a feature field, a count field, and a logic block address (LBA) field is set to a value of the performance adjustment parameter. 9. The method of claim 7 or 8, wherein the performance adjustment parameter
Wherein at least one of the adjusted performance, the type of command subject to performance adjustment, the duration of the idle time inserted for performance adjustment, and the workload parameter count value. 10. The semiconductor storage device according to claim 9, wherein the semiconductor storage device
And a memory or register for storing the performance control parameter. delete A recording medium on which a program for executing a semiconductor storage device and a host-to-host interface method according to any one of claims 1, 2, 7, and 8 is recorded. Nonvolatile memory; And
And a controller for controlling the nonvolatile memory in response to a request from the host,
The controller
Receiving a configuration request command from the host, setting a requested performance control parameter to a specific value in response to the configuration request command, and transmitting a configuration response signal to the host indicating that the performance adjustment parameter has been set,
The setting request command
A feature field, a count field, a logic block address (LBA) field, a device field, and a command field,
The command field is set to a predetermined value for classifying the type of the setting request command,
Wherein at least one of the feature field, the count field, and the logic block address (LBA) field is set to a value of the performance adjustment parameter. A CPU; And
Wherein the controller transmits a setting request command to the semiconductor storage device to set a performance control parameter of the semiconductor storage device to a specific value under the control of the CPU, And an interface unit for receiving a setting response signal indicating that the setting value is set to a specific value,
The setting request command
A feature field, a count field, a logic block address (LBA) field, a device field, and a command field,
The command field is set to a predetermined value for classifying the type of the setting request command,
Wherein at least one of the feature field, the count field, and the logic block address (LBA) field is set to a value of the performance adjustment parameter. The method according to claim 13 or 14, wherein the setting request command
A performance adjustment enable / disable command, a controlled performance setting command, a command for setting the kind of performance-controlled command, a command for setting the duration of the idle time inserted for performance adjustment, a minimum performance setting command, A performance adjustment cycle setting command, a performance adjustment reset command, a performance adjustment checkpoint setting command, and a virtual workload history setting instruction. delete delete Nonvolatile memory; And
And a controller for controlling the nonvolatile memory in response to a request from the host,
The controller
Receiving an information request command from the host, and responsive to the information request command, transmitting an information response signal including a requested performance control parameter to the host,
The information request command
A feature field, a count field, a logic block address (LBA) field, a device field, and a command field,
The command field is set to a predetermined value to identify the type of the information request command,
Wherein at least one of the feature field, the count field, and the logic block address (LBA) field is set to a value of the performance adjustment parameter. A CPU; And
Wherein the controller is configured to transmit an information request command to the semiconductor storage device to request transmission of a performance adjustment parameter of the semiconductor storage device under the control of the CPU and to transmit the value of the performance adjustment parameter transmitted in response to the information request command from the semiconductor storage device And an interface unit for receiving the information response signal,
The information request command
A feature field, a count field, a logic block address (LBA) field, a device field, and a command field,
The command field is set to a predetermined value to identify the type of the information request command,
Wherein at least one of the feature field, the count field, and the logic block address (LBA) field is set to a value of the performance adjustment parameter. 20. The method of claim 18 or 19, wherein the performance adjustment parameter
The at least one of the adjusted performance, the type of command subjected to the performance adjustment, the duration of the idle time inserted for performance adjustment, and the workload parameter count value.

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