KR101819644B1 - Voltage regulator circuit - Google Patents

Abstract

Off current in the transistor is reduced, and the conversion efficiency of the output voltage in the voltage adjustment circuit is improved. A gate electrode, a source, and a drain, a gate electrically connected to a source or a drain, a first signal input to one of a source and a drain, and a channel forming layer having an oxide semiconductor layer having a carrier concentration of 5 x 10 ¹⁴ / And a capacitive element having a first electrode and a second electrode, the first electrode being electrically connected to the other of the source and the drain of the transistor, and the second signal being a clock signal being input to the second electrode, The voltage of the signal is stepped up or stepped down and the third signal which is the stepped up or stepped down voltage is outputted as the output signal through the other of the source and the drain of the transistor.

Description

[0001] VOLTAGE REGULATOR CIRCUIT [0002]

One embodiment of the present invention relates to a voltage regulating circuit constituted by a transistor using an oxide semiconductor.

A technique of forming a thin film transistor (TFT) using a semiconductor thin film formed on a substrate having an insulating surface has attracted attention. The thin film transistor is used in a display device typified by a liquid crystal television. Silicon-based semiconductor materials are known as semiconductor thin films applicable to thin film transistors, and oxide semiconductors are attracting attention as other materials.

As the material of the oxide semiconductor, it is known that zinc oxide or zinc oxide is used as a component. And an amorphous oxide (oxide semiconductor) having an electron carrier concentration of less than 10 ¹⁸ / cm 3 (Patent Documents 1 to 3).

Japanese Patent Application Laid-Open No. 2006-165527 Japanese Patent Application Laid-Open No. 2006-165528 Japanese Patent Application Laid-Open No. 2006-165529

However, the oxide semiconductor deviates from the stoichiometric composition in the thin film forming process. For example, the electrical conductivity of the oxide semiconductor is changed by excess or shortage of oxygen. Further, hydrogen introduced during the formation of the thin film of the oxide semiconductor forms an oxygen (O) -hydrogen (H) bond to become an electron donor, thereby changing the electric conductivity. Further, since O-H is a polar molecule, characteristics of the active device such as a thin film transistor manufactured by an oxide semiconductor become a factor of variation.

Even when the electron carrier concentration is less than 10 ¹⁸ / cm 3, the oxide semiconductor is substantially n-type, and the ON / OFF ratio of the thin film transistor disclosed in Patent Documents 1 to 3 can be obtained to 10 ³ . The on-off ratio of such a thin film transistor is low because of a high off current.

Further, when a transistor having a high off-state current is used to constitute a voltage adjusting circuit such as a voltage raising circuit, a problem arises in that a current flows through the transistor even during non-operation, have.

In view of such a problem, one aspect of the present invention is to provide a thin film transistor having stable electrical characteristics (for example, an off current is extremely reduced). Another object is to improve the conversion efficiency to a desired voltage in the voltage adjusting circuit.

One mode of the present invention is to provide a voltage boosting circuit or a voltage boosting circuit using a transistor having an oxide semiconductor having a higher energy gap than that of a silicon semiconductor in a channel forming layer which is an intrinsic or substantially intrinsic semiconductor which is highly purified by removing impurities which become an electron donor And a voltage regulating circuit such as a voltage step-down circuit. As a result, the leakage current (off current) in the OFF state in the transistor can be reduced, and the conversion efficiency to the voltage of the desired value can be improved by reducing the off current in the transistor.

The concentration of hydrogen contained in the oxide semiconductor is 5 × 10 ¹⁹ / cm 3 or less, preferably 5 × 10 ¹⁸ / cm 3 or less, and more preferably 5 × 10 ¹⁷ / cm 3 or less. Further, hydrogen or OH bonds contained in the oxide semiconductor are removed. The carrier concentration is 5 x 10 ¹⁴ / cm 3 or less, preferably 5 x 10 ¹² / cm 3 or less.

The energy gap is 2 eV or more, preferably 2.5 eV or more, more preferably 3 eV or more, and the impurity such as hydrogen which forms the donor is reduced as much as possible and the carrier concentration is 1 x 10 ¹⁴ / 10 < ¹² > / cm < 3 > or less.

In the transistor having the oxide semiconductor, the off-current per channel width 1㎛ ^{10aA / ㎛ (1 × 10 -17} A / ㎛) or less, and further ^{1aA / ㎛ (1 × 10 -18} A / ㎛) or less, and further (1 × 10 ^-20 A / μm) or less, preferably 1 zA / μm (1 × 10 ^-21 A / μm) or less, and can be considerably lower than that of a conventional transistor using silicon. In addition, even when the temperature of the transistor is 85 캜, the off current per 1 탆 channel width is set to 100 zA / 탆 or less, preferably 10 zA / 탆 or less, which can be considerably lower than that of conventional transistors using silicon.

By using a transistor using an oxide semiconductor layer whose hydrogen concentration is sufficiently reduced and which is made highly purified, a voltage adjustment circuit with less power consumption due to a leakage current can be realized, compared with the case of using a transistor using a conventional silicon.

An embodiment of the present invention is a semiconductor device having a gate, a source, and a drain, a gate electrically connected to a source or a drain, a first signal input to one of a source and a drain, an oxide semiconductor layer serving as a channel forming layer, A capacitor having a first electrode and a second electrode, the first electrode being electrically connected to the other of the source and the drain of the transistor, and the second signal being a clock signal being input to the second electrode, And outputs a third signal, which is the step-up or step-down voltage, through the other of the source and the drain of the transistor as an output signal.

One aspect of the present invention is a voltage regulating circuit having an n-stage unit boosting circuit electrically connected in series with each other (n is a natural number of 2 or more), wherein 2M-1 stages (M is 1 to n / 2, The number of the source and the drain, the gate, the source and the drain, the first transistor having the gate electrically connected to one of the source and the drain, the oxide semiconductor layer serving as the channel forming layer and the off current of 100 zA / A first capacitor having one electrode and a second electrode, the first electrode being electrically connected to the other of the source and the drain of the first transistor, and the clock signal being input to the second electrode, A second transistor having a gate, a source and a drain, a gate electrically connected to one of the source and the drain, an oxide semiconductor layer serving as a channel forming layer, and an off current of 100 zA / And it has a second electrode, the first electrode is electrically connected to the other side of the source and drain of the second transistor, a first voltage regulating circuit having a second capacitor that is an inverted clock signal input to the second electrode.

One aspect of the present invention is a voltage regulating circuit having an n step (n is a natural number of 2 or more) unit step-down circuits electrically connected to each other in series connection, wherein the 2M-1 stage (M is 1 to n / 2, And a first electrode and a second electrode having an off current of 100 < z > / mu m or less and a first electrode and a second electrode, wherein the first electrode, the second electrode, And a second capacitive element, which is electrically connected to the gate of the first transistor and has a clock signal input to the second electrode, wherein the unit down voltage circuit of the 2M stage has a gate, a source and a drain, A second transistor electrically connected to a gate and a source or a drain of one transistor and having an oxide semiconductor layer as a channel forming layer and having an off current of 100 zA / 占 퐉 or less, a first electrode and a second electrode, It is electrically connected to the other side of the gate of the second transistor, and a source and a drain, a second voltage regulating circuit having a second capacitor that is an inverted clock signal input to the second electrode.

According to one aspect of the present invention, since the leak current of the transistor can be reduced and the voltage drop of the output signal can be reduced, the conversion efficiency to a desired voltage can be improved.

1 is a circuit diagram showing an example of the configuration of a voltage regulating circuit.
2 is a timing chart for explaining an example of the operation of the voltage regulating circuit shown in Fig.
3 is a circuit diagram showing an example of the configuration of the voltage regulating circuit.
4 is a circuit diagram showing an example of the configuration of the voltage regulating circuit.
5 (A) and 5 (B) are views for explaining a transistor.
6 (A) to 6 (E) are views for explaining a method of manufacturing a transistor.
7A and 7B are views for explaining a transistor.
8 (A) to 8 (E) are diagrams for explaining a method for manufacturing a transistor.
9A and 9B are views for explaining a transistor.
10 (A) to 10 (E) are diagrams for explaining a method of manufacturing a transistor.
11 is a longitudinal sectional view of a reverse stagger type thin film transistor using an oxide semiconductor.
12 is an energy band diagram (schematic diagram) taken along the line A-A 'shown in FIG.
13A shows a state in which a positive potential (+ VG) is applied to the gate electrode 1001 and FIG. 13B shows a state in which a negative potential -VG is applied to the gate electrode 1001 Fig.
14 is a diagram showing the relationship between the vacuum level and the work function? M of the metal and the electron affinity (?) Of the oxide semiconductor.
15 is a circuit diagram for evaluating characteristics of a transistor using an oxide semiconductor.
16 is a timing chart for evaluating characteristics of a transistor using an oxide semiconductor.
17 is a diagram showing the characteristics of a transistor using an oxide semiconductor.
18 is a diagram showing the characteristics of a transistor using an oxide semiconductor.
19 is a diagram showing the characteristics of a transistor using an oxide semiconductor.
20A to 20E are views for explaining a method for manufacturing a transistor.
Figs. 21A to 21D are views for explaining a method for manufacturing a transistor.
22 (A) to 22 (D) are diagrams for explaining a method of manufacturing a transistor.
23 is a view for explaining a transistor.
24 (A) and 24 (B) are diagrams for explaining an electronic apparatus.

An embodiment of the present invention will be described below with reference to the drawings. It should be understood, however, by those skilled in the art that the present invention is not limited to the following description, and that various changes in form and details may be made therein without departing from the spirit and scope of the present invention. Therefore, the present invention is not construed as being limited to the description of the embodiments described below.

(Embodiment 1)

In the present embodiment, a voltage regulating circuit, which is one aspect of the present invention, will be described.

An example of the configuration of the voltage regulating circuit of the present embodiment is that a signal S1 and a signal S2 are input as input signals and the voltage of the signal S1 is increased or decreased by stepping up or down the input signal S1, And has a function of outputting a signal S3 which is a voltage as an output signal. An example of the configuration of the voltage regulating circuit of the present embodiment will be described with reference to Fig. 1 is a circuit diagram showing an example of the configuration of a voltage regulating circuit in the present embodiment.

The voltage adjusting circuit shown in Fig. 1 has a transistor 101 and a capacitor element 102. Fig.

In this specification, a field effect transistor can be used as the transistor, for example.

Further, in this specification, the field effect transistor has at least a gate, a source, and a drain. As the field effect transistor, for example, a thin film transistor (also referred to as TFT) can be used. As the field effect transistor, for example, a top gate type or bottom gate type transistor can be used. The field effect transistor may be an N-type conductivity type.

The gate refers to a part or all of the gate electrode and the gate wiring. The gate wiring means a wiring for electrically connecting the gate electrode of at least one transistor to another electrode or another wiring.

The source refers to a part or all of the source region, the source electrode, and the source wiring. The source region is a region in which the resistance value of the semiconductor layer is lower than the channel forming layer. The source electrode is a conductive layer in a portion connected to a source region. The source wiring means a wiring for electrically connecting the source electrode of at least one transistor to another electrode or another wiring.

The drain refers to a part or all of the drain region, the drain electrode, and the drain wiring. Drain region means a region in which the resistance value of the semiconductor layer is lower than the channel forming region. And the drain electrode is a conductive layer in a portion connected to the drain region. The drain wiring means a wiring for electrically connecting the drain electrode of at least one transistor to another electrode or another wiring.

Also, in this specification, since the source and drain of the transistor are replaced with each other depending on the structure and operating conditions of the transistor, it is difficult to limit which is the source or the drain. Therefore, in this document (specification, claims, drawings, and the like), either the source or the drain is denoted as one of the source and the drain, and the other is denoted as the other of the source and the drain.

In this specification, the field effect transistor is a transistor having an oxide semiconductor layer functioning as a channel forming layer. The hydrogen concentration of the channel forming layer is set to 5 x 10 ¹⁹ atoms / cm 3 or less, preferably 5 x 10 ¹⁸ atoms / cm 3 or less, more preferably 5 x 10 ¹⁷ atoms / cm 3 or less. This hydrogen concentration is, for example, a value obtained by secondary ion mass spectroscopy (SIMS). The carrier concentration of the transistor is set to 1 × 10 ¹⁴ / cm 3 or less, preferably 1 × 10 ¹² / cm 3 or less.

Further, in this specification, for example, a capacitive element having a structure including a first electrode, a second electrode, and a dielectric may be used as the capacitive element.

A signal S1 is input to one of the source and the drain of the transistor 101 and a voltage of the signal S3 is applied to the other of the source and the drain. do. The voltage adjusting circuit shown in Fig. 1 outputs the signal S3 through the other of the source and the drain of the transistor 101. [

In the transistor 101, the voltage adjustment operation differs depending on which of the signal S1 and the signal S3 is input to the gate. For example, when the signal S1 is input to the gate, the voltage of the signal S3 can be higher than the voltage of the signal S1, and when the signal S3 is input to the gate, The voltage of the signal S1 can be lower than the voltage of the signal S1. At this time, increasing the voltage of the signal S3 higher than the voltage of the signal S1 is called boosting, and lowering the voltage of the signal S3 lower than the voltage of the signal S1 is also referred to as step-down.

In general, a voltage refers to a difference in potential between two points (also referred to as a potential difference). However, the values of voltage and potential are sometimes denoted as volts (V) in the circuit diagram and the like. Therefore, in this specification, the potential difference between a potential at a certain point and a reference potential (also referred to as a reference potential) may be used as the voltage at this point, unless otherwise specified.

In the present specification, for example, an analog signal or a digital signal using a voltage or the like can be used as a signal. For example, as a signal using a voltage (also referred to as a voltage signal), it is preferable to use a signal having at least a first voltage state and a second voltage state. For example, A digital signal having a low-level voltage state as a two-voltage state, or the like can be used. The voltage at the high level is also referred to as a voltage (V _H ), and the voltage at a low level is also referred to as a voltage (V _L ). The voltage of the first voltage state and the voltage of the second voltage state may be different depending on the respective signals. Also, since there is an influence of noise or the like, the voltage of the first voltage state and the voltage of the second voltage state are constant And each value may be within a certain range.

In the capacitor device 102, the first electrode is electrically connected to the other of the source and the drain of the transistor 101, and the signal S2 is input to the second electrode. The connection portion between the first electrode of the capacitor device 102 and the other of the source and the drain of the transistor 101 is also referred to as a node N111.

The signal S1 has a function as a first input signal (also referred to as a signal IN _VC1 ) of the voltage adjusting circuit.

The signal S2 has a function as a second input signal (also referred to as signal IN _VC2 ) of the voltage adjusting circuit. As the signal S2, for example, a clock signal can be used. The clock signal is a signal in which the first voltage state and the second voltage state are periodically repeated. The values of the first voltage state and the second voltage state in the clock signal can be set appropriately.

Signal (S3) has a function of a (also referred to as the signal OUT _VC) output signal of the voltage regulating circuit.

Next, an example of the operation (also referred to as a driving method) of the voltage adjusting circuit shown in Fig. 1 will be described with reference to Fig. Fig. 2 is a timing chart for explaining an example of the operation of the voltage regulating circuit shown in Fig. 1, and shows the voltage waveforms of the signal S1, the signal S2 and the signal S3, respectively. In the example of the operation of the voltage regulating circuit shown in Fig. 1 described with reference to Fig. 2, the signal S1 is a binary digital signal of a high level and a low level, and the signal S2 is a high- Level is periodically repeated, and the transistor 101 is an N-type transistor and the signal S1 is input to the gate of the transistor 101. [

The operation of the voltage regulating circuit shown in Fig. 1 can be described by dividing into a plurality of periods. The operation in each period will be described below.

In the period 151, the signal S1 becomes a high level and the signal S2 becomes a low level.

At this time, the source and the drain of the transistor 101 become conductive, and the voltage of the node N111 begins to rise. The voltage of the node N111 rises to V1. V1 is V _H -V _th101 (the threshold voltage of the transistor 101). When the voltage of the node N111 becomes V1, the source and the drain of the transistor 101 become non-conductive, and the node N111 becomes a floating state. At this time, the voltage applied between the first electrode and the second electrode of the capacitive element 102 is V1 - V _L , and the voltage of the signal S3 becomes V1.

Next, in the period 152, the signal S1 maintains the high level state and the signal S2 becomes the high level.

At this time, since the transistor 101 is in a non-conductive state, the node N111 is in a floating state, and further the voltage applied to the second electrode of the capacitive element 102 changes from V _L to V _H , The voltage of the first electrode of the capacitive element 102 also starts to change. The voltage of the node N111 rises to a value larger than V1, that is, V2. The voltage V2 is V _H -V _th101 + V _H. At this time, the voltage applied between the first electrode and the second electrode of the capacitor 102 is V _H-V2, the voltage signal (S3) is a V2. As described above, in the period 152, the voltage of the signal S3, which is the output signal of the voltage regulating circuit, becomes a value obtained by stepping up the voltage of the signal S1 input to the voltage regulating circuit.

As described above, in the voltage regulating circuit of the present embodiment, since the input voltage signal can be changed to output a signal of higher voltage or lower voltage than the input voltage signal, the power consumption can be reduced.

In the voltage regulating circuit of the present embodiment, the transistor includes an oxide semiconductor layer having a function as a channel forming layer, and the channel forming layer has a hydrogen concentration of 5 x 10 ¹⁹ atoms / cm 3 or less, preferably 5 x 10 ¹⁸ atoms / cm 3 More preferably 5 × 10 ¹⁷ atoms / cm 3 or less, and the carrier concentration is 1 × 10 ¹⁴ / cm 3 or less, preferably 1 × 10 ¹² / cm 3 or less. The leak current of the transistor is low, so that the leakage of charges accumulated in the capacitor element can be reduced as compared with the conventional transistor, so that the arrival speed to the voltage of the desired value can be remarkably improved.

Further, the voltage regulating circuit of the present embodiment can form the capacitive element by the same process as the transistor. Thereby, an increase in the number of process steps can be reduced.

(Embodiment 2)

In this embodiment, a step-up circuit will be described as an example of a voltage regulating circuit which is an aspect of the present invention.

An example of the circuit configuration of the voltage regulating circuit of this embodiment will be described with reference to Fig. 3 is a circuit diagram showing an example of the circuit configuration of the voltage adjusting circuit of the present embodiment.

The voltage adjusting circuit shown in Fig. 3 has a unit boosting circuit 211_1 to a unit boosting circuit 211_n (n is a natural number of 2 or more), and each of the unit boosting circuits 211_1 to 211_n is connected in series Stage unit-boosting circuit electrically connected to each other.

Each of the unit booster circuit 211_1 to the unit booster circuit 211_n has a transistor 201 and a capacitor element 202. [

As the transistor 201, a transistor having an oxide semiconductor layer functioning as a channel forming layer can be used. The hydrogen concentration of the channel forming layer is set to 5 x 10 ¹⁹ atoms / cm 3 or less, preferably 5 x 10 ¹⁸ atoms / cm 3 or less, more preferably 5 x 10 ¹⁷ atoms / cm 3 or less. This hydrogen concentration is, for example, a value obtained by secondary ion mass spectroscopy (SIMS). The carrier concentration of the transistor 201 is 1 x 10 ¹⁴ / cm 3 or less, preferably 1 x 10 ¹² / cm 3 or less.

The gates of the transistors 201 in the unit voltage-boosting circuits 211_1 to 211_n are electrically connected to one of the source and the drain of the transistor 201, respectively. That is, the transistor 201 is diode-connected. The first electrode of the capacitor device 202 is electrically connected to the other of the source and the drain of the transistor 201.

In the unit step-up circuit of the K stage (K is a natural number of 2 to n), one of the source and the drain of the transistor 201 is connected to the other of the source and the drain of the transistor 201 in the K- And is electrically connected. The connection portion of the other of the source and the drain of the transistor 201 in the K-1 stage unit voltage booster circuit with one of the source and the drain of the transistor 201 in the K stage unit voltage booster circuit is connected to the node N1_M ( M is 1 to n / 2).

In the unit boosting circuit of the 2M-1 stage (where M is 1 to n / 2 and 2M is a natural number), the second electrode of the capacitive element 202 is electrically connected to the clock signal line 221, In the step-up circuit, the second electrode of the capacitor element 202 is electrically connected to the clock signal line 222. The clock signal CK1 is input to the clock signal line 221 and the clock signal CKB1 is input to the clock signal line 222. [ The clock signal CK1 and the clock signal CKB1 are in phase opposition. For example, when the clock signal CK1 is at a high level, the clock signal CKB1 is at a low level. The inverted signal of the clock signal CK1 may be used as the clock signal CKB1 and the voltage state of the clock signal CK1 may be obtained by using a NOT circuit such as an inverter, Can be generated by inverting. The values of the high level and low level voltages in the clock signal CK1 and the clock signal CKB1 can be set appropriately. The clock signal CK1 may be generated by using an oscillation circuit such as a ring oscillator and a buffer circuit. Further, not only the clock signal CK1 and the clock signal CKB1 but also clock signals of three or more phases can be used.

In the first stage unit boosting circuit, that is, the transistor 201 in the unit boosting circuit 211_1, the signal IN1 is input to one of the source and the drain.

Further, the other voltage of the source and the drain of the transistor 201 in the final stage unit boosting circuit, that is, the unit boosting circuit 211_n, becomes the voltage of the signal OUT1 which is the output signal of the voltage adjusting circuit. In the capacitor 202 in the unit boost circuit 211_n, the voltage Vc1 is applied to the second electrode. Voltage (Vc1) is may be any value, for example, it is possible to use a voltage value equal to the voltage (V _H) or a voltage (V _L). It is also preferable that the capacitance of the capacitive element 202 in the unit boost circuit 211_n is larger than the capacitance of the capacitive element 202 in the other unit boost circuits. Thereby, the voltage state of the output signal of the unit boosting circuit 211_n, that is, the signal OUT1 which is the output signal of the voltage adjusting circuit, can be more stabilized.

As described above, an example of the voltage regulating circuit according to the present embodiment has n stages of unit boosting circuits, and each unit boosting circuit has a diode-connected transistor and a capacitor element. As the diode-connected transistor, a transistor having a highly-purified oxide semiconductor layer is used as the channel forming layer. As a result, the holding time of the voltage of each node can be lengthened, the arrival time to the target voltage can be shortened, and the voltage conversion efficiency can be improved.

Next, an example of the operation of the voltage regulating circuit shown in Fig. 3 will be described.

The operation of the voltage regulating circuit shown in Fig. 3 can be described by dividing into a plurality of periods. The operation in each period will be described below. In the example of the operation of the voltage adjusting circuit shown in Fig. 3 described herein, a high-level signal is input as the signal IN1, a clock signal CK1 is changed to a high-level and low- It is assumed that the clock signal CKB1 is an inverted clock signal of the clock signal CK and the transistor 201 in each unit boosting circuit is an N type transistor and the threshold voltage of the transistor 201 in each unit boosting circuit is The same value will be described.

First, in the first period, the clock signal CK1 becomes low level and the clock signal CKB1 becomes high level.

At this time, the diode-connected transistor 201 is turned on by the unit boost circuit 211_1, and the voltage of the node N1_1 starts to rise. The voltage (also referred to as voltage V _N1 ) of the node N1_1 rises to V _IN1 (voltage of the signal IN1) -V _th201 (threshold voltage of the transistor 201). When the voltage (V _IN1 -V _th201), the voltage at the node (N1_1) is a diode-connected transistor 201 in the unit of the step-up circuit (211_1) and a non-conductive state, the nodes (N1_1) becomes a floating state.

Next, in the second period, the clock signal CK1 becomes the high level and the clock signal CKB1 becomes the low level.

At this time, in the unit boosting circuit 211_1, the transistor 201 is kept in a non-conductive state, the node N1_1 is in a floating state, and further, the second electrode of the capacitive element 202 in the unit boost circuit 211_1 since the voltage is changed to V _H that is, the voltage of the first electrode of the capacitor device 202 in conformity with the second electrode of the capacitor element 202 also begins to change. The voltage of the node N1_1 rises to V _IN1 -V _th201 + V _H. At this time, the voltage applied between the first electrode and the second electrode of the capacitive element 202 is V _IN1 -V _th201 . As described above, in the second period, the voltage of the node N1_1 becomes a value at which the voltage of the node N1_1 in the first period is increased.

In addition, being a voltage of the nodes (N1_1) V _IN1 -V _th201 + V _H, and comes into the conduction state diode-connected transistor 201 in the unit of the step-up circuit (211_2), start the voltage of nodes (N1_2) rising do. The voltage (also referred to as V _N2 ) of the node N1_2 rises to V _N1 -V _th201 . When the voltage V _N1 -V _th201 of nodes (N1_2) is a diode-connected transistor 201 in the unit of the step-up circuit (211_2) and a non-conductive state, the nodes (N1_2) becomes a floating state.

Next, in the third period, the clock signal CK1 becomes low level and the clock signal CKB1 becomes high level.

At this time, in the unit voltage step-up circuit 211_2, the transistor 201 is kept in a non-conductive state, the node N1_2 is in a floating state, and further, The voltage at the first electrode of the capacitive element 202 also starts to change in accordance with the second electrode of the capacitive element 202 because the voltage applied to the capacitive element 202 changes from V _L to V _H. The voltage of the node N1_2 rises to V _N1 -V _th201 + V _H. At this time, the voltage applied between the first electrode and the second electrode of the capacitive element 202 is V _N1 -V _th201 . Thus, in the third period, the voltage of the node N1_2 becomes the value at which the voltage of the node N1_2 in the second period is raised.

In addition, being a voltage of the nodes (N1_2) V _N1 -V _th201 + V _H, and comes into the conduction state diode-connected transistor 201 in the unit of the step-up circuit (211_3), start the voltage of nodes (N1_3) rising do. The voltage (also referred to as V _N3 ) of the node N1_3 rises to V _N2 -V _th201 . When the voltage of the node N1_3 becomes V _N2 -V _th201 , the diode-connected transistor 201 in the unit voltage step-up circuit 211_3 becomes non-conductive and the node N1_3 becomes a floating state.

Also, in each of the unit boosting circuits after the third stage, as the clock signal CK1 or the clock signal CKB1 periodically changes to a high level or a low level, the same operation as that of the unit boosting circuit is sequentially performed, and each node N1_M Is gradually raised each time the clock signal CK1 or the clock signal CKB1 is periodically changed to the high level or the low level and is boosted to the maximum V _IN1 + M (V _H -V _th201 ). Further, the voltage of the signal OUT1 is gradually increased each time the clock signal CK1 or the clock signal CKB1 is periodically changed to the high level or the low level, and the voltage V _IN1 + n (V _H -V _th201 ) . Thus, the voltage adjustment circuit shown in Fig. 3 boosts the voltage of the signal IN1 and outputs the boosted voltage signal OUT1 as an output signal.

As described above, in the example of the voltage regulating circuit of the present embodiment, by performing the voltage-boosting operation in each of the unit boosting circuits, it is possible to output a signal of a voltage higher than the voltage of the input signal as an output signal.

In addition, an example of the voltage regulating circuit of the present embodiment is a structure in which the transistor diode-connected in each unit boosting circuit is a transistor using an oxide semiconductor layer of high purity as a channel forming layer. As a result, it is possible to reduce the leak current of the transistor and improve the conversion efficiency to a desired voltage, to increase the holding period of the voltage of each node, and to increase the arrival speed until a desired voltage is obtained by the step- You can do it fast.

The present embodiment can be combined with other embodiments as appropriate.

(Embodiment 3)

In this embodiment, a voltage-lowering circuit will be described as another example of the voltage regulating circuit which is one aspect of the present invention. In the present embodiment, the description of the same parts as the voltage regulating circuit shown in the second embodiment is appropriately used.

An example of the circuit configuration of the voltage regulating circuit of this embodiment will be described with reference to Fig. 4 is a circuit diagram showing an example of the circuit configuration of the voltage regulating circuit of the present embodiment.

The voltage regulating circuit shown in Fig. 4 has unit down circuit 511_1 to unit down circuit 511_n (n is a natural number of 2 or more), and unit down circuit 511_1 to unit down circuit 511_n are connected in series Stage unit down-converting circuit that is electrically connected.

Each of the unit down-converting circuits 511_1 to 511_n has a transistor 501 and a capacitor element 502. [

As the transistor 501, a transistor having an oxide semiconductor layer having a function as a channel forming layer can be used. The hydrogen concentration of the channel forming layer is set to 5 x 10 ¹⁹ atoms / cm 3 or less, preferably 5 x 10 ¹⁸ atoms / cm 3 or less, more preferably 5 x 10 ¹⁷ atoms / cm 3 or less. This hydrogen concentration is, for example, a value obtained by secondary ion mass spectroscopy (SIMS). The carrier concentration of the transistor 501 is 1 x 10 ¹⁴ / cm 3 or less, preferably 1 x 10 ¹² / cm 3 or less.

One of the source and drain of the transistor 501 is electrically connected to the other side of the source and the drain of the transistor 501 in the unit down-converting circuit of the K-1 stage in the unit stage down circuit of the K stage (K is a natural number of 2 to n) Respectively. The connection portion between the other of the source and the drain of the transistor 501 in the unit step-down circuit of the (K-1) stage and one of the source and the drain of the transistor 501 in the unit stage step- do.

The gate of the transistor 501 is electrically connected to the other of the source and the drain of the transistor 501 with respect to each of the unit voltage-drop circuit 511_1 to the unit voltage-drop circuit 511_n. That is, the transistor 501 is diode-connected. The first electrode of the capacitor 502 is electrically connected to the other of the source and the drain of the transistor 501. In other words, the transistor 201 in the voltage regulating circuit shown in Fig. 3 has a configuration in which the gate and one of the source and the drain are electrically connected, whereas the transistor 501 in the voltage regulating circuit shown in Fig. And the other of the source and the drain are electrically connected.

Further, in the unit step-down circuit of the 2M-1 stage, the first electrode of the capacitor 502 is electrically connected to the gate of the transistor 501, the second electrode is electrically connected to the clock signal line 521, One of the source and the drain of the transistor 501 is electrically connected to the gate and the source or the drain of the transistor 501 in the 2M-1 stage and the first electrode of the capacitor 502 is connected to the source And the other of the source and drain, and the second electrode is electrically connected to the clock signal line 522. The clock signal CK2 is input to the clock signal line 521 and the clock signal CKB2 is input to the clock signal line 522. [ The clock signal CK2 and the clock signal CKB2 are in a phase-opposing relation. For example, when the clock signal CK2 is at a high level, the clock signal CKB2 is at a low level. The inverted signal of the clock signal CK2 can be used as the clock signal CKB2 and the voltage state of the clock signal CK2 can be obtained by using a NOT circuit such as an inverter, Can be generated by inverting. The values of the high level and low level voltages in the clock signal CK2 and the clock signal CKB2 can be appropriately set. The clock signal CK2 may be generated by using an oscillation circuit such as a ring oscillator and a buffer circuit. Further, not only the clock signal CK2 and the clock signal CKB2, but also clock signals of three or more phases can be used.

Further, a signal IN2 is input to one of the source and the drain of the transistor 501 in the first unit step-down circuit, that is, the unit step-down circuit 511_1.

The voltage of the other end of the source and the drain of the transistor 501 in the unit step-down circuit of the last stage, that is, the unit step-down circuit 511_n, becomes the voltage of the signal OUT2 which is the output signal of the voltage adjusting circuit. Further, the capacitor 502 in the unit voltage-down circuit 511_n is supplied with the voltage Vc2 to the second electrode. Voltage (Vc2) is may be any value, for example, it is possible to use a voltage value equal to the voltage (V _H) or a voltage (V _L). It is also preferable that the capacitance of the capacitor 502 in the unit voltage-down circuit 511_n is made larger than the capacitance of the capacitor 502 in other unit voltage-down circuits. Thereby, the voltage state of the output signal of the unit down-converting circuit 511_n, that is, the signal OUT2 which is the output signal of the voltage adjusting circuit, can be further stabilized.

As described above, an example of the voltage regulating circuit of the present embodiment has n unit step down circuits, and each unit step down circuit has a diode-connected transistor and a capacitor element. As the diode-connected transistor, a transistor having an oxide semiconductor layer in which the hydrogen concentration is reduced and the off current is reduced is used as the channel forming layer. As a result, the holding time of the voltage of each node can be lengthened, the arrival time to the target voltage can be shortened, and the voltage conversion efficiency can be improved.

Next, an example of the operation of the voltage adjusting circuit shown in Fig. 4 will be described.

The operation of the voltage regulating circuit shown in Fig. 4 can be described by dividing into a plurality of periods. The operation in each period will be described below. In an example of the operation of the voltage adjusting circuit shown in Fig. 4 described herein, a low-level signal is input as the signal IN2, a clock signal CK2 is periodically changed to a high level and a low level, It is assumed that the clock signal CKB2 is an inverted clock signal of the clock signal CK2 and the transistor 501 in each unit voltage-lowering circuit is an N-type transistor, and the threshold voltage of the transistor 501 in each unit voltage- The same value will be described.

First, in the first period, the clock signal CK2 becomes a high level and the clock signal CKB2 becomes a low level.

At this time, the diode-connected transistor 501 in the unit down-converting circuit 511_1 becomes conductive, and the voltage of the node N2_1 begins to fall. The voltage (also referred to as voltage V _N2 ) of the node N2_1 falls to V _IN2 (voltage of the signal _{IN 2} ) -V _th 501 (threshold voltage of the transistor 501). When the voltage at the node (N2_1) V _IN2 + V _th501 is a diode-connected transistor 501 of the voltage step-down circuit in the unit (511_1) and a non-conductive state, the nodes (N2_1) becomes a floating state.

Next, in the second period, the clock signal CK2 becomes low level and the clock signal CKB2 becomes high level.

At this time, the transistor 501 in the unit down-converting circuit 511_1 is kept in a non-conductive state, the node N2_1 is in a floating state, and further, the second electrode of the capacitive element 502 in the unit- since the voltage is changed to V _L that is, the voltage of the first electrode of the capacitor device 502 in conformity with the second electrode of the capacitor element 502 also begins to change. The voltage of the node N2_1 falls to V _IN2 + V _th501 -V _H. At this time, the voltage applied between the first electrode and the second electrode of the capacitive element 502 is V _IN2 + V _th501 . Thus, in the second period, the voltage of the node N2_1 becomes a value obtained by reducing the voltage of the node N2_1 in the first period.

In addition, being a voltage of the nodes (N2_1) V _IN2 + V _H -V _th501, and a diode-connected transistor 501 in a conductive state in the step-down circuit unit (511_2), start the voltage of nodes (N2_2) falling do. The voltage of the node N2_2 (also referred to as V _N2 ) falls to V _N2 + V _th501 . When the voltage of the node N2_2 becomes V _N2 + V _th501 , the diode-connected transistor 501 in the unit down-converting circuit 511_2 becomes non-conductive and the node N2_2 becomes a floating state.

Next, in the third period, the clock signal CK2 becomes the high level and the clock signal CKB2 becomes the low level.

At this time, the transistor 501 is kept in the nonconductive state in the unit voltage step-down circuit 511_2, the node N2_2 is in the floating state, and further, the second electrode of the capacitive element 502 in the unit voltage step- since the voltage is changed to V _L that is, the voltage of the first electrode of the capacitor device 502 in conformity with the second electrode of the capacitor element 502 also begins to change. The voltage of the node N2_2 falls to V _N2 + V _th501 -V _H. At this time, the voltage applied between the first electrode and the second electrode of the capacitor 502 is V _N2 + V _th501 . As described above, the voltage of the node N2_2 in the third period becomes a value in which the voltage of the node N2_2 in the second period is reduced.

Further, since the voltage of the node N2_2 becomes V _N2 + V _th501 + V _H , the diode-connected transistor 501 in the unit down circuit 511_3 becomes conductive and the voltage of the node N2_3 begins to fall do. The voltage (also referred to as V _N3 ) of the node N2_3 falls to V _N2 + V _th501 . When the voltage of the node N2_3 becomes V _N2 -V _th501 , the diode-connected transistor 501 in the unit down-converting circuit 511_3 becomes non-conductive, and the node N2_3 becomes a floating state.

The same operation as that of the unit down-converting circuit is sequentially performed as the clock signal CK2 or the clock signal CKB2 periodically changes to a high level or a low level in each of the unit step-down circuits after the third stage, and each node N2_M Is gradually lowered each time the clock signal CK2 or the clock signal CKB2 is periodically changed to the high level or the low level, and becomes minimum V _IN2 -M (V _H + V _th501 ). In addition, the voltage clock signal (CK2) or clock signal (CKB2) is gradually falling each time a periodically changed to the high level or low level, the minimum _{V IN2 -n (V H -V th501} ) of the signal (OUT2) . Thus, the voltage adjustment circuit shown in Fig. 4 outputs the signal OUT2 of the voltage in which the voltage of the signal IN2 is reduced, as the output signal.

As described above, in the example of the voltage regulating circuit of the present embodiment, the voltage lower than the voltage of the input signal can be output as the output signal by performing the voltage lowering operation in each unit voltage lowering circuit.

An example of the voltage regulating circuit of the present embodiment is a structure in which the transistor diode-connected in each unit voltage-lowering circuit is a transistor using an oxide semiconductor layer of high purity as a channel forming layer. As a result, it is possible to reduce the leakage current of the transistor, improve the conversion efficiency to a desired voltage, to extend the holding period of the voltage of each node, and to increase the arrival speed until a desired voltage is obtained by the step- You can do it fast.

The present embodiment can be combined with other embodiments as appropriate.

(Fourth Embodiment)

This embodiment shows an example of a thin film transistor applicable to a transistor constituting the voltage regulating circuit disclosed in this specification.

One embodiment of a method of manufacturing a transistor and a transistor of this embodiment will be described with reference to Figs. 5A, 5B, 6A, and 6B.

Figs. 5A and 5B show an example of a plan view and a cross-sectional structure of the transistor. The thin film transistor 410 shown in Figs. 5 (A) and 5 (B) is one of the thin film transistors of the top gate structure.

5A is a plan view of a thin film transistor 410 of a top gate structure, and FIG. 5B is a cross-sectional view taken along line C1-C2 of FIG. 5A.

The thin film transistor 410 includes an insulating layer 407, an oxide semiconductor layer 412, a source electrode layer or a drain electrode layer 415a and a source electrode layer or a drain electrode layer 415b on a substrate 400 having an insulating surface, A wiring layer 414a and a wiring layer 414b are provided in contact with the source electrode layer or the drain electrode layer 415a and the source electrode layer or the drain electrode layer 415b so as to be electrically connected to each other .

The thin film transistor 410 is described using a thin film transistor having a single gate structure, and if necessary, a thin film transistor having a multi-gate structure having a plurality of channel forming regions can also be formed.

Hereinafter, a process for fabricating the thin film transistor 410 on the substrate 400 will be described with reference to FIGS. 6 (A) to 6 (E).

There is no particular limitation on a substrate that can be used as the substrate 400 having an insulating surface, but it is required to have heat resistance enough to withstand at least subsequent heat treatment. Glass substrates such as barium borosilicate glass and aluminoborosilicate glass can be used.

When the temperature of the subsequent heat treatment is high, a glass substrate having a distortion point of 730 캜 or higher may be used as the glass substrate. Glass substrates such as aluminosilicate glass, aluminoborosilicate glass, and barium borosilicate glass are used for the glass substrate, for example. In addition, by containing a large amount of barium oxide (BaO) in comparison with boron oxide, a more practical heat-resistant glass can be obtained. Therefore, it is preferable to use a glass substrate containing more BaO than B ₂ O ₃ .

Instead of the glass substrate, a substrate made of an insulator such as a ceramic substrate, a quartz substrate, or a sapphire substrate may be used. In addition, crystallized glass or the like can be used. A plastic substrate or the like can also be suitably used. A semiconductor substrate such as silicon may also be used as the substrate.

First, an insulating layer 407 serving as a base film is formed on a substrate 400 having an insulating surface. The insulating layer 407 in contact with the oxide semiconductor layer is preferably an oxide insulating layer such as a silicon oxide layer, a silicon oxynitride layer, an aluminum oxide layer, or an aluminum oxynitride layer. Plasma CVD or sputtering may be used as the method of forming the insulating layer 407, but in order to prevent a large amount of hydrogen from being contained in the insulating layer 407, the insulating layer 407 is preferably formed by sputtering.

In this embodiment mode, a silicon oxide layer is formed as an insulating layer 407 by a sputtering method. The substrate 400 is transported to the process chamber and a high purity sputter gas containing hydrogen and moisture removed therefrom is introduced and a silicon oxide target is deposited on the substrate 400 as an insulating layer 407 do. Further, the substrate 400 may be at room temperature or heated.

For example, quartz (preferably synthetic quartz) was used as a target, and the substrate temperature was 108 占 폚, the distance between the substrate and the target (distance between TSs) was 60 mm, the pressure was 0.4 Pa, the high frequency power was 1.5 kW, (Oxygen flow rate: 25 sccm: argon flow rate: 25 sccm = 1: 1), the silicon oxide film is formed by the RF sputtering method. The film thickness is set to 100 nm. Further, instead of quartz (preferably synthetic quartz), a silicon target can be used as a target for forming a silicon oxide film. Also, oxygen or a mixed gas of oxygen and argon is used as the sputter gas.

In this case, it is preferable to form the insulating layer 407 while removing residual moisture in the treatment chamber. This is to prevent hydrogen, hydroxyl, or moisture from being contained in the insulating layer 407.

In order to remove the residual moisture in the treatment chamber, it is preferable to use an adsorption-type vacuum pump. For example, it is preferable to use a cryo pump, an ion pump, and a titanium sublimation pump. The exhaust means may be a cold trap applied to the turbo pump. In the film forming chamber exhausted by using the cryopump, for example, a compound containing a hydrogen atom such as a hydrogen source or water (H ₂ O) is exhausted, and therefore, the film forming chamber contained in the insulating layer 407 formed in this film forming chamber The concentration of impurities can be reduced.

As the sputter gas used for forming the insulating layer 407, it is preferable to use a high purity gas in which impurities such as hydrogen, water, hydroxyl groups, or hydrides are removed to about several ppm concentration and several concentration ppb.

Examples of the sputtering method include RF sputtering using a high frequency power source as a power source for sputtering, DC sputtering using a DC power source, or pulse DC sputtering applying a pulse bias. The RF sputtering method is mainly used for forming an insulating film, and the DC sputtering method is mainly used for forming a metal film.

There is also a multi-sputter device in which a plurality of targets with different materials can be installed. The multiple sputtering apparatus may be formed by depositing different material films in the same chamber or by simultaneously discharging a plurality of kinds of materials in the same chamber.

There is also a sputtering apparatus using a magnetron sputtering method having a magnet mechanism in a chamber or a sputtering apparatus using ECR sputtering using a plasma generated by using microwaves without using a glow discharge.

As a film forming method using the sputtering method, a reactive sputtering method in which a target material and a sputter gas component are chemically reacted to form a compound thin film during film formation, or a bias sputtering method in which a voltage is applied to a substrate during film formation.

The insulating layer 407 may have a laminated structure. For example, a nitride insulating layer such as a silicon nitride layer, a silicon nitride oxide layer, an aluminum nitride layer, or a nitride oxide aluminum layer, Or the like.

For example, a silicon nitride target is used to introduce a silicon nitride layer between a silicon oxide layer and a substrate by introducing a high-purity sputter gas containing hydrogen and moisture removed therefrom. In this case as well, it is preferable to form the silicon nitride layer while removing the residual moisture in the processing chamber, similarly to the silicon oxide layer.

Even when the silicon nitride layer is formed, the substrate may be heated at the time of film formation.

When the silicon nitride layer and the silicon oxide layer are stacked as the insulating layer 407, the silicon nitride layer and the silicon oxide layer can be formed using a common silicon target in the same processing chamber. First, a sputter gas containing nitrogen is introduced, a silicon nitride layer is formed by using a silicon target mounted in the processing chamber, and then, a sputter gas containing oxygen is converted into a sputter gas containing oxygen, . It is possible to continuously form the silicon nitride layer and the silicon oxide layer without exposing them to the atmosphere, so that impurities such as hydrogen and moisture can be prevented from being adsorbed on the surface of the silicon nitride layer.

Then, an oxide semiconductor film having a film thickness of 2 nm or more and 200 nm or less is formed on the insulating layer 407.

In order to prevent hydrogen, hydroxyl, and moisture from being contained in the oxide semiconductor film as much as possible, the substrate 400 on which the insulating layer 407 is formed in the preheating chamber of the sputtering apparatus is preliminarily heated as a pre- It is preferable to desorb impurities such as hydrogen, water, and the like and exhaust the same. It is preferable that the exhaust means provided in the preheating chamber is a cryopump. The preheating treatment may be omitted. This preliminary heating may be performed on the substrate 400 before the formation of the gate insulating layer 402 to be formed later, or the source electrode layer or the drain electrode layer 415a and the source electrode layer or the drain electrode layer 415b to be formed later May be performed in the same manner on the substrate 400 formed.

In addition, it is preferable that argon gas is introduced before the oxide semiconductor film is formed by the sputtering method, and plasma is generated and reverse sputtering is carried out to remove dust adhering to the surface of the insulating layer 407. An inverse sputter is a method of applying a voltage to a substrate side in an argon atmosphere using a high frequency power source without applying a voltage to a target side to form a plasma to modify the surface. Instead of the argon atmosphere, nitrogen, helium, oxygen, or the like may be used.

The oxide semiconductor film is formed by a sputtering method. Examples of the oxide semiconductor film include an In-Zn-O-based, In-Sn-Zn-O based, In-Al-Zn-O based, Sn-Ga-Zn- In-Zn-O based, In-Zn-O based, Sn-Zn-O based, Al-Zn-O based, In-O based, In-Sn-O based, Sn- Of the oxide semiconductor film. In this embodiment mode, an oxide semiconductor film is formed by a sputtering method using an In-Ga-Zn-O-based metal oxide target. Further, the oxide semiconductor film can be formed by a sputtering method under a rare gas (typically argon) atmosphere, a nitrogen atmosphere, or a rare gas (typically argon) and an oxygen atmosphere. In the case of using the sputtering method, the film may be formed using a target containing SiO ₂ in an amount of 2 wt% or more and 10 wt% or less.

As the sputter gas used for forming the oxide semiconductor film, it is preferable to use a high purity gas in which impurities such as hydrogen, water, hydroxyl groups, or hydrides are removed to about several ppm concentration and several concentration ppb.

As a target for forming an oxide semiconductor film by a sputtering method, a metal oxide target containing zinc oxide as a main component can be used. As another example of the metal oxide target, for example, a metal oxide target having a composition ratio of In ₂ O ₃ : Ga ₂ O ₃ : ZnO = 1: 1: 1 [molar ratio] can be used. The target is not limited to the above-described target. For example, a metal oxide target having a composition ratio of In ₂ O ₃ : Ga ₂ O ₃ : ZnO = 1: 1: 2 [molar ratio] may be used. The volume ratio (also referred to as filling ratio) of the portion excluding the space occupied by voids or the like from the entire volume to the entire volume of the metal oxide target to be produced is 90% or more and 100% or less, preferably 95% or more and 99.9% or less to be. The oxide semiconductor film formed by using the metal oxide target having a high filling rate becomes a dense film.

A substrate is held in a processing chamber set in a reduced pressure state, hydrogen and water-removed sputter gas are introduced while removing residual moisture in the processing chamber, and an oxide semiconductor film is formed on the substrate 400 with metal oxide as a target. In order to remove the residual moisture in the treatment chamber, it is preferable to use an adsorption-type vacuum pump. For example, it is preferable to use a cryo pump, an ion pump, and a titanium sublimation pump. The exhaust means may be a cold trap applied to the turbo pump. In the film formation chamber exhausted by using the cryopump, for example, a hydrogen atom, a compound containing a hydrogen atom such as water (H ₂ O) (more preferably a compound containing a carbon atom) The concentration of the impurity contained in the oxide semiconductor film formed in the deposition chamber can be reduced. Further, the substrate may be heated at the time of forming the oxide semiconductor film.

As an example of the deposition condition, conditions are set under the atmosphere of substrate temperature at room temperature, a distance of 60 mm between the substrate and the target, a pressure of 0.4 Pa, a direct current (DC) power of 0.5 kW, oxygen and argon (oxygen flow rate of 15 sccm: argon flow rate of 30 sccm = 1: 2) do. In addition, the use of a pulsed direct current (DC) power source is preferable because the dispersed substances (also referred to as particles and dust) generated during film formation can be alleviated and the film thickness distribution becomes uniform. The oxide semiconductor film is preferably 5 nm or more and 30 nm or less. In addition, an appropriate thickness differs depending on the oxide semiconductor material to be applied, and the thickness may be appropriately selected depending on the material.

Then, the oxide semiconductor film is processed into a island-shaped oxide semiconductor layer 412 by a first photolithography process (see Fig. 6 (A)). Further, a resist mask for forming the island-shaped oxide semiconductor layer 412 may be formed by an ink-jet method. When the resist mask is formed by the ink-jet method, the manufacturing cost can be reduced because the photomask is not used.

Here, the etching of the oxide semiconductor film may be dry etching, wet etching, or both.

As the etching gas used for the dry etching, a gas containing chlorine (a chlorine gas such as chlorine (Cl ₂ ), boron chloride (BCl ₃ ), silicon chloride (SiCl ₄ ), carbon tetrachloride (CCl ₄ ) .

The fluorine-containing gas (fluorine-based gas such as tetrafluoromethane (CH ₄ ), sulfur fluoride (SF ₆ ), nitrogen fluoride (NF ₃ ), trifluoromethane (CHF ₃ ) HBr), oxygen (O ₂ ), a gas obtained by adding a rare gas such as helium (He) or argon (Ar) to these gases, or the like can be used.

As the dry etching method, a parallel plate type RIE (Reactive Ion Etching) method or ICP (Inductively Coupled Plasma) etching method can be used. (The amount of electric power applied to the coil-shaped electrode, the amount of electric power applied to the electrode on the substrate side, the electrode temperature on the substrate side, and the like) are appropriately controlled so that etching can be performed with a desired processing shape.

As the etching solution used for the wet etching, a solution obtained by mixing phosphoric acid, acetic acid and nitric acid can be used. Alternatively, ITO07N (manufactured by Kanto Kagaku Kabushiki Kaisha) may be used.

Further, the etchant after the wet etching is removed by cleaning together with the etched material. The waste liquid of the etchant containing the removed material may be refined and the included material may be used again. The material such as indium contained in the oxide semiconductor layer is recovered from the waste solution after the etching and used again, whereby the resources can be effectively utilized and the cost can be reduced.

The etching conditions (etching solution, etching time, temperature, etc.) are appropriately adjusted according to the material so that the desired shape can be etched.

In this embodiment, the oxide semiconductor film is processed into a island-shaped oxide semiconductor layer 412 by a wet etching method using a solution in which phosphoric acid, acetic acid, and nitric acid are mixed as an etching solution.

In the present embodiment, the first heat treatment is performed on the oxide semiconductor layer 412. The temperature of the first heat treatment is set to 400 ° C or more and 750 ° C or less, preferably 400 ° C or more, and less than the distortion point of the substrate. Here, the substrate is introduced into an electric furnace, which is one of the heat treatment apparatuses, and the oxide semiconductor layer is subjected to heat treatment at 450 DEG C for 1 hour in a nitrogen atmosphere, and then water or hydrogen is prevented from being mixed into the oxide semiconductor layer, . This dehydration or dehydrogenation of the oxide semiconductor layer 412 can be performed by this first heat treatment.

The heat treatment apparatus is not limited to an electric furnace, and an apparatus for heating the article to be treated by heat conduction or heat radiation from a heating element such as a resistance heating element may be used. For example, an RTA (Rapid Thermal Anneal) device such as a GRTA (Gas Rapid Thermal Anneal) device or an LRTA (Lamp Rapid Thermal Anneal) device can be used. The LRTA apparatus is an apparatus for heating an object to be processed by radiating light (electromagnetic waves) emitted from a lamp such as a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high pressure sodium lamp, or a high pressure mercury lamp. The GRTA apparatus is a device that performs a heating process using a high-temperature gas. As the gas, a rare gas such as argon or an inert gas which does not react with the substance to be treated by a heat treatment such as nitrogen is used.

For example, when the substrate is moved into an inert gas heated to a high temperature of 650 ° C to 700 ° C as a first heat treatment, the substrate is heated for several minutes, and GRTA is taken out from the inert gas heated at a high temperature do. The use of GRTA enables high-temperature heat treatment in a short time.

In the first heat treatment, it is preferable that the rare gas such as nitrogen or helium, neon or argon does not contain water, hydrogen or the like. Nitrogen, or a rare gas such as helium, neon, or argon is introduced into the heat treatment apparatus at a purity of 6N (99.9999%) or more, preferably 7N (99.99999%) or more (i.e., impurity concentration of 1 ppm or less, Or less).

Depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer, the oxide semiconductor layer 412 may be crystallized into a microcrystalline film or a polycrystalline film. For example, there may be a microcrystalline oxide semiconductor film having a crystallization rate of 90% or more, or 80% or more. Depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer, there may be an amorphous oxide semiconductor film containing no crystal component. Further, there is also a case where an amorphous oxide semiconductor is an oxide semiconductor film in which an open crystal (a grain size of 1 nm or more and 20 nm or less (typically 2 nm or more and 4 nm or less)) is mixed.

In addition, the first heat treatment may be performed on the oxide semiconductor film before the island-shaped oxide semiconductor layer 412 is processed. In this case, the substrate is taken out from the heating device after the first heat treatment, and a photolithography process is performed.

In the heat treatment for effecting dehydration and dehydrogenation of the oxide semiconductor layer, after the oxide semiconductor layer is formed, a source electrode layer or a drain electrode layer is laminated on the oxide semiconductor layer, and then a gate insulating film is formed on the source electrode layer and the drain electrode layer Or in any of the following cases.

Then, a conductive film is formed on the insulating layer 407 and the oxide semiconductor layer 412. For example, a conductive film may be formed by a sputtering method or a vacuum vapor deposition method. As the material of the conductive film, an element selected from the group consisting of Al, Cr, Cu, Ta, Ti, Mo and W, an alloy containing the above-described elements, and an alloy film obtained by combining the above- Further, a material selected from any one or plural of manganese, magnesium, zirconium, beryllium, and yttrium may be used. The conductive film may have a single-layer structure or a laminated structure of two or more layers. For example, a three-layer structure in which a single layer structure of an aluminum film including silicon, a two-layer structure in which a titanium film is laminated on an aluminum film, a Ti film, an aluminum film laminated on the Ti film, And the like. It is also possible to use a film in which a single element or a combination of plural elements selected from titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), chromium (Cr), neodymium (Nd), and scandium , An alloy film containing a plurality of these elements, or a nitride film may be used.

A resist mask is formed on the conductive film by the second photolithography process and selectively etched to form a source electrode layer or a drain electrode layer 415a, a source electrode layer or a drain electrode layer 415b, and then the resist mask is removed 6 (B)). Further, if the end portions of the formed source and drain electrode layers are tapered, the covering property of the gate insulating layer to be laminated thereon is improved, which is preferable.

In this embodiment, a titanium film having a thickness of 150 nm is formed as a source electrode layer or a drain electrode layer 415a, a source electrode layer or a drain electrode layer 415b by a sputtering method.

Further, the respective materials and the etching conditions are appropriately adjusted so that the oxide semiconductor layer 412 is removed at the time of etching the conductive film, and the insulating layer 407 below the oxide semiconductor layer 412 is not exposed.

In this embodiment, a Ti film is used as the conductive film, an In-Ga-Zn-O-based oxide semiconductor is used for the oxide semiconductor layer 412, and ammonia water (a mixture of ammonia, water, and hydrogen peroxide solution) is used as an etchant .

Further, in the second photolithography step, only a part of the oxide semiconductor layer 412 is etched, resulting in an oxide semiconductor layer having a trench (recess). A resist mask for forming the source electrode layer or the drain electrode layer 415a, the source electrode layer or the drain electrode layer 415b may be formed by an inkjet method. When the resist mask is formed by the ink-jet method, the manufacturing cost can be reduced because the photomask is not used.

Ultraviolet light, KrF laser light or ArF laser light is used for exposure in forming the resist mask in the second photolithography step. The channel length L of the thin film transistor to be formed later is determined by the interval between the lower end of the source electrode layer and the lower end of the drain electrode layer which are adjacent to each other on the oxide semiconductor layer 412. In the case of performing exposure with a channel length (L) of less than 25 nm, exposure is performed at the time of forming a resist mask in the second photolithography process using extreme ultraviolet having a very short wavelength from several nm to several tens nm . In ultra-violet exposure, the resolution is high and the depth of focus is large. Therefore, the channel length L of the thin film transistor to be formed later can be set to 10 nm or more and 1000 nm or less, the operation speed of the circuit can be increased, and the off current value can be made extremely small, can do.

Next, a gate insulating layer 402 is formed on the insulating layer 407, the oxide semiconductor layer 412, the source electrode layer or the drain electrode layer 415a, and the source or drain electrode layer 415b (see FIG. 6C) ).

The gate insulating layer 402 can be formed by plasma CVD, sputtering or the like using a single layer or stacked layers of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a silicon nitride oxide layer, or an aluminum oxide layer. In order to prevent a large amount of hydrogen from being contained in the gate insulating layer 402, it is preferable to form the gate insulating layer 402 by sputtering. When a silicon oxide film is formed by the sputtering method, a silicon target or a quartz target is used as a target, and a mixed gas of oxygen or oxygen and argon is used as a sputter gas.

The gate insulating layer 402 may have a structure in which a silicon oxide layer and a silicon nitride layer are stacked from the source electrode layer or the drain electrode layer 415a, the source electrode layer, or the drain electrode layer 415b side. For example, a silicon oxide layer (SiOx (x > 0)) having a thickness of 5 nm or more and 300 nm or less is formed as a first insulating layer, and a second gate insulating layer is formed on the first gate insulating layer by a sputtering method A silicon nitride layer (SiNy (y> 0)) of 50 nm or more and 200 nm or less may be laminated to form a gate insulating layer having a thickness of 100 nm. In this embodiment mode, a silicon oxide layer having a thickness of 100 nm is formed by RF sputtering under a pressure of 0.4 Pa, a high frequency power of 1.5 kW, and an atmosphere of oxygen and argon (oxygen flow rate 25 sccm: argon flow rate 25 sccm = 1: 1).

Subsequently, a resist mask is formed by a third photolithography process, and a portion of the gate insulating layer 402 is selectively removed by etching to form a source electrode layer or a drain electrode layer 415a, a source electrode layer or a drain electrode layer 415b And an opening 421a and an opening 421b are formed (see Fig. 6 (D)).

Next, a conductive film is formed on the gate insulating layer 402 and openings 421a and 421b, and then a gate electrode layer 411 and wiring layers 414a and 414b are formed by a fourth photolithography process. The resist mask may be formed by an ink-jet method. When the resist mask is formed by the ink-jet method, the manufacturing cost can be reduced because the photomask is not used.

The conductive film for forming the gate electrode layer 411 and the wiring layers 414a and 414b may be formed of a metal material such as molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, or scandium, Can be formed as a single layer or by laminating.

For example, as the two-layer lamination structure of the gate electrode layer 411 and the wiring layers 414a and 414b, a two-layered laminate structure in which a molybdenum layer is laminated on an aluminum layer, or a laminate structure in which a molybdenum layer is laminated on a copper layer A two-layer structure in which a titanium nitride layer or a tantalum nitride layer is laminated on a layer structure or a copper layer, and a two-layer structure in which a titanium nitride layer and a molybdenum layer are laminated. As the three-layered laminated structure, it is preferable to form a laminate of a tungsten layer or a tungsten nitride layer, an alloy of aluminum and silicon, a layer of an alloy of aluminum and titanium, and a titanium nitride layer or a titanium layer. Further, a gate electrode layer may be formed using a conductive film having a light-transmitting property. As the conductive film having translucency, a translucent conductive oxide or the like is exemplified.

In this embodiment, a titanium film having a thickness of 150 nm is formed as a gate electrode layer 411 and wiring layers 414a and 414b by a sputtering method.

Subsequently, the second heat treatment (preferably 200 deg. C or more and 400 deg. C or less, for example, 250 deg. C or more and 350 deg. C or less) is performed in an inert gas atmosphere or an oxygen gas atmosphere. In the present embodiment, the second heat treatment is performed at 250 캜 for one hour in a nitrogen atmosphere. The second heat treatment may be performed after forming the protective insulating layer or the planarization insulating layer on the thin film transistor 410. [

The heat treatment may be carried out in air at 100 ° C or more and 200 ° C or less for 1 hour or more and 30 hours or less. This heating treatment may be carried out by heating at a constant heating temperature, and the temperature may be raised from room temperature to a heating temperature of 100 ° C or more and 200 ° C or repeatedly from a heating temperature to room temperature repeatedly. The heat treatment may be performed under reduced pressure. If the heating treatment is performed under reduced pressure, the heating time can be shortened.

The thin film transistor 410 having the oxide semiconductor layer 412 in which the concentration of hydrogen, moisture, hydride, and hydroxide is reduced can be formed (see FIG. 6 (E)).

Further, a protective insulating layer or a planarization insulating layer for planarization may be provided on the thin film transistor 410. For example, as the protective insulating layer, a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a silicon nitride oxide layer, or an aluminum oxide layer can be formed singly or in layers.

As the planarization insulating layer, an organic material having heat resistance such as polyimide, acrylic, benzocyclobutene, polyamide, or epoxy can be used. In addition to the above organic materials, a low dielectric constant material (low-k material), a siloxane-based resin, PSG (phosphorous glass), BPSG (boron glass) and the like can be used. Further, a plurality of insulating films formed of these materials may be stacked to form a planarization insulating layer.

The siloxane-based resin corresponds to a resin containing a Si-O-Si bond formed from a siloxane-based material as a starting material. As the siloxane-based resin, organic groups (for example, an alkyl group or an aryl group) and a fluoro group may be used as the substituent. Further, the organic group may have a fluoro group.

The method for forming the planarization insulating layer is not particularly limited and may be any of a sputtering method, an SOG method, a spin coating method, a dip method, a spraying method, a droplet discharging method (ink jet method, screen printing, offset printing, A curtain coater, a knife coater, or the like can be used.

The concentration of hydrogen and hydride in the oxide semiconductor film can be reduced by removing the residual moisture in the reaction atmosphere when the oxide semiconductor film is formed as described above. Thus, the oxide semiconductor film can be stabilized.

Further, a capacitor element in the voltage regulating circuit according to an embodiment of the present invention can be formed by the same process as the transistor described in this embodiment mode. By forming transistors and capacitors in the same process, it is possible to reduce the number of process steps.

By using the transistor having the above structure, a transistor having stable electrical characteristics and high reliability can be provided. Since the transistor has a low leakage current, the transistor can be used to constitute the voltage adjusting circuit, which is an aspect of the present invention, so that the arrival speed to the voltage of the desired value can be remarkably improved. Further, by configuring the voltage regulating circuit, which is an aspect of the present invention, by using this transistor, it is possible to provide a voltage regulating circuit having stable electrical characteristics and high reliability.

The present embodiment can be carried out by appropriately combining with other embodiments.

(Embodiment 5)

This embodiment shows another example of a thin film transistor applicable to a transistor constituting the voltage regulating circuit disclosed in this specification. In addition, the same parts as those of the fourth embodiment, or the parts having the same function, and the process may be the same as those of the fourth embodiment, and a repetitive description thereof will be omitted. Further, detailed description of the same portions will be omitted.

One embodiment of a method of manufacturing a transistor and a transistor according to the present embodiment will be described with reference to Figs. 7 (A), 7 (B) and 8 (A) to 8 (E).

Figs. 7A and 7B show an example of a planar structure and a cross-sectional structure of the transistor. The thin film transistor 460 shown in Figs. 7 (A) and 7 (B) is one of the thin film transistors of the top gate structure.

7A is a plan view of a thin film transistor 460 having a top gate structure, and FIG. 7B is a cross-sectional view taken along line D1-D2 in FIG. 7A.

The thin film transistor 460 includes an insulating layer 457, a source electrode layer or a drain electrode layer 465a (465a1, 465a2), an oxide semiconductor layer 462, a source electrode layer or a drain electrode layer 465b A source electrode layer or a drain electrode layer 465a (465a1, 465a2) includes a wiring layer (468a, 465b) through a wiring layer 468. The wiring layer 468 includes a wiring layer 468, a gate insulating layer 452 and gate electrode layers 461a, 461b. 464, respectively. Although not shown, a source electrode layer or a drain electrode layer 465b is also electrically connected to another wiring layer at an opening provided in the gate insulating layer 452. [

Hereinafter, a process of manufacturing the thin film transistor 460 on the substrate 450 will be described with reference to FIGS. 8 (A) to 8 (E).

First, an insulating layer 457 serving as a base film is formed on a substrate 450 having an insulating surface.

In this embodiment mode, a silicon oxide layer is formed as an insulating layer 457 by a sputtering method. The substrate 450 is transported to the processing chamber and a high purity sputter gas containing hydrogen and oxygen from which moisture has been removed is introduced and a silicon target or quartz (preferably synthetic quartz) 457, a silicon oxide layer is formed. Further, oxygen or a mixed gas of oxygen and argon is used as the sputter gas.

For example, quartz (preferably synthetic quartz) having a purity of 6N was used as a target, and the substrate temperature was 108 DEG C, the distance between the substrate and the target (distance between TSs) was 60 mm, the pressure was 0.4 Pa, , A silicon oxide film is formed by RF sputtering under an atmosphere of oxygen and argon (oxygen flow rate 25 sccm: argon flow rate 25 sccm = 1: 1). The film thickness is set to 100 nm. Further, instead of quartz (preferably synthetic quartz), a silicon target can be used as a target for forming a silicon oxide film.

In this case, it is preferable to form the insulating layer 457 while removing residual moisture in the treatment chamber. This is to prevent the insulating layer 457 from containing hydrogen, hydroxyl, or moisture. In the film-forming chamber evacuated by using the cryopump, for example, a hydrogen atom or a compound containing a hydrogen atom such as water (H ₂ O) is exhausted. Therefore, the film is sealed in the insulating layer 457 formed in this film- It is possible to reduce the concentration of the impurities.

As the sputter gas used for forming the insulating layer 457, it is preferable to use a high purity gas in which impurities such as hydrogen, water, hydroxyl groups, or hydrides are removed to about several ppm concentration and several concentration ppb.

The insulating layer 457 may have a laminated structure. For example, a nitride insulating layer such as a silicon nitride layer, a silicon nitride oxide layer, an aluminum nitride layer, or an aluminum nitride oxide layer may be formed on the substrate 450 side, Or the like.

For example, a silicon nitride target is used to introduce a silicon nitride layer between a silicon oxide layer and a substrate by introducing a high-purity sputter gas containing hydrogen and moisture removed therefrom. In this case as well, it is preferable to form the silicon nitride layer while removing the residual moisture in the processing chamber, similarly to the silicon oxide layer.

Subsequently, a conductive film is formed on the insulating layer 457, a resist mask is formed on the conductive film by the first photolithography process, and selectively etching is performed to form the source or drain electrode layers 465a1 and 465a2. The mask is removed (see Fig. 8 (A)). The source or drain electrode layers 465a1 and 465a2 are shown in a sectional view, but are continuous films. Further, if the end portions of the formed source and drain electrode layers are tapered, the covering property of the gate insulating layer to be laminated thereon is improved, which is preferable.

As the material of the source or drain electrode layers 465a1 and 465a2, an element selected from the group consisting of Al, Cr, Cu, Ta, Ti, Mo and W or an alloy containing the above- . Further, any one or a plurality of materials selected from manganese, magnesium, zirconium, beryllium and yttrium may be used. The metal conductive film may have a single-layer structure or a laminated structure of two or more layers. For example, a three-layer structure in which a single layer structure of an aluminum film including silicon, a two-layer structure in which a titanium film is laminated on an aluminum film, a Ti film, an aluminum film laminated on the Ti film, And the like. It is also possible to use a film in which a single element or a combination of plural elements selected from titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), chromium (Cr), neodymium (Nd), and scandium , An alloy film, or a nitride film may be used.

In this embodiment, a titanium film having a thickness of 150 nm is formed as a source electrode layer or a drain electrode layer 465a1 or 465a2 by a sputtering method.

Then, an oxide semiconductor film having a film thickness of 2 nm or more and 200 nm or less is formed on the insulating layer 457.

Next, the oxide semiconductor film is processed into a island-shaped oxide semiconductor layer 462 by a second photolithography process (see FIG. 8 (B)). In this embodiment mode, an oxide semiconductor film is formed by a sputtering method using an In-Ga-Zn-O-based metal oxide target.

The oxide semiconductor film holds a substrate in a processing chamber held in a reduced pressure state, introduces hydrogen and moisture-removed sputter gas while removing residual moisture in the processing chamber, and forms an oxide semiconductor film on the substrate 450 do. In order to remove the residual moisture in the treatment chamber, it is preferable to use an adsorption-type vacuum pump. For example, it is preferable to use a cryo pump, an ion pump, and a titanium sublimation pump. The exhaust means may be a cold trap applied to the turbo pump. In the film formation chamber exhausted by using the cryopump, for example, a hydrogen atom, a compound containing a hydrogen atom such as water (H ₂ O) (more preferably a compound containing a carbon atom) The concentration of the impurity contained in the oxide semiconductor film formed in the deposition chamber can be reduced. Further, the substrate may be heated at the time of forming the oxide semiconductor film.

As the sputter gas used for forming the oxide semiconductor film, it is preferable to use a high purity gas in which impurities such as hydrogen, water, hydroxyl groups, or hydrides are removed to about several ppm concentration and several concentration ppb.

As an example of the deposition condition, conditions are set under the atmosphere of substrate temperature at room temperature, a distance of 60 mm between the substrate and the target, a pressure of 0.4 Pa, a direct current (DC) power of 0.5 kW, oxygen and argon (oxygen flow rate of 15 sccm: argon flow rate of 30 sccm = 1: 2) do. In addition, the use of a pulsed direct current (DC) power source is preferable because the dispersed substances (also referred to as particles and dust) generated during film formation can be alleviated and the film thickness distribution becomes uniform. The oxide semiconductor film is preferably 5 nm or more and 30 nm or less. In addition, an appropriate thickness differs depending on the oxide semiconductor material to be applied, and the thickness may be appropriately selected depending on the material.

In this embodiment, the oxide semiconductor film is processed into a island-shaped oxide semiconductor layer 462 by a wet etching method using a solution in which phosphoric acid, acetic acid, and nitric acid are mixed as an etching solution.

In the present embodiment, the first heat treatment is performed on the oxide semiconductor layer 462. [ The temperature of the first heat treatment is set to 400 ° C or more and 750 ° C or less, preferably 400 ° C or more, and less than the distortion point of the substrate. Here, the substrate is introduced into an electric furnace, which is one of the heat treatment apparatuses, and the oxide semiconductor layer is subjected to heat treatment at 450 DEG C for 1 hour in a nitrogen atmosphere, and then water or hydrogen is prevented from being mixed into the oxide semiconductor layer, . This dehydration or dehydrogenation of the oxide semiconductor layer 462 can be performed by this first heat treatment.

The heat treatment apparatus is not limited to an electric furnace but may be provided with a device for heating the object to be treated by thermal conduction from a heating element such as a resistance heating element or by thermal radiation. For example, an RTA (Rapid Thermal Anneal) device such as a GRTA (Gas Rapid Thermal Anneal) device or an LRTA (Lamp Rapid Thermal Anneal) device can be used. For example, when the substrate is moved into an inert gas heated to a high temperature of 650 ° C to 700 ° C as a first heat treatment, the substrate is heated for several minutes, and GRTA is taken out from the inert gas heated at a high temperature do. The use of GRTA enables high-temperature heat treatment in a short time.

In the first heat treatment, it is preferable that the rare gas such as nitrogen or helium, neon or argon does not contain water, hydrogen or the like. Nitrogen, or a rare gas such as helium, neon, or argon is introduced into the heat treatment apparatus at a purity of 6N (99.9999%) or more, preferably 7N (99.99999%) or more (i.e., impurity concentration of 1 ppm or less, Or less).

Depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer, the oxide semiconductor layer 462 may be crystallized to become a microcrystalline film or a polycrystalline film.

In addition, the first heat treatment may be performed on the oxide semiconductor film before the island-shaped oxide semiconductor layer 462 is processed. In such a case, the substrate is taken out from the heating device after the first heat treatment, and the photolithography process is performed.

 In the heat treatment for effecting dehydration and dehydrogenation of the oxide semiconductor layer, after the oxide semiconductor layer is formed, a source electrode and a drain electrode are further stacked on the oxide semiconductor layer, and then a gate insulating layer is formed on the source electrode and the drain electrode May be performed in any of the following cases.

Subsequently, a conductive film is formed on the insulating layer 457 and the oxide semiconductor layer 462, a resist mask is formed on the conductive film by a third photolithography process, and etching is selectively performed to form a source electrode layer or a drain electrode layer 465b ), A wiring layer 468 is formed, and then the resist mask is removed (see Fig. 8 (C)). The source electrode layer or the drain electrode layer 465b and the wiring layer 468 may be formed using the same materials and processes as the source or drain electrode layers 465a1 and 465a2.

In this embodiment, a titanium film having a thickness of 150 nm is formed as a source electrode layer or a drain electrode layer 465b and a wiring layer 468 by a sputtering method. The present embodiment is an example in which the same titanium film is used for the source or drain electrode layers 465a1 and 465a2 and the source or drain electrode layer 465b and the source or drain electrode layers 465a2 and 465b. Can not take a selection ratio in etching. A wiring layer (not shown) is formed on the source electrode layer or the drain electrode layer 465a2 that is not covered with the oxide semiconductor layer 462 so that the source or drain electrode layers 465a1 and 465a2 are not etched when etching the source or drain electrode layer 465b 468 are provided. When a different material having a high selectivity in the etching process is used for the source or drain electrode layers 465a1 and 465a2 and the source or drain electrode layer 465b, a protective layer for protecting the source or drain electrode layer 465a2 (468) need not necessarily be provided.

Further, the respective materials and the etching conditions are appropriately adjusted so that the oxide semiconductor layer 462 is not removed at the time of etching the conductive film.

In this embodiment, a Ti film is used as the conductive film, an In-Ga-Zn-O-based oxide semiconductor is used for the oxide semiconductor layer 462, and ammonia water (ammonia, water, a mixture of hydrogen peroxide water) is used as an etchant .

Further, in the third photolithography step, only a part of the oxide semiconductor layer 462 is etched to be an oxide semiconductor layer having a trench (recess). A resist mask for forming the source electrode layer or the drain electrode layer 465b and the wiring layer 468 may be formed by an inkjet method. When the resist mask is formed by the ink-jet method, the manufacturing cost can be reduced because the photomask is not used.

Next, a gate insulating layer 452 is formed on the insulating layer 457, the oxide semiconductor layer 462, the source or drain electrode layers 465a1 and 465a2, the source or drain electrode layer 465b, and the wiring layer 468 do.

The gate insulating layer 452 can be formed by plasma CVD, sputtering or the like using a single layer or a stack of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a silicon nitride oxide layer, or an aluminum oxide layer. In order to prevent a large amount of hydrogen from being contained in the gate insulating layer 452, it is preferable to form the gate insulating layer 452 by sputtering. When a silicon oxide film is formed by the sputtering method, a silicon target or a quartz target is used as a target, and a mixed gas of oxygen or oxygen and argon is used as a sputter gas.

The gate insulating layer 452 may have a structure in which a silicon oxide layer and a silicon nitride layer are stacked from the source or drain electrode layers 465a1 and 465a2 and the source or drain electrode layer 465b. In this embodiment mode, a silicon oxide layer having a thickness of 100 nm is formed by RF sputtering under a pressure of 0.4 Pa, a high frequency power of 1.5 kW, and an atmosphere of oxygen and argon (oxygen flow rate 25 sccm: argon flow rate 25 sccm = 1: 1).

Then, a resist mask is formed by a fourth photolithography process, and etching is selectively performed to remove a part of the gate insulating layer 452 to form an opening 423 reaching the wiring layer 468 ) Reference). Although not shown, an opening reaching the source electrode layer or the drain electrode layer 465b at the time of forming the opening 423 may be formed. In this embodiment, the opening to the source electrode layer or the drain electrode layer 465b is formed after laminating further the interlayer insulating layer, and the wiring layer to be electrically connected is formed in the opening.

Next, a conductive film is formed on the gate insulating layer 452 and the opening 423, and then a gate electrode layer 461 (461a, 461b) and a wiring layer 464 are formed by a fifth photolithography process. The resist mask may be formed by an ink-jet method. When the resist mask is formed by the ink-jet method, the manufacturing cost can be reduced because the photomask is not used.

The conductive film for forming the gate electrode layers 461 (461a and 461b) and the wiring layer 464 may be formed of a metal material such as molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, or scandium, Layered or laminated using an alloy material.

In this embodiment, a titanium film having a thickness of 150 nm is formed as a gate electrode layer 461 (461a, 461b) and a wiring layer 464 by a sputtering method.

Subsequently, the second heat treatment (preferably 200 deg. C or more and 400 deg. C or less, for example, 250 deg. C or more and 350 deg. C or less) is performed in an inert gas atmosphere or an oxygen gas atmosphere. In the present embodiment, the second heat treatment is performed at 250 캜 for one hour in a nitrogen atmosphere. The second heat treatment may be performed after forming the protective insulating layer or the planarization insulating layer on the thin film transistor 460.

The heat treatment may be performed in the air at 100 ° C or more and 200 ° C or less for 1 hour or more and 30 hours or less. This heating treatment may be carried out by heating at a constant heating temperature, and the temperature may be raised from room temperature to a heating temperature of 100 ° C or more and 200 ° C or repeatedly from a heating temperature to room temperature repeatedly. The heat treatment may be performed under reduced pressure. If the heating treatment is performed under reduced pressure, the heating time can be shortened.

The thin film transistor 460 having the oxide semiconductor layer 462 in which the concentration of hydrogen, moisture, hydride, and hydroxide is reduced can be formed (see FIG. 8 (E)).

Further, a protective insulating layer or a planarization insulating layer for planarization may be provided on the thin film transistor 460. Although not shown, an opening reaching the source electrode layer or the drain electrode layer 465b is formed in the gate insulating layer 452, the protective insulating layer or the planarization insulating layer, and the source electrode layer or the drain electrode layer 465b is electrically connected to the opening Thereby forming a wiring layer to be connected.

As described above, when the oxide semiconductor film is formed, residual moisture in the reaction atmosphere is removed, so that the concentration of hydrogen and hydride in the oxide semiconductor film can be reduced. Thus, the oxide semiconductor film can be stabilized.

Further, a capacitor element in the voltage regulating circuit according to an embodiment of the present invention can be formed by the same process as the transistor described in this embodiment mode. By forming transistors and capacitors in the same process, it is possible to reduce the number of process steps.

By using the transistor having the above structure, a transistor having stable electrical characteristics and high reliability can be provided. Since the transistor has a low leakage current, the transistor can be used to constitute the voltage adjusting circuit, which is an aspect of the present invention, so that the arrival speed to the voltage of the desired value can be remarkably improved. Further, by configuring the voltage regulating circuit, which is an aspect of the present invention, by using this transistor, it is possible to provide a voltage regulating circuit having stable electrical characteristics and high reliability.

The present embodiment can be carried out by appropriately combining with other embodiments.

(Embodiment 6)

This embodiment shows another example of a thin film transistor which can be applied to the transistor constituting the voltage regulating circuit disclosed in this specification. In addition, the same parts as those of the fourth embodiment, or the parts having the same function, and the process may be the same as those of the fourth embodiment, and a repetitive description thereof will be omitted. Further, the detailed description of the same portions will be omitted. The thin film transistors 425 and 426 shown in this embodiment can be used as the thin film transistors constituting the voltage adjusting circuit of the first to third embodiments.

The thin film transistor of this embodiment will be described with reference to Figs. 9 (A) and 9 (B).

9 (A) and 9 (B) show an example of the sectional structure of the thin film transistor. The thin film transistors 425 and 426 shown in Figs. 9 (A) and 9 (B) are one of thin film transistors having a structure in which an oxide semiconductor layer is interposed between a conductive layer and a gate electrode layer.

In FIGS. 9A and 9B, a silicon substrate is used as a substrate, and thin film transistors 425 and 426 are provided on an insulating layer 422 provided on a silicon substrate 420, respectively.

9A, a conductive layer 427 is provided between the insulating layer 422 and the insulating layer 407 provided on the silicon substrate 420 so as to overlap at least the entire oxide semiconductor layer 412.

9B shows a case where the conductive layer between the insulating layer 422 and the insulating layer 407 is processed by etching like the conductive layer 424 and the conductive layer 424 including at least the channel region of the oxide semiconductor layer 412 It is an example overlapping with a part.

The conductive layers 427 and 424 may be made of a metal material capable of withstanding the heat treatment temperature performed in a subsequent process and may be formed of a material selected from the group consisting of titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo) An alloy selected from the group consisting of neodymium (Nd) and scandium (Sc), an alloy containing any of the above elements, an alloy film obtained by combining the above elements, or a nitride containing any of the above elements may be used. In addition, a single layer structure or a lamination structure may be used. For example, a single layer of a tungsten layer or a lamination structure of a tungsten nitride layer and a tungsten layer can be used.

The potentials of the conductive layers 427 and 424 may be the same or different from those of the gate electrode layer 411 of the thin film transistors 425 and 426 and may function as the second gate electrode layer. The potential of the conductive layers 427 and 424 may be a fixed potential of GND and 0V.

The electrical characteristics of the thin film transistors 425 and 426 can be controlled by the conductive layers 427 and 424.

When a semiconductor substrate is used as the substrate, for example, the substrate is thermally oxidized so that the region formed on the substrate serves as the second gate electrode layer .

Further, a capacitor element in the voltage regulating circuit according to an embodiment of the present invention can be formed by the same process as the transistor described in this embodiment mode. By forming transistors and capacitors in the same process, it is possible to reduce the number of process steps.

By using the transistor having the above structure, a transistor having stable electrical characteristics and high reliability can be provided. Since the transistor has a low leakage current, the transistor can be used to constitute the voltage adjusting circuit, which is an aspect of the present invention, so that the arrival speed to the voltage of the desired value can be remarkably improved. Further, by configuring the voltage regulating circuit, which is an aspect of the present invention, by using this transistor, it is possible to provide a voltage regulating circuit having stable electrical characteristics and high reliability.

The present embodiment can be carried out by appropriately combining with other embodiments.

(Seventh Embodiment)

This embodiment shows an example of a thin film transistor applicable to a transistor constituting the voltage regulating circuit disclosed in this specification.

One embodiment of the method of manufacturing the thin film transistor and the thin film transistor of the present embodiment will be described with reference to Figs. 10 (A) to 10 (E).

10 (A) to 10 (E) show an example of a method of manufacturing a thin film transistor. The thin film transistor 390 shown in Figs. 10 (A) to 10 (E) is one of the bottom gate structures and is also called a reverse stagger type thin film transistor.

The thin film transistor 390 is described using a thin film transistor having a single gate structure, and if necessary, a thin film transistor having a multi-gate structure having a plurality of channel forming regions can also be formed.

Hereinafter, the process of manufacturing the thin film transistor 390 on the substrate 394 will be described with reference to FIGS. 10 (A) to 10 (E).

First, a conductive film is formed on a substrate 394 having an insulating surface, and then a gate electrode layer 391 is formed by a first photolithography process. If the end of the formed gate electrode layer has a tapered shape, the covering property of the gate insulating layer to be laminated thereon is improved, which is preferable. The resist mask may be formed by an ink-jet method. When the resist mask is formed by the ink-jet method, the manufacturing cost can be reduced because the photomask is not used.

There is no particular limitation on the substrate that can be used as the substrate 394 having an insulating surface, but it is required to have at least heat resistance enough to withstand subsequent heat treatment. Glass substrates such as barium borosilicate glass and aluminoborosilicate glass can be used.

When the temperature of the subsequent heat treatment is high, a glass substrate having a distortion point of 730 캜 or higher may be used as the glass substrate. Glass substrates such as aluminosilicate glass, aluminoborosilicate glass, and barium borosilicate glass are used for the glass substrate, for example. In addition, by containing a large amount of barium oxide (BaO) in comparison with boron oxide (B ₂ O ₃ ), a more practical heat-resistant glass can be obtained. Therefore, it is preferable to use a glass substrate containing more BaO than B ₂ O ₃ .

Instead of the glass substrate, a substrate made of an insulator such as a ceramic substrate, a quartz substrate, or a sapphire substrate may be used. In addition, crystallized glass or the like can be used. A plastic substrate or the like can also be suitably used. A semiconductor substrate such as silicon may also be used as the substrate.

An insulating film to be a base film may be provided between the substrate 394 and the gate electrode layer 391. The underlying film has a function of preventing the diffusion of the impurity element from the substrate 394 and is formed by a lamination structure of one or a plurality of films selected from a silicon nitride film, a silicon oxide film, a silicon nitride oxide film, or a silicon oxynitride film .

The conductive film for forming the gate electrode layer 391 may be formed by a single layer or stacked layers using a metal material such as molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, or scandium, .

For example, as the two-layered structure of the gate electrode layer 391, there may be used a two-layer structure in which a molybdenum layer is laminated on an aluminum layer, a two-layer structure in which a molybdenum layer is laminated on a copper layer, Layer structure obtained by laminating a titanium nitride layer and a tantalum nitride layer, a two-layer structure obtained by laminating a titanium nitride layer and a molybdenum layer, or a two-layer structure obtained by laminating a tungsten nitride layer and a tungsten nitride layer. As the three-layered laminated structure, it is preferable to form a laminate of a tungsten layer or a tungsten nitride layer, a layer of an alloy of aluminum and silicon, a layer of an alloy of aluminum and titanium, and a titanium nitride layer or a titanium layer. Further, a gate electrode layer may be formed using a conductive film having a light-transmitting property. As the conductive film having translucency, a translucent conductive oxide or the like is exemplified.

Next, a gate insulating layer 397 is formed on the gate electrode layer 391.

Since the i-type or substantially i-type oxide semiconductor (high-purity oxide semiconductor) is extremely sensitive to the interface level and the interface charge by removing the impurities, the interface with the gate insulating layer is important. Therefore, the quality of the gate insulating layer (GI) in contact with the highly-purified oxide semiconductor layer is required.

For example, high-density plasma CVD using μ waves (2.45 GHz) is preferable because it can form a high-quality insulating film having high density and high withstand voltage. This is because the high-purity oxide semiconductor layer and the high-quality gate insulating layer are in close contact with each other, so that the interface level can be reduced and the interface characteristics can be improved. As the high-density plasma apparatus used herein, an apparatus capable of achieving a plasma density of 1 x 10 ¹¹ / cm 3 or more can be used.

For example, a microwave power of 3 kW to 6 kW is applied to generate a plasma to form an insulating film. Monosilane gas (SiH ₄ ), nitrous oxide (N ₂ O) and rare gas are introduced into the chamber as a material gas to generate a high-density plasma under a pressure of 10 Pa to 30 Pa to form an insulating film on a substrate having an insulating surface such as glass do. Thereafter, the supply of the monosilane gas may be stopped, and nitrous oxide (N ₂ O) and a rare gas may be introduced to the surface of the insulating film without exposing the film to the atmosphere. At least the nitrous oxide (N ₂ O) and the rare gas are introduced into the insulating film to perform the plasma treatment later than the film formation of the insulating film. The flow rate ratio of monosilane gas (SiH ₄ ) and nitrous oxide (N ₂ O) introduced into the chamber is set in the range of 1:10 to 1: 200. As the rare gas to be introduced into the chamber, helium, argon, krypton, xenon, or the like can be used, but it is preferable to use inexpensive argon.

Other deposition methods such as the sputtering method and the plasma CVD method can be applied as long as a good quality insulating film can be formed as the gate insulating layer 397. An insulating film may be used in which the film quality of the gate insulating film and the interface characteristics with the oxide semiconductor are modified by heat treatment after film formation. In any case, it is needless to say that the film quality as the gate insulating film is good, and the interface level density with the oxide semiconductor is reduced so long as a good interface can be formed.

Further, in the gate bias / thermal stress test (BT test) at 85 占 폚 and 2 占⁰⁶ V / cm for 12 hours, if the impurity is added to the oxide semiconductor, the bonding strength between the impurity and the main component of the oxide semiconductor becomes strong : Bias) and a high temperature (T: temperature), and the generated unbonded hand causes drift of the threshold voltage Vth. On the other hand, a transistor which is one embodiment of the present invention is capable of obtaining a stable thin film transistor even for the BT test by removing the impurities of the oxide semiconductor, particularly hydrogen or water, as much as possible and improving the interface property with the gate insulating layer as described above .

As the gate insulating layer 397, a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer (also referred to as SiO _x N _y , where x>y> 0), a silicon nitride oxide layer (also referred to as SiN _x O _y ) x > y > 0), or an aluminum oxide layer.

The gate insulating layer 397 may have a structure in which a silicon oxide layer and a silicon nitride layer are stacked. In this embodiment, as an example, a silicon oxynitride layer having a film thickness of 100 nm is formed by high-density plasma CVD at a pressure of 30 Pa and a microwave power of 6 kW. At this time, the flow rate ratio of the monosilane gas (SiH ₄ ) and the oxygen-oxygen nitrogen (N ₂ O) introduced into the chamber is 1:10.

In order to prevent hydrogen, hydroxyl, or moisture from being contained in the gate insulating layer 397 and the oxide semiconductor film 393 as much as possible, a substrate 394 having a gate electrode layer 391 formed in a preheating chamber of a sputtering apparatus as a pre- Or the substrate 394 formed up to the gate insulating layer 397 is preliminarily heated to desorb impurities such as hydrogen and moisture adsorbed on the substrate 394 and desorb it. The preheating temperature is not lower than 100 ° C and not higher than 400 ° C, preferably not lower than 150 ° C but not higher than 300 ° C. It is preferable that the exhaust means provided in the preheating chamber is a cryopump. The preheating treatment may be omitted. This preliminary heating may be performed in the same manner on the substrate 394 formed up to the source electrode layer or the drain electrode layer 395a and the source electrode layer or the drain electrode layer 395b before the oxide insulating layer 396 is formed.

Then, an oxide semiconductor film 393 having a film thickness of 2 nm or more and 200 nm or less is formed on the gate insulating layer 397 (see Fig. 10 (A)).

Further, it is preferable that argon gas is introduced before the oxide semiconductor film 393 is formed by the sputtering method, the plasma is generated, and reverse sputtering is performed to remove dust adhering to the surface of the gate insulating layer 397 . An inverse sputter is a method in which a voltage is applied to the substrate side in an argon atmosphere by applying an RF power to the substrate side without applying a voltage to the target side to form a plasma in the vicinity of the substrate to modify the surface. Instead of the argon atmosphere, nitrogen, helium, oxygen, or the like may be used.

The oxide semiconductor film 393 is formed by a sputtering method. The oxide semiconductor film 393 is formed of an In-Ga-Zn-O-based, In-Sn-Zn-O-based, In-Al-Zn-O-based, Zn-O-based, In-Zn-O-based, Sn-Zn-O based, Sn-Zn-O based, Al-Zn-O based, In-O based, -O-based oxide semiconductor film is used. In this embodiment mode, the oxide semiconductor film 393 is formed by a sputtering method using an In-Ga-Zn-O-based metal oxide target. The oxide semiconductor film 393 can be formed by a sputtering method under an atmosphere of rare gas (typically argon) or an atmosphere of rare gas (typically argon) and an oxygen atmosphere. In the case of using the sputtering method, the film may be formed using a target containing SiO ₂ in an amount of 2 wt% or more and 10 wt% or less.

As a target for forming the oxide semiconductor film 393 by a sputtering method, a target of a metal oxide containing zinc oxide as a main component can be used. As another example of the metal oxide target, for example, a metal oxide target having a composition ratio of In ₂ O ₃ : Ga ₂ O ₃ : ZnO = 1: 1: 1 [molar ratio] can be used. The target is not limited to the above-described target. For example, a metal oxide target having a composition ratio of In ₂ O ₃ : Ga ₂ O ₃ : ZnO = 1: 1: 2 [molar ratio] may be used. The filling rate of the metal oxide target to be produced is 90% or more and 100% or less, preferably 95% or more and 99.9% or more. The oxide semiconductor film formed by using the metal oxide target having a high filling rate becomes a dense film.

Holding the substrate in a processing chamber held in a reduced pressure state, and heating the substrate to a room temperature or a temperature lower than 400 캜. Then, hydrogen and water-removed sputter gas are introduced while removing residual moisture in the treatment chamber, and an oxide semiconductor film 393 is formed on the substrate 394 with a metal oxide as a target. In order to remove the residual moisture in the treatment chamber, it is preferable to use an adsorption-type vacuum pump. For example, it is preferable to use a cryo pump, an ion pump, and a titanium sublimation pump. The exhaust means may be a cold trap applied to the turbo pump. In the film formation chamber exhausted by using the cryopump, for example, a hydrogen atom, a compound containing a hydrogen atom such as water (H ₂ O) (more preferably a compound containing a carbon atom) The concentration of the impurity contained in the oxide semiconductor film formed in the deposition chamber can be reduced. Further, the substrate temperature at the time of forming the oxide semiconductor film 393 by performing the sputtering while removing the moisture remaining in the treatment chamber by the cryopump can be made lower than 400 占 폚 at room temperature.

As an example of film forming conditions, conditions are applied under the atmosphere of a distance of 60 mm between the substrate and the target, a pressure of 0.6 Pa, a direct current (DC) power of 0.5 kW, and oxygen (oxygen flow rate ratio of 100%). Use of a pulsed direct current (DC) power source is preferable because the pulverulent material generated at the time of film formation can be alleviated and the film thickness distribution becomes uniform. The oxide semiconductor film is preferably 5 nm or more and 30 nm or less. In addition, an appropriate thickness differs depending on the oxide semiconductor material to be applied, and the thickness may be appropriately selected depending on the material.

Then, the oxide semiconductor film is processed into a island-shaped oxide semiconductor layer 399 by a second photolithography process (see FIG. 10 (B)). A resist mask for forming the island-shaped oxide semiconductor layer 399 may be formed by an ink-jet method. When the resist mask is formed by the ink-jet method, the manufacturing cost can be reduced because the photomask is not used.

In the case of forming the contact hole in the gate insulating layer 397, the process can be performed at the time of forming the oxide semiconductor layer 399.

Here, the etching of the oxide semiconductor film 393 may be dry etching, wet etching, or both.

As the etching gas used for the dry etching, a gas containing chlorine (a chlorine gas such as chlorine (Cl ₂ ), boron chloride (BCl ₃ ), silicon chloride (SiCl ₄ ), carbon tetrachloride (CCl ₄ ) .

The fluorine-containing gas (fluorine-based gas such as tetrafluoromethane (CH ₄ ), sulfur fluoride (SF ₆ ), nitrogen fluoride (NF ₃ ), trifluoromethane (CHF ₃ ) HBr), oxygen (O ₂ ), a gas obtained by adding a rare gas such as helium (He) or argon (Ar) to these gases, or the like can be used.

As the dry etching method, a parallel plate type RIE (Reactive Ion Etching) method or ICP (Inductively Coupled Plasma) etching method can be used. (The amount of electric power applied to the coil-shaped electrode, the amount of electric power applied to the electrode on the substrate side, the electrode temperature on the substrate side, and the like) are appropriately controlled so that etching can be performed with a desired processing shape.

As the etching solution used for the wet etching, a solution obtained by mixing phosphoric acid, acetic acid and nitric acid can be used. Alternatively, ITO07N (manufactured by Kanto Kagaku Kabushiki Kaisha) may be used.

Further, the etchant after the wet etching is removed by cleaning together with the etched material. The waste liquid of the etchant containing the removed material may be refined and the included material may be used again. The material such as indium contained in the oxide semiconductor layer is recovered from the waste solution after the etching and used again, whereby the resources can be effectively utilized and the cost can be reduced.

The etching conditions (etching solution, etching time, temperature, etc.) are appropriately adjusted according to the material so that the desired shape can be etched.

In addition, it is preferable to perform reverse sputtering before the conductive film of the next step is formed to remove the resist residue or the like attached to the surfaces of the oxide semiconductor layer 399 and the gate insulating layer 397.

Subsequently, a conductive film is formed on the gate insulating layer 397 and the oxide semiconductor layer 399. For example, a conductive film may be formed by a sputtering method or a vacuum vapor deposition method. As the material of the conductive film, an element selected from the group consisting of Al, Cr, Cu, Ta, Ti, Mo and W, an alloy containing the above-described elements, and an alloy film obtained by combining the above- Further, a material selected from any one or plural of manganese, magnesium, zirconium, beryllium, and yttrium may be used. The conductive film may have a single-layer structure or a laminated structure of two or more layers. For example, a three-layer structure in which a single layer structure of an aluminum film including silicon, a two-layer structure in which a titanium film is laminated on an aluminum film, a Ti film, an aluminum film laminated on the Ti film, And the like. It is also possible to use a film in which a single element or a combination of plural elements selected from titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), chromium (Cr), neodymium (Nd), and scandium , An alloy film, or a nitride film may be used.

A resist mask is formed on the conductive film by a third photolithography process and selectively etched to form a source electrode layer or a drain electrode layer 395a, a source electrode layer or a drain electrode layer 395b, and then the resist mask is removed 10 (C)).

Ultraviolet light, KrF laser light or ArF laser light is used for exposure in forming the resist mask in the third photolithography step. The channel length L of the thin film transistor to be formed later is determined by the interval between the lower end of the source electrode layer adjacent to the oxide semiconductor layer 399 and the lower end of the drain electrode layer. In the case of performing exposure with a channel length (L) of less than 25 nm, exposure is performed at the time of forming a resist mask in the third photolithography process by using Extreme Ultraviolet having a very short wavelength from several nm to several tens nm . In ultra-violet exposure, the resolution is high and the depth of focus is large. Therefore, the channel length L of the thin film transistor to be formed later can be set to 10 nm or more and 1000 nm or less, the operation speed of the circuit can be increased, and the off current value can be made extremely small, can do.

Further, the respective materials and the etching conditions are appropriately adjusted so that the oxide semiconductor layer 399 is not removed during the etching of the conductive film.

In this embodiment, a Ti film is used as the conductive film, an In-Ga-Zn-O-based oxide semiconductor is used for the oxide semiconductor layer 399, and ammonia water (ammonia, water, a mixture of hydrogen peroxide water) is used as an etchant .

In addition, in the third photolithography step, only a part of the oxide semiconductor layer 399 is etched to be an oxide semiconductor layer having a trench (recess). A resist mask for forming a source electrode layer or a drain electrode layer 395a, a source electrode layer or a drain electrode layer 395b may be formed by an inkjet method. When the resist mask is formed by the ink-jet method, the manufacturing cost can be reduced because the photomask is not used.

Further, in order to reduce the number of photomasks and processes used in the photolithography process, an etching process may be performed using a resist mask formed by a multi-gradation mask, which is an exposure mask having a plurality of intensities of transmitted light. The resist mask formed by using the multi-gradation mask has a shape having a plurality of film thicknesses and can be further deformed by performing etching, so that it can be used for a plurality of etching processes for processing into different patterns. Therefore, a resist mask corresponding to at least two different patterns can be formed by one multi-gradation mask. Therefore, the number of exposure masks can be reduced, and the corresponding photolithography process can also be reduced, so that the process can be simplified.

The adsorbed water or the like adhering to the surface of the oxide semiconductor layer exposed by the plasma treatment using a gas such as N ₂ O, N ₂ , or Ar may be removed. In addition, a plasma treatment may be performed using a mixed gas of oxygen and argon.

The oxide insulating layer 396 is formed as an oxide insulating layer which is not exposed to the atmosphere and becomes a protective insulating film in contact with a part of the oxide semiconductor layer (see FIG. 10 (D)). The oxide semiconductor layer 399 and the oxide insulating layer 396 are in contact with each other in a region where the oxide semiconductor layer 399 does not overlap with the source electrode layer or the drain electrode layer 395a or the source or drain electrode layer 395b .

The substrate 394 formed up to the island-shaped oxide semiconductor layer 399, the source electrode layer or the drain electrode layer 395a and the source electrode layer or the drain electrode layer 395b is heated to a room temperature or a temperature lower than 100 ° C, A high-purity sputter gas containing moisture-removed oxygen is introduced, and a silicon oxide layer containing defects is formed as an oxide insulating layer 396 by using a target of silicon semiconductor.

For example, a silicon target (resistivity: 0.01? Cm) having a purity of 6N and doped with boron was used, and a distance between the substrate and the target (distance between TSs) of 89 mm, a pressure of 0.4 Pa, a direct current (DC) A silicon oxide film is formed by the pulsed DC sputtering method in an atmosphere of oxygen (oxygen flow rate ratio 100%). The film thickness is 300 nm. Further, quartz (preferably, synthetic quartz) can be used as a target for forming a silicon oxide film instead of a silicon target. Also, oxygen or a mixed gas of oxygen and argon is used as the sputter gas.

In this case, it is preferable to form the oxide insulating layer 396 while removing residual moisture in the treatment chamber. This is to prevent the oxide semiconductor layer 399 and the oxide insulating layer 396 from containing hydrogen, hydroxyl or moisture.

In order to remove the residual moisture in the treatment chamber, it is preferable to use an adsorption-type vacuum pump. For example, it is preferable to use a cryo pump, an ion pump, and a titanium sublimation pump. The exhaust means may be a cold trap applied to the turbo pump. In the film formation chamber exhausted by using the cryopump, for example, a compound containing a hydrogen atom such as a hydrogen source or water (H ₂ O) is exhausted, so that the oxide insulating layer 396 formed in the deposition chamber It is possible to reduce the concentration of the impurities.

As the oxide insulating layer 396, a silicon oxynitride layer, an aluminum oxide layer, an aluminum oxynitride layer, or the like may be used instead of the silicon oxide layer.

Further, the heat treatment may be performed at 100 占 폚 to 400 占 폚 in a state where the oxide insulating layer 396 and the oxide semiconductor layer 399 are in contact with each other. Since the oxide insulating layer 396 in this embodiment contains many defects, impurities such as hydrogen, moisture, hydroxyl, or hydride contained in the oxide semiconductor layer 399 are removed by the heat treatment to the oxide insulating layer 396, The impurity contained in the oxide semiconductor layer 399 can be further reduced.

The thin film transistor 390 having the oxide semiconductor layer 392 whose concentration of hydrogen, moisture, hydroxyl group or hydride is reduced in the above process can be formed (see FIG. 10 (E)).

As described above, when the oxide semiconductor film is formed, residual moisture in the reaction atmosphere is removed, so that the concentration of hydrogen and hydride in the oxide semiconductor film can be reduced. Thus, the oxide semiconductor film can be stabilized.

A protective insulating layer may be provided on the oxide insulating layer. In this embodiment, the protective insulating layer 398 is formed on the oxide insulating layer 396. [ As the protective insulating layer 398, a silicon nitride film, a silicon nitride oxide film, an aluminum nitride film, or an aluminum nitride oxide film is used.

The substrate 394 formed up to the oxide insulating layer 396 is heated to a temperature of 100 DEG C to 400 DEG C to introduce a high purity sputter gas containing nitrogen and moisture removed therefrom, A silicon nitride film is formed as a layer 398. [ In this case as well, it is preferable to form the protective insulating layer 398 while removing the residual moisture in the process chamber, like the oxide insulating layer 396.

When the protective insulating layer 398 is formed, the substrate 394 is heated to 100 ° C to 400 ° C at the time of forming the protective insulating layer 398 so that hydrogen or moisture contained in the oxide semiconductor layer 399 is oxidized Layer 396 as shown in FIG. In this case, the heat treatment may not be performed after the oxide insulating layer 396 is formed.

When a silicon oxide layer is laminated as the oxide insulating layer 396 and a silicon nitride layer is laminated as the protective insulating layer 398, the silicon oxide layer and the silicon nitride layer can be formed using a common silicon target in the same processing chamber. First, a sputter gas containing oxygen is introduced, a silicon oxide layer is formed by using a silicon target mounted in the processing chamber, and then a sputter gas is converted into a sputter gas containing nitrogen, and a silicon nitride target The layer is deposited. The silicon oxide layer and the silicon nitride layer can be formed continuously without being exposed to the atmosphere, so that impurities such as hydrogen and moisture can be prevented from being adsorbed on the surface of the silicon oxide layer. In this case, a silicon oxide layer is formed as the oxide insulating layer 396, a silicon nitride layer is stacked as the protective insulating layer 398, and then hydrogen or moisture contained in the oxide semiconductor layer is diffused into the oxide insulating layer 396 (At a temperature of 100 ° C to 400 ° C).

After the formation of the protective insulating layer 398, the heat treatment may be performed in the atmosphere at 100 ° C or more and 200 ° C or less for 1 hour or more and 30 hours or less. This heating treatment may be carried out by heating at a constant heating temperature, and the temperature may be raised from room temperature to a heating temperature of 100 ° C or higher and 200 ° C or from a heating temperature to room temperature repeatedly several times. The heat treatment may be performed under a reduced pressure before the oxide insulating layer 396 is formed. If the heating treatment is performed under reduced pressure, the heating time can be shortened. By this heat treatment, a thin film transistor which is normally turned off can be obtained. Therefore, the reliability of the thin film transistor can be improved.

In addition, when the oxide semiconductor layer to be a channel forming region is formed on the gate insulating layer, the residual moisture in the reaction atmosphere is removed, so that the concentration of hydrogen and the hydride in the oxide semiconductor layer can be reduced.

Since the above process is performed at a temperature of 400 DEG C or less, the present invention can be applied to a manufacturing process using a glass substrate having a thickness of 1 mm or less and a side length exceeding 1 m. In addition, all processes can be performed at a treatment temperature of 400 DEG C or lower.

11 is a longitudinal sectional view of a reverse stagger type thin film transistor using an oxide semiconductor. A source electrode 1004a and a drain electrode 1004b are provided on the gate electrode 1001 through a gate insulating film 1002 and a source electrode 1004a and a drain electrode 1004b are formed thereon. The oxide insulating layer 1005 is provided on the oxide semiconductor layer 1004 and the conductive layer 1006 is provided on the oxide semiconductor layer 1003 with the oxide insulating layer 1005 interposed therebetween.

12 is an energy band diagram (schematic diagram) taken along the line A-A 'shown in FIG. FIG. 12A shows a case where the voltage between the source and the drain is set to an equal potential (VD = 0V), and FIG. 12B shows a case where a positive potential (VD> 0) is added to the drain with respect to the source.

13 is an energy band diagram (schematic diagram) taken along the line B-B 'in Fig. 13A shows a state in which a positive potential (+ VG) is applied to the gate G1 and an ON state in which carriers (electrons) flow between the source and the drain. 13 (B) shows a state in which a negative potential (-VG) is applied to the gate G1 and in an off state (a minority carrier does not flow).

14 shows the relationship between the vacuum level and the work function? M of the metal and the electron affinity (?) Of the oxide semiconductor.

Since the metal is degenerated, the Fermi level is located in the conduction band. Meanwhile, the conventional oxide semiconductor is generally n-type, and the Fermi level (Ef) in this case is located near the conduction band away from the intrinsic Fermi level (Ei) located at the center of the band gap. Further, although it depends on the film forming method in the oxide semiconductor, it is known that a large amount of hydrogen or water is contained in the oxide semiconductor layer, and a part thereof becomes a donor to supply electrons and is one factor of n-type formation.

On the other hand, the oxide semiconductor according to the present invention is an oxide semiconductor in which hydrogen as the n-type impurity is removed from the oxide semiconductor and highly purified so as to contain impurities other than the main component of the oxide semiconductor as much as possible, will be. (Intrinsic semiconductors) of high purity due to the elimination of impurities such as hydrogen and water as much as possible, rather than i-type by adding impurities. By doing so, the Fermi level Ef can reach the same level as the intrinsic Fermi level Ei.

When the band gap Eg of the oxide semiconductor is 3.15 eV, the electron affinity x is 4.3 eV. The work function of titanium (Ti) constituting the source electrode and the drain electrode is substantially equal to the electron affinity (x) of the oxide semiconductor. In this case, a Schottky barrier is not formed with respect to electrons at the metal-oxide semiconductor interface.

That is, when the work function? M of the metal and the electron affinity (?) Of the oxide semiconductor are the same, an energy band diagram (schematic diagram) as shown in Fig.

In Figure 12 (B), a black circle (●) represents electrons. When positive potential is applied to the drain, electrons exceed the barrier h and are injected into the oxide semiconductor and flow toward the drain. In this case, the height of the barrier h changes depending on the gate voltage and the drain voltage. When the positive drain voltage is applied, the height of the barrier in Fig. 12A without voltage application, / 2, the height h of the barrier becomes smaller.

At this time, as shown in Fig. 13 (A), the electrons move at the energy-stabilized lowest part of the oxide semiconductor side at the interface between the gate insulating film and the highly-purified oxide semiconductors.

Further, when a negative potential (reverse bias) is applied to the gate electrode 1001 in Fig. 13B, since the hole which is a minority carrier is substantially zero, the current becomes nearly zero without limitation.

For example, even if the channel width W of the thin film transistor is 1 x 10 ⁴ 탆 and the channel length is 3 탆, the off current is 10 ^-13 A or less, the subthreshold swing value (S value) Is 0.1 V / dec. (Gate insulating film thickness: 100 nm).

Further, the results obtained by more accurate determination of the off current of the transistor using the high purity oxide semiconductor will be described below.

The off-state current of the transistor using the high-purity oxide semiconductor is 1 x 10 < ^-13 > A or less, which is the detection limit of the measuring device, as described above. Hereinafter, the characteristics evaluation device will be described, and a more accurate off current value (a value below the detection limit of the measuring device in the measurement) is described below.

First, a characteristic evaluation element used in the current measurement method will be described with reference to Fig.

In the characteristic evaluation device shown in Fig. 15, the measurement system 800 is electrically connected in three parallel connections. The measurement system 800 has a capacitive element 802, a transistor 804, a transistor 805, a transistor 806, and a transistor 808. As the transistor 804 and the transistor 808, for example, a transistor manufactured according to the fourth embodiment is used.

A voltage V11 is input to one of the source and the drain of the transistor 808, and a potential Vext_b1 is input to the gate thereof. The potential Vext_b1 is a potential for controlling the ON state or the OFF state of the transistor 808. [

One of the source and the drain of the transistor 804 is electrically connected to the other of the source and the drain of the transistor 808, the voltage V12 is input to the other of the source and the drain, and the potential Vext_b2 is input to the gate . The potential Vext_b2 is a potential for controlling the ON state or the OFF state of the transistor 804. [

The capacitor 802 has a first terminal and a second terminal, and the first terminal is electrically connected to one of the source and the drain of the transistor 804. The second terminal is electrically connected to the source and the drain of the transistor 804, As shown in FIG. The connecting portion of the first terminal of the capacitor element 802 and the other of the source and the drain of the transistor 808 and one of the source and the drain of the transistor 804 and the gate of the transistor 805 is connected to the node A).

A potential V11 is input to one of the source and the drain of the transistor 806, and the gate is electrically connected to one of the source and the drain thereof.

One of the source and the drain of the transistor 805 is electrically connected to the other of the source and the drain of the transistor 806, and the potential V12 is input to the other side of the source and the drain.

A connection portion between the other of the source and the drain of the transistor 806 and one of the source and the drain of the transistor 805 serves as an output terminal in the measurement system 800. The measurement system 800 has a potential (Vout).

Next, a current measurement method using the measurement system shown in Fig. 15 will be described.

First, an outline of an initial period in which a potential difference is given to measure an off current will be described. In the initial period, the value of the potential Vext_b1 is set to a value at which the transistor 808 is turned on, the transistor 808 is turned on, and a potential V11 is applied to the node A. Here, the potential V11 is, for example, a high potential. Further, the transistor 804 is turned off.

Thereafter, the potential Vext_b1 is set to a value at which the transistor 808 is turned off, and the transistor 808 is turned off. Further, after the transistor 808 is turned off, the potential V11 is lowered. Here, the transistor 804 is also turned off. The potential V12 is set to the same potential as the potential V11. Thus, the initial period is terminated. A potential difference is generated between the node A and one of the source and the drain of the transistor 804 and a potential difference is generated between the node A and the other side of the source and drain of the transistor 808. [ A small amount of charge flows through the transistor 804 and the transistor 808. [ That is, an OFF current is generated.

Next, the outline of the measurement period of the off current will be described. In the measurement period, one of the source or drain of the transistor 804 (i.e., the potential V12) and the other of the source or drain of the transistor 808 (i.e., the potential V11) are fixed at the low potential. On the other hand, during the measurement period, the potential of the node A is not fixed (floating state). As a result, a charge flows to the transistor 804, and the amount of charge held in the node A with time elapses. The potential of the node A fluctuates in accordance with the variation of the amount of charges held in the node A. That is, the potential Vout, which is the output potential of the output terminal, also fluctuates.

FIG. 16 shows the details (timing chart) of the relationship between the potentials in the initial period in which the potential difference is given and in the subsequent measurement period.

In the initial period, the potential Vext_b2 is set to the potential at which the transistor 804 is turned on (high potential). Thereby, the potential of the node A becomes V12, that is, the low potential (for example, VSS). Thereafter, the potential Vext_b2 is set to the potential (low potential) for turning off the transistor 804, and the transistor 804 is turned off. Subsequently, the potential Vext_b1 is set to the potential (high potential) at which the transistor 808 is turned on. Thereby, the potential of the node A becomes V11, that is, high potential (for example, VDD). Thereafter, Vext_b1 is set to the potential at which the transistor 808 is turned off. As a result, the node A is in a floating state and the initial period is ended.

In the subsequent measurement period, the potential V11 and the potential V12 are set to the potential at which electric charge flows into the node A or electric charge flows from the node A. [ Here, the potential V11 and the potential V12 are set to the low potential VSS. At the timing of measuring the short-circuit output potential Vout, it is necessary to operate the output circuit, so that V11 may be temporarily set to the high potential (VDD). The period for setting V11 to the high potential (VDD) is set to a short period that does not affect the measurement.

As described above, when the potential difference is given and the measurement period starts, the amount of charge held in the node A changes with the lapse of time, and the potential of the node A fluctuates accordingly. This means that the potential of the gate of the transistor 805 fluctuates, so that the potential of the output potential Vout of the output terminal is also changed over time.

A method of calculating the off current from the obtained output potential Vout will be described below.

The relationship between the potential V _A and the output potential Vout of the node A is calculated before the calculation of the off current. Thus, the potential V _A of the node A can be obtained from the output potential Vout. From the above-described relationship, the potential V _A of the node A can be expressed as a function of the output potential Vout as follows.

[Equation 1]

The charge Q _A of the node _A is expressed by the following equation using the potential V _A of the node A, the capacitance C _A connected to the node _A , and the constant const. Here, the capacitance C _A connected to the node A is the sum of the capacitances of the capacitive element 802 and capacitances different from each other.

&Quot; (2) "

Since the current I _A of the node A is a time derivative of the charge flowing into the node A (or the charge flowing out of the node A), the current I _A of the node _A is expressed by the following equation.

&Quot; (3) "

Thus, the current I _A of the node A can be obtained from the connected capacitor C _A connected to the node A and the output potential V out of the output terminal.

The leakage current (off current) flowing between the source and the drain of the transistor in the OFF state can be measured by the method described above.

In the present embodiment, a transistor 804 and a transistor 808 were fabricated using an oxide semiconductor which was made highly purified. The ratio of the channel length (L) to the channel width (W) of the transistor is L / W = 1/5. Further, capacitance values of the capacitive element 802 in the parallel measuring system 800 were set to 100 fF, 1 pF, and 3 pF, respectively.

In the measurement according to the present embodiment, VDD = 5V and VSS = 0V. In the measurement period, the potential V11 is basically set as VSS, and Vout is measured as VDD for a period of 100 msec every 10 to 300 seconds. Further,? T used for calculation of the current (I) flowing in the element was set to about 30000 sec.

FIG. 17 shows the relationship between the elapsed time (Time) and the output potential (Vout) according to the current measurement. From about 90 hours, the appearance of the potential change can be confirmed.

Fig. 18 shows the off current calculated by the current measurement. 18 shows the relationship between the source-drain voltage V and the off-current I. From FIG. 18, it was found that the off current was 40 zA / 占 퐉 under the condition that the source-drain voltage was 4V. It was also found that the off current was 10 < z > / mu m or less under the condition that the source-drain voltage was 3.1 V. Also, IzA represents 10 ^-21 A.

19 shows the off current calculated by the current measurement when the temperature of the transistor is 85 ° C. 19 shows the relationship between the source-drain voltage V and the off-current I at 85 占 폚. From FIG. 19, it was found that the off current was 100 zA / 占 퐉 under the condition that the source-drain voltage was 3.1 V.

As a result, it was confirmed that the off current is sufficiently reduced in the transistor using the oxide semiconductor of high purity.

In this way, the operation of the thin film transistor can be improved by making the impurity other than the main component of the oxide semiconductor high-purity so as not to include as much as possible.

Further, a capacitor element in the voltage regulating circuit according to an embodiment of the present invention can be formed by the same process as the transistor described in this embodiment mode. By forming transistors and capacitors in the same process, it is possible to reduce the number of process steps.

By using the transistor having the above structure, a transistor having stable electrical characteristics and high reliability can be provided. Since the transistor has a low leakage current, the transistor can be used to constitute the voltage regulating circuit, which is an aspect of the present invention, so that the arrival speed to the voltage of the desired value can be remarkably improved. Further, by configuring the voltage regulating circuit, which is an aspect of the present invention, by using this transistor, it is possible to provide a voltage regulating circuit having stable electrical characteristics and high reliability.

The present embodiment can be carried out by appropriately combining with other embodiments.

(Embodiment 8)

This embodiment shows another example of a thin film transistor applicable to a transistor constituting the voltage regulating circuit disclosed in this specification.

An embodiment of a method of manufacturing a thin film transistor and a thin film transistor according to the present embodiment will be described with reference to Figs. 20 (A) to 20 (E).

20 (A) to 20 (E) show an example of a method of manufacturing a thin film transistor. The thin film transistor 310 shown in Figs. 20 (A) to 20 (E) is one of the bottom gate structures and is also called a reverse stagger type thin film transistor.

Further, although the thin film transistor 310 is described using a thin film transistor having a single gate structure, a thin film transistor having a multi-gate structure having a plurality of channel forming regions can also be formed if necessary.

Hereinafter, the process of fabricating the thin film transistor 310 on the substrate 300 will be described with reference to FIGS. 20 (A) to 20 (E).

First, a conductive film is formed on a substrate 300 having an insulating surface, and then a gate electrode layer 311 is formed by a first photolithography process. The resist mask may be formed by an ink-jet method. When the resist mask is formed by the ink-jet method, the manufacturing cost can be reduced because the photomask is not used.

There is no particular limitation on the substrate that can be used for the substrate 300 having the insulating surface, but it is required to have at least heat resistance enough to withstand subsequent heat treatment. Glass substrates such as barium borosilicate glass and aluminoborosilicate glass can be used.

When the temperature of the subsequent heat treatment is high, a glass substrate having a distortion point of 730 캜 or higher may be used as the glass substrate. Glass substrates such as aluminosilicate glass, aluminoborosilicate glass, and barium borosilicate glass are used for the glass substrate, for example. In addition, by containing a large amount of barium oxide (BaO) in comparison with boron oxide (B ₂ O ₃ ), a more practical heat-resistant glass can be obtained. Therefore, it is preferable to use a glass substrate containing more BaO than B ₂ O ₃ .

Instead of the glass substrate, a substrate made of an insulator such as a ceramic substrate, a quartz substrate, or a sapphire substrate may be used. In addition, crystallized glass or the like can be used. A semiconductor substrate such as silicon may also be used as the substrate.

An insulating film to be a base film may be provided between the substrate 300 and the gate electrode layer 311. The underlying film has a function of preventing the diffusion of the impurity element from the substrate 300 and is formed by a lamination structure of one or a plurality of films selected from a silicon nitride film, a silicon oxide film, a silicon nitride oxide film, or a silicon oxynitride film .

The conductive film for forming the gate electrode layer 311 may be formed as a single layer or a stacked layer by using a metal material such as molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, or scandium, .

For example, as the two-layer laminated structure of the gate electrode layer 311, there are a two-layered laminate structure in which a molybdenum layer is laminated on an aluminum layer, a two-layer laminated structure in which a molybdenum layer is laminated on a copper layer, A laminated structure of a two-layered structure in which a titanium nitride layer or a tantalum nitride layer is laminated, a two-layered structure in which a titanium nitride layer and a molybdenum layer are laminated, or a laminated structure of two layers of a tungsten nitride layer and a tungsten layer. As the three-layer laminated structure, it is preferable that the laminated structure is formed by laminating a tungsten layer or a tungsten nitride layer, a layer of an alloy of aluminum and silicon, a layer of an alloy of aluminum and titanium, and a titanium nitride layer or a titanium layer.

Next, a gate insulating layer 302 is formed on the gate electrode layer 311.

Since the i-type or substantially i-type oxide semiconductor (high-purity oxide semiconductor) is extremely sensitive to the interface level and the interface charge by removing the impurities, the interface with the gate insulating layer is important. Therefore, the quality of the gate insulating layer (GI) in contact with the highly-purified oxide semiconductor layer is required.

For example, high-density plasma CVD using μ waves (2.45 GHz) is preferable because it can form a high-quality insulating film having high density and high withstand voltage. This is because the high-purity oxide semiconductor layer and the high-quality gate insulating layer are in close contact with each other, so that the interface level can be reduced and the interface characteristics can be improved. As the high-density plasma apparatus used herein, an apparatus capable of achieving a plasma density of 1 x 10 ¹¹ / cm 3 or more can be used.

For example, a microwave power of 3 kW to 6 kW is applied to generate a plasma to form an insulating film. Monosilane gas (SiH ₄ ), nitrous oxide (N ₂ O) and rare gas are introduced into the chamber as a material gas to generate a high-density plasma under a pressure of 10 Pa to 30 Pa to form an insulating film on a substrate having an insulating surface such as glass do. Thereafter, the supply of the monosilane gas may be stopped, and nitrous oxide (N ₂ O) and a rare gas may be introduced to the surface of the insulating film without exposing the film to the atmosphere. The plasma treatment performed at least on the surface of the insulating film by introducing nitrous oxide (N ₂ O) and rare gas is performed later than the film formation of the insulating film. The flow rate ratio of monosilane gas (SiH ₄ ) and nitrous oxide (N ₂ O) introduced into the chamber is set in the range of 1:10 to 1: 200. As the rare gas to be introduced into the chamber, helium, argon, krypton, xenon, or the like can be used, but it is preferable to use inexpensive argon.

Other deposition methods such as sputtering and plasma CVD can be applied as long as a good quality insulating film can be formed as the gate insulating layer 302. [ An insulating film may be used in which the film quality of the gate insulating film and the interface characteristics with the oxide semiconductor are modified by heat treatment after film formation. In any case, it is needless to say that the film quality as the gate insulating film is good, and the interface level density with the oxide semiconductor is reduced so long as a good interface can be formed.

Further, in the gate bias / thermal stress test (BT test) at 85 占 폚 and 2 占⁰⁶ V / cm for 12 hours, if the impurity is added to the oxide semiconductor, the bonding strength between the impurity and the main component of the oxide semiconductor becomes strong : Bias) and a high temperature (T: temperature), and the generated unbonded hand causes drift of the threshold voltage Vth. On the other hand, a transistor which is one embodiment of the present invention is capable of obtaining a stable thin film transistor even for the BT test by removing the impurities of the oxide semiconductor, particularly hydrogen or water, as much as possible and improving the interface property with the gate insulating layer as described above .

As the gate insulating layer 302, a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer (also referred to as SiO _x N _y , where x>y> 0), a silicon nitride oxide layer (also referred to as SiN _x O _y ) x > y > 0), or an aluminum oxide layer.

The gate insulating layer 302 may have a structure in which a silicon oxide layer and a silicon nitride layer are stacked. In this embodiment, as an example, a silicon oxynitride layer having a film thickness of 100 nm is formed by high-density plasma CVD at a pressure of 30 Pa and a microwave power of 6 kW. At this time, the flow ratio of the monosilane gas (SiH ₄ ) and the oxygen-oxygen nitrogen (N ₂ O) introduced into the chamber is 1:10.

Next, an oxide semiconductor film 330 having a thickness of 2 nm or more and 200 nm or less is formed on the gate insulating layer 302.

Further, it is preferable that argon gas is introduced before the oxide semiconductor film 330 is formed by the sputtering method, and plasma is generated to perform inverse sputtering to remove dust adhering to the surface of the gate insulating layer 302 . Instead of the argon atmosphere, nitrogen, helium, oxygen, or the like may be used.

The oxide semiconductor film 330 may be formed of In-Ga-Zn-O-based, In-Sn-Zn-O-based, In-Al-Zn-O-based, Sn- Zn-O-based, In-Zn-O-based, Sn-Zn-O based, Sn-Zn-O based, Al-Zn-O based, In-O based, -O-based oxide semiconductor film is used. In this embodiment mode, an In-Ga-Zn-O-based metal oxide target is used as the oxide semiconductor film 330 to form a film by a sputtering method. A sectional view at this stage corresponds to Fig. 20 (A). The oxide semiconductor film 330 can be formed by sputtering under an atmosphere of rare gas (typically argon) or an atmosphere of rare gas (typically argon) and an oxygen atmosphere. In the case of using the sputtering method, the film may be formed using a target containing SiO ₂ in an amount of 2 wt% or more and 10 wt% or less.

As a target for forming the oxide semiconductor film 330 by the sputtering method, a target of a metal oxide containing zinc oxide as a main component can be used. As another example of the metal oxide target, for example, a metal oxide target having a composition ratio of In ₂ O ₃ : Ga ₂ O ₃ : ZnO = 1: 1: 1 [molar ratio] can be used. The target is not limited to the above-described target. For example, a metal oxide target having a composition ratio of In ₂ O ₃ : Ga ₂ O ₃ : ZnO = 1: 1: 2 [molar ratio] may be used. The filling rate of the metal oxide target to be produced is 90% or more and 100% or less, preferably 95% or more and 99.9% or more. The oxide semiconductor film formed by using the metal oxide target having a high filling rate becomes a dense film.

As the sputter gas used for forming the oxide semiconductor film 330, it is preferable to use a high purity gas in which impurities such as hydrogen, water, hydroxyl groups, or hydrides are removed to about several ppm concentration and several concentration ppb.

The substrate is held in a treatment chamber held in a reduced pressure state, and the substrate is heated to 100 占 폚 or higher and 600 占 폚 or lower, preferably 200 占 폚 or higher and 400 占 폚 or lower. By forming the film while heating the substrate, the impurity concentration contained in the deposited oxide semiconductor film can be reduced. In addition, damage caused by sputtering is reduced. Then, hydrogen and water-removed sputter gas are introduced while removing residual moisture in the process chamber, and the oxide semiconductor film 330 is formed on the substrate 300 with the metal oxide as a target. In order to remove the residual moisture in the treatment chamber, it is preferable to use an adsorption-type vacuum pump. For example, it is preferable to use a cryo pump, an ion pump, and a titanium sublimation pump. The exhaust means may be a cold trap applied to the turbo pump. In the film formation chamber exhausted by using the cryopump, for example, a hydrogen atom, a compound containing a hydrogen atom such as water (H ₂ O) (more preferably a compound containing a carbon atom) The concentration of the impurity contained in the oxide semiconductor film formed in the deposition chamber can be reduced.

As an example of film forming conditions, conditions are applied under the atmosphere of a distance of 100 mm between the substrate and the target, a pressure of 0.6 Pa, a direct current (DC) power of 0.5 kW, and oxygen (oxygen flow rate ratio of 100%). Use of a pulsed direct current (DC) power supply is preferable because dust can be reduced and film thickness distribution becomes uniform. The oxide semiconductor film is preferably 5 nm or more and 30 nm or less. In addition, an appropriate thickness differs depending on the oxide semiconductor material to be applied, and the thickness may be appropriately selected depending on the material.

Then, the oxide semiconductor film 330 is processed into a island-shaped oxide semiconductor layer 331 by a second photolithography process. A resist mask for forming the island-shaped oxide semiconductor layer 331 may be formed by an ink-jet method. When the resist mask is formed by the ink-jet method, the manufacturing cost can be reduced because the photomask is not used.

Then, the first heat treatment is performed on the oxide semiconductor layer. Dehydration or dehydrogenation of the oxide semiconductor layer can be performed by the first heat treatment. The temperature of the first heat treatment is set to 400 ° C or more and 750 ° C or less, preferably 400 ° C or more, and less than the distortion point of the substrate. Here, the substrate is introduced into an electric furnace, which is one of the heat treatment apparatuses, and the oxide semiconductor layer is subjected to heat treatment at 450 DEG C for 1 hour in a nitrogen atmosphere, and then water or hydrogen is prevented from being mixed into the oxide semiconductor layer, (See Fig. 20 (B)).

The heat treatment apparatus is not limited to an electric furnace but may be provided with a device for heating the object to be treated by thermal conduction from a heating element such as a resistance heating element or by thermal radiation. For example, an RTA (Rapid Thermal Anneal) device such as a GRTA (Gas Rapid Thermal Anneal) device or an LRTA (Lamp Rapid Thermal Anneal) device can be used. The LRTA apparatus is an apparatus for heating an object to be processed by radiating light (electromagnetic waves) emitted from a lamp such as a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high pressure sodium lamp, or a high pressure mercury lamp. The GRTA apparatus is a device that performs a heating process using a high-temperature gas. A rare gas such as argon or an inert gas which does not react with a substance to be treated by a heat treatment such as nitrogen is used.

For example, when the substrate is moved into an inert gas heated to a high temperature of 650 ° C to 700 ° C as a first heat treatment, the substrate is heated for several minutes, and GRTA is taken out from the inert gas heated at a high temperature do. The use of GRTA enables high-temperature heat treatment in a short time.

In the first heat treatment, it is preferable that the rare gas such as nitrogen or helium, neon or argon does not contain water, hydrogen or the like. Nitrogen, or a rare gas such as helium, neon, or argon is introduced into the heat treatment apparatus at a purity of 6N (99.9999%) or more, preferably 7N (99.99999%) or more (i.e., impurity concentration of 1 ppm or less, Or less).

Depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer, the oxide semiconductor layer may be crystallized into a microcrystalline film or a polycrystalline film. For example, there may be a microcrystalline oxide semiconductor film having a crystallization rate of 90% or more, or 80% or more. Depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer, there may be an amorphous oxide semiconductor film containing no crystal component. Further, there is also a case where an amorphous oxide semiconductor is an oxide semiconductor film in which an open crystal (a grain size of 1 nm or more and 20 nm or less (typically 2 nm or more and 4 nm or less)) is mixed.

In addition, the first heat treatment may be performed on the oxide semiconductor film 330 before being processed into a island-shaped oxide semiconductor layer. In this case, the substrate is taken out from the heating device after the first heat treatment, and a photolithography process is performed.

In the heat treatment for effecting dehydration and dehydrogenation of the oxide semiconductor layer, after forming the oxide semiconductor layer, a source electrode or a drain electrode is laminated on the oxide semiconductor layer, and then a gate insulating film is formed on the source electrode and the drain electrode Or in any of the following cases.

When a contact hole is formed in the gate insulating layer 302, the process is performed before or after the oxide semiconductor layer 331 is subjected to dehydration or dehydrogenation treatment.

Note that the etching of the oxide semiconductor film is not limited to the wet etching, and dry etching may be used.

The etching conditions (etching solution, etching time, temperature, etc.) are appropriately adjusted according to the material so that the desired shape can be etched.

Subsequently, a conductive film is formed on the gate insulating layer 302 and the oxide semiconductor layer 331. For example, a conductive film may be formed by a sputtering method or a vacuum vapor deposition method. As the material of the conductive film, an element selected from the group consisting of Al, Cr, Cu, Ta, Ti, Mo and W, an alloy containing the above-described elements, and an alloy film obtained by combining the above- Further, a material selected from any one or plural of manganese, magnesium, zirconium, beryllium, and yttrium may be used. The conductive film may have a single-layer structure or a laminated structure of two or more layers. For example, a three-layer structure in which a single layer structure of an aluminum film including silicon, a two-layer structure in which a titanium film is laminated on an aluminum film, a Ti film, an aluminum film laminated on the Ti film, And the like. It is also possible to use a film in which a single element or a combination of plural elements selected from titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), chromium (Cr), neodymium (Nd), and scandium , An alloy film, or a nitride film may be used.

When the heat treatment is performed after the conductive film formation, it is preferable to impart heat resistance to the conductive film to withstand this heat treatment.

A resist mask is formed on the conductive film by the third photolithography process and selectively etched to form the source electrode layer 315a and the drain electrode layer 315b and then the resist mask is removed (see FIG. 20 (C)) .

Ultraviolet light, KrF laser light or ArF laser light is used for exposure in forming the resist mask in the third photolithography step. The channel length L of the thin film transistor to be formed later is determined by the gap width between the lower end of the source electrode layer and the lower end of the drain electrode layer which are adjacent to each other on the oxide semiconductor layer 331. [ In the case of performing exposure with a channel length (L) of less than 25 nm, exposure is performed at the time of forming a resist mask in the third photolithography process by using Extreme Ultraviolet having a very short wavelength from several nm to several tens nm . Exposure by ultraviolet light has high resolution and large depth of focus. Therefore, the channel length L of the thin film transistor to be formed later can be set to 10 nm or more and 1000 nm or less, the operation speed of the circuit can be increased, and further, the off current value is extremely small, .

Further, the respective materials and the etching conditions are appropriately adjusted so that the oxide semiconductor layer 331 is not removed at the time of etching the conductive film.

In this embodiment mode, a Ti film is used as the conductive film, an In-Ga-Zn-O-based oxide semiconductor is used for the oxide semiconductor layer 331, and ammonia water (a mixture of ammonia, water and hydrogen peroxide solution) is used as an etchant .

Further, in the third photolithography step, only a part of the oxide semiconductor layer 331 is etched to be an oxide semiconductor layer having a trench (recess). A resist mask for forming the source electrode layer 315a and the drain electrode layer 315b may be formed by an ink jet method. When the resist mask is formed by the ink-jet method, the manufacturing cost can be reduced because the photomask is not used.

Further, an oxide conductive layer may be formed between the oxide semiconductor layer and the source electrode layer and the drain electrode layer. The metal layer for forming the oxide conductive layer, the source electrode layer, and the drain electrode layer can be continuously formed. The oxide conductive layer can function as a source region and a drain region.

By providing the oxide conductive layer between the oxide semiconductor layer and the source electrode layer and the drain electrode layer as the source region and the drain region, the resistance of the source region and the drain region can be reduced and high-speed operation of the transistor can be achieved.

Further, in order to reduce the number of photomasks used in the photolithography process and the number of processes, an etching process may be performed using a resist mask formed by a multi-gradation mask, which is an exposure mask having a plurality of intensities of transmitted light. A resist mask formed using a multi-gradation mask has a shape having a plurality of film thicknesses and can be further used for a plurality of etching processes for processing into different patterns because the shape can be further modified by performing etching. Therefore, a resist mask corresponding to at least two different patterns can be formed by one multi-gradation mask. Therefore, the number of exposure masks can be reduced, and the corresponding photolithography process can also be reduced, so that the process can be simplified.

Then, a plasma process using a gas such as N ₂ O, N ₂ , or Ar is performed. And adsorbed water or the like adhering to the surface of the oxide semiconductor layer exposed by the plasma treatment is removed. In addition, a plasma treatment may be performed using a mixed gas of oxygen and argon.

After the plasma treatment, the oxide insulating layer 316 is formed as a protective insulating film that is in contact with a part of the oxide semiconductor layer without being exposed to the atmosphere.

The oxide insulating layer 316 may have a film thickness of at least 1 nm or more and may be formed by appropriately using a method of not impregnating an oxide insulating layer 316 such as a sputtering method with impurities such as water and hydrogen. When hydrogen is contained in the oxide insulating layer 316, the hydrogen penetrates into the oxide semiconductor layer, or hydrogen extracts oxygen in the oxide semiconductor layer to lower the resistance of the back channel of the oxide semiconductor layer (N-type) There is a possibility that a channel is formed. Therefore, it is important that the oxide insulating layer 316 is made of a film that does not contain hydrogen as much as possible so as not to use hydrogen for the film forming method.

In this embodiment mode, a silicon oxide film with a thickness of 200 nm is formed as the oxide insulating layer 316 by sputtering. The substrate temperature at the time of film formation may be from room temperature to 300 캜 or less, and is set at 100 캜 in the present embodiment. The film formation by the sputtering method of the silicon oxide film can be performed under an atmosphere of rare gas (typically argon), an oxygen atmosphere, or a rare gas (typically argon) and an oxygen atmosphere. Further, a silicon oxide target or a silicon target can be used as a target. For example, a silicon oxide film can be formed by sputtering under oxygen and nitrogen atmosphere using a silicon target. As the oxide insulating layer 316 formed in contact with the oxide semiconductor layer which is in a state of oxygen deficiency and has a low resistance, that is, an N-type oxide semiconductor layer, an impurity such as moisture, hydrogen ion and OH ^- A silicon oxide film, a silicon oxynitride film, an aluminum oxide film, or an aluminum oxynitride film is typically used.

In this case, it is preferable to form the oxide insulating layer 316 while removing residual moisture in the treatment chamber. This is to prevent hydrogen, hydroxyl or moisture from being contained in the oxide semiconductor layer 331 and the oxide insulating layer 316.

In order to remove the residual moisture in the treatment chamber, it is preferable to use an adsorption-type vacuum pump. For example, it is preferable to use a cryo pump, an ion pump, and a titanium sublimation pump. The exhaust means may be a cold trap applied to the turbo pump. In the film formation chamber exhausted using the cryopump, for example, a compound containing a hydrogen atom such as a hydrogen source or water (H ₂ O) is exhausted, so that the oxide insulation layer 316 formed in the deposition chamber It is possible to reduce the concentration of the impurities.

As the sputter gas used in forming the oxide insulating layer 316, it is preferable to use a high purity gas in which impurities such as hydrogen, water, hydroxyl groups, or hydrides are removed to about several ppm concentration and several concentration ppb.

Subsequently, the second heat treatment (preferably 200 deg. C or more and 400 deg. C or less, for example, 250 deg. C or more and 350 deg. C or less) is performed in an inert gas atmosphere or an oxygen gas atmosphere. For example, the second heat treatment is performed at 250 DEG C for one hour in a nitrogen atmosphere. When a second heat treatment is performed, a part of the oxide semiconductor layer (channel forming region) is heated in contact with the oxide insulating layer 316.

By performing the above steps, the oxide semiconductor film after the film formation is subjected to heat treatment for dehydration or dehydrogenation to make the oxide semiconductor layer into an oxygen-deficient state to lower the resistance, that is, N-type, and then contact the oxide semiconductor layer An oxide insulating layer is formed so that a part of the oxide semiconductor layer is selectively in an oxygen excess state. As a result, the channel forming region 313 overlapping with the gate electrode layer 311 becomes I-type. At this time, the carrier concentration is higher than at least the channel forming region 313 and the carrier concentration is higher than at least the channel forming region 313 and the high resistance source region 314a overlapping the source electrode layer 315a, And the high-resistance drain region 314b which overlaps with the source region 315a is formed in a self-aligning manner. Through the above process, the thin film transistor 310 is formed (see Fig. 20 (D)).

Further, heat treatment may be carried out in the atmosphere at 100 ° C or more and 200 ° C or less for 1 hour or more and 30 hours or less. In the present embodiment, heat treatment is performed at 150 占 폚 for 10 hours. This heating treatment may be carried out by heating to a heating temperature of 100 ° C or more and 200 ° C or less from the room temperature, or by repeating several times of cooling from the heating temperature to room temperature. The heat treatment may be performed under a reduced pressure before forming the oxide insulating film. If the heating treatment is performed under reduced pressure, the heating time can be shortened. By this heat treatment, a thin film transistor which is normally turned off can be obtained. Therefore, the reliability of the thin film transistor can be improved. In addition, when a silicon oxide layer containing a large amount of defects is used in the oxide insulating layer, the impurity contained in the oxide semiconductor layer is further reduced by this heat treatment.

Further, by forming the high-resistance drain region 314b (and the high-resistance source region 314a) in the oxide semiconductor layer superimposed on the drain electrode layer 315b (and the source electrode layer 315a), reliability of the thin film transistor is improved can do. More specifically, by forming the high resistance drain region 314b, it is possible to change the conductivity stepwise from the drain electrode layer 315b to the high resistance drain region 314b and the channel formation region 313. Therefore, when a wiring for supplying the high voltage source VDD to the drain electrode layer 315b is connected to operate, even when a high electric field is applied between the gate electrode layer 311 and the drain electrode layer 315b, the high resistance drain region 314b It is possible to provide a structure in which the internal high voltage of the transistor is improved without applying a local high electric field to the buffer.

The high-resistance source region or the high-resistance drain region in the oxide semiconductor layer is formed over the entire film thickness direction when the oxide semiconductor layer has a small thickness of 15 nm or less, but the oxide semiconductor layer has a thickness of 30 nm or more and 50 nm or less A portion of the oxide semiconductor layer, a region in contact with the source electrode layer or the drain electrode layer and the vicinity thereof and a region near the gate insulating film in the oxide semiconductor layer may be I-type.

A further protective insulating layer may be formed on the oxide insulating layer 316. For example, a silicon nitride film is formed by RF sputtering. The RF sputtering method is preferable as a film forming method of the protective insulating layer because of its good mass productivity. As the protective insulating layer, an inorganic insulating film which does not contain impurities such as moisture, hydrogen ions and OH ^-, and which prevents them from intruding from the outside is used and a silicon nitride film, an aluminum nitride film, a silicon nitride oxide film, . In this embodiment, the protective insulating layer 303 is formed as a protective insulating layer by using a silicon nitride film (see FIG. 20 (E)).

In the present embodiment, the substrate 300 formed up to the oxide insulating layer 316 is heated to a temperature of 100 ° C to 400 ° C, and a high purity sputter gas containing nitrogen and nitrogen from which hydrogen and moisture are removed is introduced, Then, a silicon nitride film is formed as the protective insulating layer 303. In this case as well, it is preferable to form the protective insulating layer 303 while removing residual moisture in the processing chamber, similarly to the oxide insulating layer 316.

Further, a planarization insulating layer for planarization may be provided on the protective insulating layer 303.

Further, a conductive layer overlapping the oxide semiconductor layer may be provided on the protective insulating layer 303 (on the planarization insulating layer in the case of providing the planarization insulating layer). The potential of the conductive layer may be the same as or different from that of the gate electrode layer 311 of the thin film transistor 310, and may function as a second gate electrode layer. The potential of the conductive layer may be a fixed potential such as GND or 0V.

The electrical characteristics of the thin film transistor 310 can be controlled by the conductive layer.

Further, a capacitor element in the voltage regulating circuit according to an embodiment of the present invention can be formed by the same process as the transistor described in this embodiment mode. By forming transistors and capacitors in the same process, the number of process steps can be reduced.

By using the transistor having the above structure, a transistor having stable electrical characteristics and high reliability can be provided. Since the transistor has a low leakage current, the transistor can be used to constitute the voltage regulating circuit, which is an aspect of the present invention, so that the arrival speed to the voltage of the desired value can be remarkably improved. Further, by configuring the voltage regulating circuit, which is an aspect of the present invention, by using this transistor, it is possible to provide a voltage regulating circuit having stable electrical characteristics and high reliability.

The present embodiment can be carried out by appropriately combining with other embodiments.

(Embodiment 9)

This embodiment shows another example of a thin film transistor applicable to a transistor constituting the voltage regulating circuit disclosed in this specification.

An embodiment of a method of manufacturing a thin film transistor and a thin film transistor according to the present embodiment will be described with reference to Figs. 21A to 21D. Fig.

21A to 21D show an example of a method of manufacturing a thin film transistor. The thin film transistor 360 shown in Figs. 21 (A) to 21 (D) is one of the bottom gate structures referred to as a channel protection type (also referred to as a channel stop type) and is also called a reverse stagger type thin film transistor.

The thin film transistor 360 is described using a thin film transistor having a single gate structure, and a thin film transistor having a multi-gate structure having a plurality of channel forming regions can also be formed if necessary.

Hereinafter, a process of manufacturing the thin film transistor 360 on the substrate 320 will be described with reference to FIGS. 21A to 21D.

First, a conductive film is formed on a substrate 320 having an insulating surface, and then a gate electrode layer 361 is formed by a first photolithography process. The resist mask may be formed by an ink-jet method. When the resist mask is formed by the ink-jet method, the manufacturing cost can be reduced because the photomask is not used.

The conductive film for forming the gate electrode layer 361 may be formed as a single layer or a stacked layer by using a metal material such as molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, or scandium, .

Next, a gate insulating layer 322 is formed on the gate electrode layer 361.

Since the i-type or substantially i-type oxide semiconductor (highly purified oxide semiconductors) is extremely sensitive to the interface level and the interface charge by removing the impurities, the interface with the gate insulating layer is important. Therefore, the quality of the gate insulating layer (GI) in contact with the highly-purified oxide semiconductor layer is required.

For example, high-density plasma CVD using μ waves (2.45 GHz) is preferable because it can form a high-quality insulating film having high density and high withstand voltage. This is because the high-purity oxide semiconductor layer and the high-quality gate insulating layer are in close contact with each other, so that the interface level can be reduced and the interface characteristics can be improved. As the high-density plasma apparatus used herein, an apparatus capable of achieving a plasma density of 1 x 10 ¹¹ / cm 3 or more can be used.

For example, a microwave power of 3 kW to 6 kW is applied to generate a plasma to form an insulating film. Monosilane gas (SiH ₄ ), nitrous oxide (N ₂ O) and rare gas are introduced into the chamber as a material gas to generate a high-density plasma under a pressure of 10 Pa to 30 Pa to form an insulating film on a substrate having an insulating surface such as glass do. Thereafter, the supply of the monosilane gas may be stopped, and nitrous oxide (N ₂ O) and a rare gas may be introduced to the surface of the insulating film without exposing the film to the atmosphere. At least the nitrous oxide (N ₂ O) and the rare gas are introduced into the insulating film to perform the plasma treatment later than the film formation of the insulating film. The flow rate ratio of monosilane gas (SiH ₄ ) and nitrous oxide (N ₂ O) introduced into the chamber is set in the range of 1:10 to 1: 200. As the rare gas to be introduced into the chamber, helium, argon, krypton, xenon, or the like can be used, but it is preferable to use inexpensive argon.

Of course, if a good quality insulating film can be formed as the gate insulating layer 322, another film forming method such as a sputtering method or a plasma CVD method can be applied. An insulating film may be used in which the film quality of the gate insulating film and the interface characteristics with the oxide semiconductor are modified by heat treatment after film formation. In any case, it is needless to say that the film quality as the gate insulating film is good, and the interface level density with the oxide semiconductor is reduced so long as a good interface can be formed.

Further, in the gate bias / thermal stress test (BT test) at 85 占 폚 and 2 占⁰⁶ V / cm for 12 hours, if the impurity is added to the oxide semiconductor, the bonding strength between the impurity and the main component of the oxide semiconductor becomes strong : Bias) and a high temperature (T: temperature), and the generated unbonded hand causes drift of the threshold voltage Vth. On the other hand, a transistor which is one embodiment of the present invention is capable of obtaining a stable thin film transistor even for the BT test by removing the impurities of the oxide semiconductor, particularly hydrogen or water, as much as possible and improving the interface property with the gate insulating layer as described above .

As the gate insulating layer 322, a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer (also referred to as SiO _x N _y , where x>y> 0), a silicon nitride oxide layer (also referred to as SiN _x O _y ) x > y > 0), or an aluminum oxide layer.

The gate insulating layer 322 may have a structure in which a silicon oxide layer and a silicon nitride layer are stacked. In this embodiment, as an example, a silicon oxynitride layer having a film thickness of 100 nm is formed by high-density plasma CVD at a pressure of 30 Pa and a microwave power of 6 kW. At this time, the flow ratio of the monosilane gas (SiH ₄ ) and the oxygen-oxygen nitrogen (N ₂ O) introduced into the chamber is 1:10.

An oxide semiconductor film having a film thickness of 2 nm or more and 200 nm or less is formed on the gate insulating layer 322 and processed into a island-shaped oxide semiconductor layer by a second photolithography process. In this embodiment mode, an oxide semiconductor film is formed by a sputtering method using an In-Ga-Zn-O-based metal oxide target.

In this case, it is preferable to form the oxide semiconductor film while removing residual moisture in the treatment chamber. This is to prevent the oxide semiconductor film from containing hydrogen, hydroxyl or moisture.

In order to remove the residual moisture in the treatment chamber, it is preferable to use an adsorption-type vacuum pump. For example, it is preferable to use a cryo pump, an ion pump, and a titanium sublimation pump. The exhaust means may be a cold trap applied to the turbo pump. In the film formation chamber exhausted using the cryopump, for example, a hydrogen source, a compound containing a hydrogen atom such as water (H ₂ O), and the like are exhausted. Therefore, in the film formation chamber exhausted by using the cryopump, The concentration of impurities can be reduced.

It is preferable to use a high purity gas in which impurities such as hydrogen, water, hydroxyl groups, or hydrides are removed to about several ppm and several ppb, respectively, as the sputter gas used for forming the oxide semiconductor film.

Next, dehydration or dehydrogenation of the oxide semiconductor layer is performed. The temperature of the first heat treatment for dehydration or dehydrogenation is set to 400 ° C or more and 750 ° C or less, preferably 400 ° C or more, and less than the distortion point of the substrate. Here, the substrate is introduced into an electric furnace, which is one of the heat treatment apparatuses, and the oxide semiconductor layer is subjected to heat treatment at 450 DEG C for 1 hour in a nitrogen atmosphere, and then water or hydrogen is prevented from being mixed into the oxide semiconductor layer, (See Fig. 21 (A)).

Then, a plasma process using a gas such as N ₂ O, N ₂ , or Ar is performed. And adsorbed water or the like adhering to the surface of the oxide semiconductor layer exposed by the plasma treatment is removed. In addition, a plasma treatment may be performed using a mixed gas of oxygen and argon.

Subsequently, an oxide insulating layer is formed on the gate insulating layer 322 and the oxide semiconductor layer 332, a resist mask is formed by a third photolithography process, and etching is selectively performed to form the oxide insulating layer 366 After formation, the resist mask is removed.

In this embodiment mode, a silicon oxide film with a thickness of 200 nm is formed as the oxide insulating layer 366 by sputtering. The substrate temperature at the time of film formation may be from room temperature to 300 캜 or less, and is set at 100 캜 in the present embodiment. The film formation by the sputtering method of the silicon oxide film can be performed under an atmosphere of rare gas (typically argon), an oxygen atmosphere, or a rare gas (typically argon) and an oxygen atmosphere. Further, a silicon oxide target or a silicon target can be used as a target. For example, a silicon oxide film can be formed by sputtering under oxygen and nitrogen atmosphere using a silicon target. The oxide insulating layer 366, which is formed in contact with the low-resistance, ie, N-type, oxide semiconductor layer due to the oxygen deficiency state, does not contain impurities such as moisture, hydrogen ions, and OH ^- An insulating film is used, and typically a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, or an aluminum oxynitride film is used.

In this case, it is preferable to form the oxide insulating layer 366 while removing residual moisture in the treatment chamber. This is to prevent hydrogen, hydroxyl, or moisture from being contained in the oxide semiconductor layer 332 and the oxide insulating layer 366.

In order to remove the residual moisture in the treatment chamber, it is preferable to use an adsorption-type vacuum pump. For example, it is preferable to use a cryo pump, an ion pump, and a titanium sublimation pump. The exhaust means may be a cold trap applied to the turbo pump. In the film formation chamber exhausted using the cryopump, for example, a compound containing a hydrogen atom such as a hydrogen source or water (H ₂ O) is exhausted, so that the oxide insulation layer 366 formed in the deposition chamber It is possible to reduce the concentration of the impurities.

As the sputter gas used for forming the oxide insulating layer 366, it is preferable to use a high purity gas in which impurities such as hydrogen, water, hydroxyl groups, or hydrides are removed to about several ppm concentration and several concentration ppb.

Subsequently, the second heat treatment (preferably 200 deg. C or more and 400 deg. C or less, for example, 250 deg. C or more and 350 deg. C or less) may be performed in an inert gas atmosphere or an oxygen gas atmosphere. For example, the second heat treatment is performed at 250 DEG C for one hour in a nitrogen atmosphere. When the second heat treatment is performed, a part of the oxide semiconductor layer (channel forming region) is heated in contact with the oxide insulating layer 366.

In this embodiment, the oxide semiconductor layer 332 in which an oxide insulating layer 366 is provided and a part of which is exposed is subjected to heat treatment under an atmosphere of nitrogen, inert gas or reduced pressure. The region of the exposed oxide semiconductor layer 332 that is not covered with the oxide insulating layer 366 can be reduced in resistance by performing heat treatment in an atmosphere of nitrogen, inert gas, or reduced pressure. For example, heat treatment is performed at 250 DEG C for 1 hour in a nitrogen atmosphere.

The exposed region of the oxide semiconductor layer 332 is reduced in resistance by the heat treatment in the nitrogen atmosphere with respect to the oxide semiconductor layer 332 provided with the oxide insulating layer 366. In the region where the resistance is different A hatched region and a white region).

Subsequently, a conductive film is formed on the gate insulating layer 322, the oxide semiconductor layer 362, and the oxide insulating layer 366, and then a resist mask is formed by a fourth photolithography process, and etching is selectively performed, The drain electrode layer 365a, and the drain electrode layer 365b are formed, and then the resist mask is removed (see Fig. 21 (C)).

As the material of the source electrode layer 365a and the drain electrode layer 365b, an alloy selected from the group consisting of Al, Cr, Cu, Ta, Ti, Mo and W, or an alloy containing the above- And the like. The conductive film may have a single-layer structure or a laminated structure of two or more layers.

As described above, the oxide semiconductor film after the film formation is subjected to heat treatment for dehydration or dehydrogenation to reduce the resistance of the oxide semiconductor layer to an oxygen-deficient state, that is, N-type, and thereafter, Layer, thereby selectively making a portion of the oxide semiconductor layer selectively in an oxygen-excess state. As a result, the channel forming region 363 overlapping with the gate electrode layer 361 becomes I-type. The carrier concentration is higher than at least the channel forming region 363 and the carrier concentration is higher than the high resistance source region 364a and the channel forming region 363 overlapping the source electrode layer 365a and the drain electrode layer 365b The high resistance drain region 364b is formed in a self-aligning manner. The thin film transistor 360 is formed by the above process.

Further, heat treatment may be carried out in the atmosphere at 100 ° C or more and 200 ° C or less for 1 hour or more and 30 hours or less. In the present embodiment, heat treatment is performed at 150 占 폚 for 10 hours. This heating treatment may be carried out by heating to a heating temperature of 100 ° C or more and 200 ° C or less from the room temperature, or by repeating several times of cooling from the heating temperature to room temperature. The heat treatment may be performed under a reduced pressure before forming the oxide insulating film. If the heating treatment is performed under reduced pressure, the heating time can be shortened. By this heat treatment, hydrogen is introduced into the oxide insulating layer from the oxide semiconductor layer, and a thin film transistor which is normally turned off can be obtained. Therefore, the reliability of the thin film transistor can be improved.

Further, by forming the high-resistance drain region 364b (and the high-resistance source region 364a) in the oxide semiconductor layer superimposed on the drain electrode layer 365b (and the source electrode layer 365a), the reliability of the thin film transistor can be improved . Specifically, by forming the high-resistance drain region 364b, it is possible to change the conductivity stepwise from the drain electrode layer 365b to the high-resistance drain region 364b and the channel formation region 363. Therefore, when the wiring for supplying the high voltage source VDD is connected to the drain electrode layer 365b and operated, even if a high electric field is applied between the gate electrode layer 361 and the drain electrode layer 365b, the high resistance drain region 364b It is possible to provide a buffer structure in which the local high field is not applied and the breakdown voltage of the transistor is improved.

A protective insulating layer 323 is formed on the source electrode layer 365a, the drain electrode layer 365b, and the oxide insulating layer 366. [ In this embodiment, the protective insulating layer 323 is formed using a silicon nitride film (see FIG. 21 (D)).

Further, an oxide insulating layer may be further formed on the source electrode layer 365a, the drain electrode layer 365b, and the oxide insulating layer 366, and the protective insulating layer 323 may be stacked on the oxide insulating layer.

By using the transistor having the above structure, a transistor having stable electrical characteristics and high reliability can be provided. Since the transistor has a low leakage current, the transistor can be used to constitute the voltage adjusting circuit, which is an aspect of the present invention, so that the arrival speed to the voltage of the desired value can be remarkably improved. Further, by configuring the voltage regulating circuit, which is an aspect of the present invention, by using this transistor, it is possible to provide a voltage regulating circuit having stable electrical characteristics and high reliability.

Further, a capacitor element in the voltage regulating circuit according to an embodiment of the present invention can be formed by the same process as the transistor described in this embodiment mode. By forming transistors and capacitors in the same process, it is possible to reduce the number of process steps.

The present embodiment can be carried out by appropriately combining with other embodiments.

(Embodiment 10)

This embodiment shows another example of a thin film transistor applicable to a transistor constituting the voltage regulating circuit disclosed in this specification.

An embodiment of a method of manufacturing the thin film transistor and the thin film transistor of the present embodiment will be described with reference to Figs. 22 (A) to 22 (D).

The thin film transistor 350 is described using a thin film transistor having a single gate structure. If necessary, a multi-gate thin film transistor having a plurality of channel forming regions can also be formed.

Hereinafter, the process of fabricating the thin film transistor 350 on the substrate 340 will be described with reference to FIGS. 22A to 22D.

First, a conductive film is formed on a substrate 340 having an insulating surface, and then a gate electrode layer 351 is formed by a first photolithography process. In this embodiment mode, a tungsten film having a thickness of 150 nm is formed as the gate electrode layer 351 by sputtering.

Next, a gate insulating layer 342 is formed on the gate electrode layer 351.

Since the i-type or substantially i-type oxide semiconductor (highly purified oxide semiconductors) is extremely sensitive to the interface level and the interface charge by removing the impurities, the interface with the gate insulating layer is important. Therefore, the quality of the gate insulating layer (GI) in contact with the highly-purified oxide semiconductor layer is required.

For example, high-density plasma CVD using μ waves (2.45 GHz) is preferable because it can form a high-quality insulating film having high density and high withstand voltage. This is because the high-purity oxide semiconductor layer and the high-quality gate insulating layer are in close contact with each other, so that the interface level can be reduced and the interface characteristics can be improved. As the high-density plasma apparatus used herein, an apparatus capable of achieving a plasma density of 1 x 10 ¹¹ / cm 3 or more can be used.

For example, a microwave power of 3 kW to 6 kW is applied to generate a plasma to form an insulating film. Monosilane gas (SiH ₄ ), nitrous oxide (N ₂ O) and rare gas are introduced into the chamber as a material gas to generate a high-density plasma under a pressure of 10 Pa to 30 Pa to form an insulating film on a substrate having an insulating surface such as glass do. Thereafter, the supply of the monosilane gas may be stopped, and nitrous oxide (N ₂ O) and a rare gas may be introduced to the surface of the insulating film without exposing the film to the atmosphere. At least the nitrous oxide (N ₂ O) and the rare gas are introduced into the insulating film to perform the plasma treatment later than the film formation of the insulating film. The flow rate ratio of monosilane gas (SiH ₄ ) and nitrous oxide (N ₂ O) introduced into the chamber is set in the range of 1:10 to 1: 200. As the rare gas to be introduced into the chamber, helium, argon, krypton, xenon, or the like can be used, but it is preferable to use inexpensive argon.

Of course, if a good quality insulating film can be formed as the gate insulating layer 342, another film forming method such as a sputtering method or a plasma CVD method can be applied. An insulating film may be used in which the film quality of the gate insulating film and the interface characteristics with the oxide semiconductor are modified by heat treatment after film formation. In any case, it is needless to say that the film quality as the gate insulating film is good, and the interface level density with the oxide semiconductor is reduced so long as a good interface can be formed.

Further, in the gate bias / thermal stress test (BT test) at 85 占 폚 and 2 占⁰⁶ V / cm for 12 hours, if the impurity is added to the oxide semiconductor, the bonding strength between the impurity and the main component of the oxide semiconductor becomes strong : Bias) and a high temperature (T: temperature), and the generated unbonded hand causes drift of the threshold voltage Vth. On the other hand, a transistor which is one embodiment of the present invention is capable of obtaining a stable thin film transistor even for the BT test by removing the impurities of the oxide semiconductor, particularly hydrogen or water, as much as possible and improving the interface property with the gate insulating layer as described above .

As the gate insulating layer 342, a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer (also referred to as SiO _x N _y , where x>y> 0), a silicon nitride oxide layer (also referred to as SiN _x O _y ) x > y > 0), or an aluminum oxide layer.

The gate insulating layer 342 may have a structure in which a silicon oxide layer and a silicon nitride layer are stacked. In this embodiment, as an example, a silicon oxynitride layer having a film thickness of 100 nm is formed by high-density plasma CVD at a pressure of 30 Pa and a microwave power of 6 kW. At this time, the flow ratio of the monosilane gas (SiH ₄ ) and the oxygen-oxygen nitrogen (N ₂ O) introduced into the chamber is 1:10.

Then, a conductive film is formed on the gate insulating layer 342, a resist mask is formed on the conductive film by the second photolithography process, and a selective etching is performed to form a source electrode layer 355a and a drain electrode layer 355b Thereafter, the resist mask is removed (see Fig. 22 (A)).

Next, an oxide semiconductor film 345 is formed (see Fig. 22 (B)). In this embodiment mode, the oxide semiconductor film 345 is formed by a sputtering method using an In-Ga-Zn-O-based metal oxide target. The oxide semiconductor film 345 is processed into a island-shaped oxide semiconductor layer by a third photolithography process.

In this case, it is preferable to form the oxide semiconductor film 345 while removing residual moisture in the treatment chamber. This is to prevent the oxide semiconductor film 345 from containing hydrogen, hydroxyl, or moisture.

In order to remove the residual moisture in the treatment chamber, it is preferable to use an adsorption-type vacuum pump. For example, it is preferable to use a cryo pump, an ion pump, and a titanium sublimation pump. The exhaust means may be a cold trap applied to the turbo pump. In the deposition chamber exhausted using the cryopump, for example, a hydrogen source or a compound containing hydrogen atoms such as water (H ₂ O) is exhausted. Therefore, the oxide semiconductor film 345 formed in this deposition chamber, It is possible to reduce the concentration of the impurities contained in the impurities.

As the sputter gas used for forming the oxide semiconductor film 345, it is preferable to use a high purity gas in which impurities such as hydrogen, water, hydroxyl groups, or hydrides are removed to about several ppm concentration and several concentration ppb.

Next, dehydration or dehydrogenation of the oxide semiconductor layer is performed. The temperature of the first heat treatment for dehydration or dehydrogenation is set to 400 ° C or more and 750 ° C or less, preferably 400 ° C or more, and less than the distortion point of the substrate. Here, the substrate is introduced into an electric furnace, which is one of the heat treatment apparatuses, and the oxide semiconductor layer is subjected to heat treatment at 450 DEG C for 1 hour in a nitrogen atmosphere, and then water or hydrogen is prevented from being mixed into the oxide semiconductor layer, (See Fig. 22 (C)).

Further, as the first heat treatment, GRTA may be performed in which the substrate is moved into an inert gas heated to a high temperature of 650 ° C to 700 ° C, heated for several minutes, and then moved out of the inert gas heated at a high temperature . The use of GRTA enables high-temperature heat treatment in a short time.

An oxide insulating layer 356 to be a protective insulating film in contact with the oxide semiconductor layer 346 is formed.

The oxide insulating layer 356 may have a thickness of at least 1 nm or more and may be formed by appropriately using a method of not impregnating the oxide insulating layer 356, such as a sputtering method, with impurities such as water and hydrogen. When hydrogen is contained in the oxide insulating layer 356, the back channel of the oxide semiconductor layer is reduced in resistance (N-type) by introducing hydrogen into the oxide semiconductor layer or extracting oxygen in the oxide semiconductor layer by hydrogen, A parasitic channel may be formed. Therefore, it is important that the oxide insulating layer 356 is made of a film that does not contain hydrogen as much as possible so as not to use hydrogen in the film forming method.

In this embodiment mode, a silicon oxide film with a thickness of 200 nm is formed as the oxide insulating layer 356 by sputtering. The substrate temperature at the time of film formation may be from room temperature to 300 deg. C or higher, and is set at 100 deg. C in the present embodiment. The film formation by the sputtering method of the silicon oxide film can be performed under an atmosphere of rare gas (typically argon), an oxygen atmosphere, or a rare gas (typically argon) and an oxygen atmosphere. Further, a silicon oxide target or a silicon target can be used as a target. For example, a silicon oxide film can be formed by sputtering under oxygen and nitrogen atmosphere using a silicon target. The oxide insulating layer 356 formed in contact with the low-resistance, that is, the N-type oxide semiconductor layer in the state of oxygen deficiency does not contain impurities such as moisture, hydrogen ions, and OH ^- An insulating film is used, and typically a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, or an aluminum oxynitride film is used.

In this case, it is preferable to form the oxide insulating layer 356 while removing residual moisture in the treatment chamber. This is to prevent the oxide semiconductor layer 346 and the oxide insulating layer 356 from containing hydrogen, hydroxyl, or moisture.

In order to remove the residual moisture in the treatment chamber, it is preferable to use an adsorption-type vacuum pump. For example, it is preferable to use a cryo pump, an ion pump, and a titanium sublimation pump. The exhaust means may be a cold trap applied to the turbo pump. In the film formation chamber exhausted using the cryopump, for example, a compound containing a hydrogen atom such as a hydrogen source or water (H ₂ O) is exhausted. Therefore, in the oxide insulation layer 356 formed in this film formation chamber The concentration of the contained impurities can be reduced.

As the sputter gas used for forming the oxide insulating layer 356, it is preferable to use a high purity gas in which impurities such as hydrogen, water, hydroxyl groups, or hydrides are removed to about several ppm concentration and several concentration ppb.

Subsequently, the second heat treatment (preferably 200 deg. C or more and 400 deg. C or less, for example, 250 deg. C or more and 350 deg. C or less) is performed in an inert gas atmosphere or an oxygen gas atmosphere. For example, the second heat treatment is performed at 250 DEG C for one hour in a nitrogen atmosphere. When the second heat treatment is performed, the oxide semiconductor layer is heated in contact with the oxide insulating layer 356.

As described above, the oxide semiconductor layer is made to be in an oxygen-deficient state by performing a heat treatment for dehydration or dehydrogenation to lower the resistance, i.e., N-type, and then the oxide insulating layer is formed so as to contact the oxide semiconductor layer, Oxygen excess state. As a result, a high-resistance I-type oxide semiconductor layer 352 is formed. The thin film transistor 350 is formed by the above process.

Further, heat treatment may be carried out in the atmosphere at 100 ° C or more and 200 ° C or less for 1 hour or more and 30 hours or less. In the present embodiment, heat treatment is performed at 150 占 폚 for 10 hours. This heating treatment may be carried out by heating to a heating temperature of 100 ° C or more and 200 ° C or less from the room temperature, or by repeating several times of cooling from the heating temperature to room temperature. If the heating treatment is performed under reduced pressure, the heating time can be shortened. By this heat treatment, hydrogen is introduced into the oxide insulating layer from the oxide semiconductor layer, and a thin film transistor which is normally turned off can be obtained. Therefore, the reliability of the thin film transistor can be improved.

A further protective insulating layer may be formed on the oxide insulating layer 356. For example, a silicon nitride film is formed by RF sputtering. In this embodiment, the protective insulating layer 343 is formed as a protective insulating layer by using a silicon nitride film (see FIG. 22 (D)).

A planarization insulating layer for planarization may be provided on the protective insulating layer 343.

By using the transistor having the above structure, a transistor having stable electrical characteristics and high reliability can be provided. Since the transistor has a low leakage current, the transistor can be used to constitute the voltage adjusting circuit, which is an aspect of the present invention, so that the arrival speed to the voltage of the desired value can be remarkably improved. Further, by configuring the voltage regulating circuit, which is an aspect of the present invention, by using this transistor, it is possible to provide a voltage regulating circuit having stable electrical characteristics and high reliability.

Further, a capacitor element in the voltage regulating circuit according to an embodiment of the present invention can be formed by the same process as the transistor described in this embodiment mode. By forming transistors and capacitors in the same process, it is possible to reduce the number of process steps.

The present embodiment can be implemented in appropriate combination with other embodiments.

(Embodiment 11)

This embodiment shows another example of a thin film transistor applicable to a transistor constituting the voltage regulating circuit disclosed in this specification.

In this embodiment, an example in which a part of the manufacturing process of the thin film transistor is different from the eighth embodiment is shown in Fig. 20 (A) to 20 (E), the same reference numerals are used for the same portions, and detailed descriptions of the same portions in FIGS. 20 (A) to 20 The description is omitted.

First, a gate electrode layer 381 is formed on the substrate 370, and a first gate insulating layer 372a and a second gate insulating layer 372b are stacked. In this embodiment mode, the gate insulating layer has a two-layer structure, the nitride insulating layer is used for the first gate insulating layer 372a, and the oxide insulating layer is used for the second gate insulating layer 372b.

As the oxide insulating layer, a silicon oxide layer, a silicon oxynitride layer, an aluminum oxide layer, an aluminum oxynitride layer, or the like can be used. As the nitride insulating layer, a silicon nitride layer, a silicon nitride oxide layer, an aluminum nitride layer, or an aluminum nitride oxide layer can be used.

In this embodiment, a structure in which a silicon nitride layer and a silicon oxide layer are stacked is formed from the gate electrode layer 381 side. A silicon nitride layer (SiN _y (y> 0)) having a thickness of 50 nm or more and 200 nm or less (50 nm in this embodiment) is formed as a first gate insulating layer 372a by a sputtering method and a first gate insulating layer 372a A silicon oxide layer (SiO _x (x> 0)) having a thickness of 5 nm or more and 300 nm or less (100 nm in this embodiment) is laminated as a second gate insulating layer 372b to form a gate insulating layer having a thickness of 150 nm .

Next, an oxide semiconductor film is formed, and the oxide semiconductor film is processed into a island-shaped oxide semiconductor layer by a photolithography process. In this embodiment mode, an oxide semiconductor film is formed by a sputtering method using an In-Ga-Zn-O-based metal oxide target.

In this case, it is preferable to form the oxide semiconductor film while removing residual moisture in the treatment chamber. This is to prevent the oxide semiconductor film from containing hydrogen, hydroxyl or moisture.

In order to remove the residual moisture in the treatment chamber, it is preferable to use an adsorption-type vacuum pump. For example, it is preferable to use a cryo pump, an ion pump, and a titanium sublimation pump. The exhaust means may be a cold trap applied to the turbo pump. In the film formation chamber exhausted using the cryopump, for example, a compound containing a hydrogen atom such as a hydrogen source or water (H ₂ O) is exhausted, so that impurities contained in the oxide semiconductor film formed in this film formation chamber The concentration can be reduced.

As the sputter gas used for forming the oxide semiconductor film, it is preferable to use a high purity gas in which impurities such as hydrogen, water, hydroxyl groups, or hydrides are removed to about several ppm concentration and several concentration ppb.

Then, dehydration or dehydrogenation of the oxide semiconductor layer is performed. The temperature of the first heat treatment for dehydration or dehydrogenation is set to 400 ° C or higher and 750 ° C or lower, preferably 425 ° C or higher and 750 ° C or lower. If the temperature is 425 DEG C or higher, the heat treatment time may be 1 hour or less. If the temperature is lower than 425 DEG C, the heat treatment time is longer than 1 hour. Here, the substrate is introduced into an electric furnace, which is one of the heat treatment apparatuses, and the oxide semiconductor layer is subjected to heat treatment in a nitriding atmosphere, and then water or hydrogen is prevented from being mixed into the oxide semiconductor layer. Subsequently, oxygen gas of high purity, N ₂ O gas of high purity or super-drying air (dew point of -40 ° C or lower, preferably -60 ° C or lower) is introduced into the same furnace to perform cooling. It is preferable that oxygen gas or N ₂ O gas does not contain water, hydrogen or the like. Or the purity of the oxygen gas or the N ₂ O gas to be introduced into the heat treatment apparatus is set to 6N (99.9999%) or more, preferably 7N (99.99999%) or more (that is, the impurity concentration in the oxygen gas or N ₂ O gas is 1ppm or less Or less) is preferably 0.1 ppm or less).

The heat treatment apparatus is not limited to an electric furnace. For example, an RTA (Rapid Thermal Anneal) apparatus such as a GRTA (Gas Rapid Thermal Anneal) apparatus or an LRTA (Lamp Rapid Thermal Anneal) apparatus can be used. The LRTA apparatus is an apparatus for heating an object to be processed by radiating light (electromagnetic waves) emitted from a lamp such as a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high pressure sodium lamp, or a high pressure mercury lamp. In addition to the LRTA apparatus and the lamp, an apparatus for heating the object to be processed by thermal conduction or heat radiation from a heating element such as a resistance heating element may be used. GRTA is a method of performing heat treatment using a gas at a high temperature. As the gas, a rare gas such as argon or an inert gas which does not react with the substance to be treated by a heat treatment such as nitrogen is used. The heat treatment may be performed at 600 ° C to 750 ° C for several minutes by the RTA method.

After the first heat treatment for dehydration or dehydrogenation, heat treatment may be performed at a temperature of 200 ° C to 400 ° C, preferably 200 ° C to 300 ° C, in an atmosphere of oxygen gas or N ₂ O gas.

Further, the first heat treatment of the oxide semiconductor layer may be performed on the oxide semiconductor film before being processed into the island-shaped oxide semiconductor layer. In such a case, the substrate is taken out from the heating device after the first heat treatment and the photolithography process is performed.

Through the above steps, the entire oxide semiconductor film is made to be in an oxygen-excess state to have a high resistance, i. Thus, an oxide semiconductor layer 382 which is entirely I-shaped is obtained.

Next, a conductive film is formed on the oxide semiconductor layer 382, a resist mask is formed by a photolithography process, and a selective etching is performed to form a source electrode layer 385a and a drain electrode layer 385b, Layer 386 is formed.

In this case, it is preferable to form the oxide insulating layer 386 while removing residual moisture in the treatment chamber. This is to prevent the oxide semiconductor layer 382 and the oxide insulating layer 386 from containing hydrogen, hydroxyl, or moisture.

In order to remove the residual moisture in the treatment chamber, it is preferable to use an adsorption-type vacuum pump. For example, it is preferable to use a cryo pump, an ion pump, and a titanium sublimation pump. The exhaust means may be a cold trap applied to the turbo pump. In the film-forming chamber evacuated by using the cryopump, for example, a hydrogen atom, a compound containing hydrogen atoms such as water (H ₂ O), and the like are exhausted. Therefore, the oxide insulating layer 386 formed in this film- It is possible to reduce the concentration of the impurities contained in the impurities.

As the sputter gas used for forming the oxide insulating layer 386, it is preferable to use a high purity gas in which impurities such as hydrogen, water, hydroxyl groups, or hydrides are removed to about several ppm concentration and several concentration ppb.

The thin film transistor 380 can be formed by the above process.

Then, in order to alleviate fluctuation in the electrical characteristics of the thin film transistor, heat treatment (preferably at 150 deg. C or more and less than 350 deg. C) may be performed under an inert gas atmosphere or a nitrogen gas atmosphere. For example, heat treatment is performed at 250 DEG C for 1 hour in a nitrogen atmosphere.

Further, heat treatment may be carried out in the atmosphere at 100 ° C or more and 200 ° C or less for 1 hour or more and 30 hours or less. In the present embodiment, heat treatment is performed at 150 占 폚 for 10 hours. This heating treatment may be carried out by heating to a heating temperature of 100 ° C or more and 200 ° C or less from the room temperature, or by repeating several times of cooling from the heating temperature to room temperature. If the heating treatment is performed under reduced pressure, the heating time can be shortened. By this heat treatment, hydrogen is introduced into the oxide insulating layer from the oxide semiconductor layer, whereby a thin film transistor which is normally turned off can be obtained. Therefore, the reliability of the thin film transistor can be improved.

A protective insulating layer 373 is formed on the oxide insulating layer 386. In this embodiment, a silicon nitride film with a thickness of 100 nm is formed as a protective insulating layer 373 by sputtering.

The protective insulating layer 373 and the first gate insulating layer 372a made of a nitride insulating layer do not contain moisture, impurities such as hydrogen, hydrides and hydroxides, and have an effect of preventing them from intruding from the outside.

Therefore, intrusion of impurities such as moisture from the outside can be prevented in the manufacturing process after the protective insulating layer 373 is formed, and the long-term reliability of the device can be improved.

A part of the insulating layer provided between the protective insulating layer 373 made of the nitride insulating layer and the first gate insulating layer 372a is removed so that the protective insulating layer 373 and the first gate insulating layer 372a A contact structure may be used.

Therefore, impurities such as water, hydrogen, hydrides and hydroxides in the oxide semiconductor layer can be reduced as much as possible, the impurity can be prevented from being mixed, and the impurity concentration in the oxide semiconductor layer can be kept low.

Further, a planarization insulating layer for planarization may be provided on the protective insulating layer 373.

Further, a conductive layer overlapping the oxide semiconductor layer may be provided on the protective insulating layer 373. The potential of the conductive layer may be the same as or different from that of the gate electrode layer 381 of the thin film transistor 380, and may function as the second gate electrode layer. The potential of the conductive layer may be a fixed potential of GND or 0V.

The electrical characteristics of the thin film transistor 380 can be controlled by this conductive layer.

By using the transistor having the above structure, a transistor having stable electrical characteristics and high reliability can be provided. Since the transistor has a low leakage current, the transistor can be used to constitute the voltage regulating circuit, which is an aspect of the present invention, so that the arrival speed to the voltage of the desired value can be remarkably improved. Further, by configuring the voltage regulating circuit, which is an aspect of the present invention, by using this transistor, it is possible to provide a voltage regulating circuit having stable electrical characteristics and high reliability.

The present embodiment can be carried out by appropriately combining with other embodiments.

(Embodiment 12)

This embodiment will be described with reference to Figs. 24 (A) and 24 (B) for an example of an electronic apparatus to which a voltage regulating circuit according to an aspect of the present invention can be applied.

24A is a notebook personal computer and includes a main body 3001, a housing 3002, a display portion 3003, a keyboard 3004, and the like. Further, the voltage adjusting circuit shown in the first to third embodiments can be applied to generate the power supply voltage to be supplied to the notebook personal computer shown in Fig. 24 (A).

24 (B) is a cellular phone, which is composed of two housings, a housing 2800 and a housing 2801. Fig. The housing 2801 is provided with a display panel 2802, a speaker 2803, a microphone 2804, a pointing device 2806, a camera lens 2807 and an external connection terminal 2808. In addition, the housing 2800 is provided with a solar cell 2810, an external memory slot 2811, and the like for charging the portable information terminal. In addition, the antenna is built in the housing 2801.

The display panel 2802 is provided with a touch panel, and in Fig. 24B, a plurality of operation keys 2805 displayed in video are indicated by dotted lines. The cellular phone shown in Fig. 24 (B) has a step-up circuit (voltage regulating circuit shown in the first to third embodiments) for stepping up the voltage output from the solar cell 2810 to the voltage required for each circuit Respectively.

As described above, the voltage regulating circuit, which is one aspect of the present invention, can be applied to various electronic apparatuses, and can also supply the power supply voltage efficiently to the electronic apparatuses.

The present embodiment can be combined with other embodiments as appropriate.

101: transistor 102: capacitive element
108: substrate temperature 151: period
152: Period 201: Transistor
202: Capacitive element 211: Unit boost circuit
221: clock signal line 222: clock signal line
300: substrate 302: gate insulating layer
303: protective insulating layer 310: thin film transistor
311: gate electrode layer 313: channel forming region
314a: high resistance source region 314b: high resistance drain region
315a: source electrode layer 315b: drain electrode layer
316: oxide insulating layer 320: substrate
322: gate insulating layer 323: protective insulating layer
330: oxide semiconductor film 331: oxide semiconductor layer
332: oxide semiconductor layer 340: substrate
342: Gate insulating layer 343: Protective insulating layer
345: oxide semiconductor film 346: oxide semiconductor layer
350: thin film transistor 351: gate electrode layer
352: oxide semiconductor layer 355a: source electrode layer
355b: drain electrode layer 356: oxide insulating layer
360: Thin film transistor 361: Gate electrode layer
362: oxide semiconductor layer 363: channel forming region
364a: high resistance source region 364b: high resistance drain region
365a: source electrode layer 365b: drain electrode layer
366: oxide insulating layer 370: substrate
372a: Gate insulating layer 372b: Gate insulating layer
373: Protection insulating layer 380: Thin film transistor
381: gate electrode layer 382: oxide semiconductor layer
385a: source electrode layer 385b: drain electrode layer
386: oxide insulating layer 390: thin film transistor
391: gate electrode layer 392: oxide semiconductor film
393: oxide semiconductor film 394: substrate
395a: a source electrode layer or a drain electrode layer
395b: a source electrode layer or a drain electrode layer
396: oxide insulating layer 397: gate insulating layer
398: protective insulating layer 399: oxide semiconductor layer
400: substrate 402: gate insulating layer
407: Insulating layer 410: Thin film transistor
411: gate electrode layer 412: oxide semiconductor layer
414a: wiring layer 414b: wiring layer
415a: a source electrode layer or a drain electrode layer
415b: a source electrode layer or a drain electrode layer
420: silicon substrate 421a: opening
421b: opening 422: insulating layer
423: opening 424: conductive layer
425: thin film transistor 427: conductive layer
450: substrate 452: gate insulating layer
457: Insulating layer 460: Thin film transistor
461: Gate electrode layer 462: Oxide semiconductor layer
464: wiring layer
465a1: a source electrode layer or a drain electrode layer
465a2: a source electrode layer or a drain electrode layer
465b: a source electrode layer or a drain electrode layer
468: wiring layer 501: transistor
502: Capacitive element 511: Unit step-down circuit
521: clock signal line 522: clock signal line
800: measuring system 802: capacitive element
804: transistor 805: transistor
806: transistor 808: transistor
1001: gate electrode 1002: gate insulating film
1003: oxide semiconductor layer 1004a: source electrode
1004b: drain electrode 1005: oxide insulating layer
1006: conductive layer 2800: housing
2801: housing 2802: display panel
2803: Speaker 2804: Microphone
2805: Operation key 2806: Pointing device
2807: Camera lens 2808: External connection terminal
2810: Solar cell 2811: External memory slot
3001: main body 3002: housing
3003: Display section 3004: Keyboard

Claims (9)

A semiconductor device comprising:
A transistor including a channel forming region, a gate, a source, and a drain; and a capacitive element including a first electrode and a second electrode,
Wherein the channel forming region comprises an oxide semiconductor material and the off current of the transistor is 100 < z > / mu m or less under the condition that the temperature is 85 DEG C and the source-drain voltage is 3.1 V,
And the first electrode is electrically connected to one of the source and the drain of the transistor.
A semiconductor device comprising:
A first transistor and a second transistor;
A first capacitor; And
And a second capacitor element,
Wherein the first transistor and the second transistor each include a channel forming region, a gate, a source, and a drain,
Wherein the channel forming region includes an oxide semiconductor material and the off current of the first transistor and the second transistor is 100 zA / 占 퐉 or less at a temperature of 85 占 폚 and a source-drain voltage of 3.1 V,
The gate of the first transistor being electrically connected to one of the source and the drain of the first transistor,
A first electrode of the first capacitor is electrically connected to the other of the source and the drain of the first transistor,
The other of the source and the drain of the first transistor is electrically connected to one of the source and the drain of the gate of the second transistor and the second transistor,
And a first electrode of the second capacitor is electrically connected to the other of the source and the drain of the second transistor.
A semiconductor device comprising:
A transistor including a channel forming region, a gate, a source, and a drain; and a capacitive element including a first electrode and a second electrode,
Wherein the channel forming region comprises an oxide semiconductor material and the off current of the transistor is 100 < z > / mu m or less under the condition that the temperature is 85 DEG C and the source-drain voltage is 3.1 V,
The first electrode being electrically connected to one of the source and the drain of the transistor,
Wherein the concentration of hydrogen contained in the oxide semiconductor material is 5 x 10 < ¹⁹ > / cm < ³ > or less.
The method according to claim 1 or 3,
Wherein the off current of the transistor is 10 < RTI ID = 0.0 > zA /.
3. The method of claim 2,
And the off current of the first transistor and the second transistor is 10 < z > / mu m or less.
4. The method according to any one of claims 1 to 3,
Wherein the oxide semiconductor material has a transistor carrier concentration of 5 x 10 < ¹⁴ > / cm < ³ > or less.
4. The method according to any one of claims 1 to 3,
Wherein the semiconductor device is a voltage regulating circuit.
4. The method according to any one of claims 1 to 3,
Wherein the oxide semiconductor material is an In-Ga-Zn-O-based oxide semiconductor.
4. The method according to any one of claims 1 to 3,
Wherein the oxide semiconductor material comprises gallium, indium, and zinc.

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