KR101808776B1 - A communication mediating device for chips - Google Patents

A communication mediating device for chips Download PDF

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Publication number
KR101808776B1
KR101808776B1 KR1020150174050A KR20150174050A KR101808776B1 KR 101808776 B1 KR101808776 B1 KR 101808776B1 KR 1020150174050 A KR1020150174050 A KR 1020150174050A KR 20150174050 A KR20150174050 A KR 20150174050A KR 101808776 B1 KR101808776 B1 KR 101808776B1
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KR
South Korea
Prior art keywords
chip
block
bus
address
inter
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KR1020150174050A
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Korean (ko)
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KR20170067405A (en
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문현정
이상헌
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문현정
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network

Abstract

The present invention introduces a chip-to-chip communication intermediary device capable of reusing a bus control signal, ID conversion of an address area of a reception chip, conversion of a bus ID width of a reception chip, and transmission of an interrupt signal and a message signal, do. The chip-to-chip communication mediation apparatus according to the present invention, when designating the address of a functional block installed in a receiving chip in a transmitting chip, converts the address of the functional block of the receiving chip specified by the transmitting chip into a promised one, A function of converting the bus ID width between the transmitting chip and the receiving chip into a system in which the bus ID width is preliminarily agreed, a function of not duplicating the same bus control signal, and a function of receiving at least one message and an interrupt signal And transferring the address signal and the data included in the subsequent address signal to the chip.

Description

[0001] A communication mediating device for chips [

The present invention relates to a chip-to-chip communication mediator, and more particularly to a chip-to-chip communication mediator that reuses bus control signals transmitted and received between chips, performs ID conversion of an address area of a receiving chip, To-chip communication intermediary device capable of delivering the highest priority after occurrence.

Recently, Internet Of Things (IoT) applications have been increasing, but due to limitations in microfabrication of semiconductor devices, rather than implementing a specific application as a single chip, many chips that perform different functions are connected There is an increasing demand for implementing systems that perform various functions. In order to connect two or more chips, various interface methods including I2C and SPI have been proposed as inter-chip communication protocols. However, these methods suggest a method of data conversion transferred between chips, It is not. (Patent Registration No. 10-1164355)

Currently, chip-to-chip communication uses a method of establishing a host-slave relationship so that a host chip accesses a limited address area of a slave chip in a limited manner. However, this method has considerable limitations in integrating the functions of a plurality of chips into a single communication method.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and it is an object of the present invention to provide a method and apparatus for reusing a bus control signal, ID conversion of an address area of a reception chip, conversion of bus ID width of a reception chip, And to provide an intermediate apparatus.

According to another aspect of the present invention, there is provided an inter-chip communication mediator comprising: a first inter-chip communication mediating block for processing commands and data from a transmitting chip and transmitting commands and data from the receiving chip to a transmitting chip; A second inter-chip communication mediating block for transferring the processed command and data transmitted from the first inter-chip communication mediating block to the receiving chip, processing the command and data applied from the receiving chip, and transmitting the processed command and data to the first inter- . Here, each of the first inter-chip communication mediating block and the second inter-chip communication mediating block is configured such that when an address of a functional block installed in the receiving chip is designated by the transmitting chip, the address of the functional block of the receiving chip specified by the transmitting chip is set in advance A function of converting the bus ID width between the transmitting chip and the receiving chip into a predetermined arrangement, a function of not duplicating the same bus control signal, and a function of transmitting at least one And transferring the message and the interrupt signal included in the subsequent address signal and data when transmitting the message and the interrupt signal to the receiving chip.

As described above, the interchip communication mediating apparatus according to the present invention is a device that interrupts communication between the interchip communication intermediary apparatus and the interchip communication interposing apparatus via a bus, such as reuse of the bus control signal, ID conversion of the address area of the reception unit chip, conversion of the bus ID width of the reception unit chip, Thereby enabling the chips to be connected to each other to perform free and effective communication with the respective chips.

Figure 1 shows the relationship between chip-to-chip communication mediator and chips according to the present invention.
2 illustrates a protocol for performing inter-chip communication in an inter-chip communication mediation block according to the present invention.
FIG. 3 shows an embodiment of functional blocks constituting one inter-chip communication mediation block constituting the inter-chip communication mediation apparatus according to the present invention.
4 illustrates the bus ID remapping process.
5 illustrates the process of reusing the bus control signal.
6 illustrates a change in the signal output from the transmission interface.
FIG. 7 illustrates a technical field in which the interchip communication intermediary apparatus according to the present invention can be used.

In order to fully understand the present invention and the operational advantages of the present invention and the objects achieved by the practice of the present invention, reference should be made to the accompanying drawings, which are provided for explaining exemplary embodiments of the present invention, and the contents of the accompanying drawings.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like reference symbols in the drawings denote like elements.

Figure 1 shows the relationship between chip-to-chip communication mediator and chips according to the present invention.

Referring to FIG. 1, the inter-chip communication mediation apparatus 100 according to the present invention mediates communication between two chips 110 and 120. The two chips 110 and 120 transmit and receive commands and data to and from the outside through a master bus, a slave bus, a central processing unit (CPU), and a codec (codec) Lt; / RTI > is possible only if there is a promised protocol between each other. It is common that chips with various functions are not equipped with functional blocks or programs related to communication with external devices and the present invention mediates communication between the various chips 110 and 120 in such conditions, We propose a chip-to-chip communication intermediary device capable of performing core ideas.

The inter-chip communication mediation apparatus 100 according to the present invention is composed of two inter-chip communication mediation blocks 101 and 102, and one of the two inter-chip communication mediation blocks 101 and 102 is connected to the transmission unit And the other performs the function of the receiver. The two inter-chip communication intermediation blocks 101 and 102 constituting the inter-chip communication mediator 100 may be constituted by separate chips and may be implemented one by one in a chip for performing communication.

The key idea of the present invention is as follows.

The addresses of the functional blocks constituting each of the chips 110 and 120 may be set differently from each other. In the present invention, the number of functional blocks installed in the receiving chip (for example, 120) When the address is specified, the address of the functional block of the receiving chip designated by the transmitting chip is converted as previously promised and then transmitted to the receiving chip so that the addresses of the functional blocks of the receiving chip specified by the transmitting chip can be matched with each other exactly do.

Since the bus ID widths used in the respective chips are also different from each other, the bus ID widths between the two chips that perform communication are converted into a scheme that is predetermined before use.

In the case where a bus control signal requesting the use of the same bus among chips is continuously used, the present invention maximizes the transmission efficiency by preventing duplicate bus control signals from being transmitted.

When transmitting at least one message and an interrupt signal generated in a transmitting chip to a receiving chip, the interrupt signal and the message are transmitted in a priority order by transmitting the at least one message and an interrupt signal included in an address signal and data.

Hereinafter, how the four core ideas of the present invention are performed through a certain process will be described below.

1, the inter-chip communication mediation apparatus according to the present invention should be composed of two inter-chip communication mediation blocks. One inter-chip communication mediation block may perform a transmitting function or a receiving function according to a communication direction In addition, since the internal configuration is the same, only one inter-chip communication mediation block will be described for convenience of explanation.

Before describing the present invention in detail, a protocol for performing chip-to-chip communication will be described in order to facilitate understanding of the operation of the present invention. In the following description, the inter-chip communication mediator 100 transmits and receives an address, a control signal and data according to an AMBA (Advanced Micro-controller Bus Architecture) bus protocol, which is an industry standard.

Chip intercommunication apparatus 100 according to the present invention which performs a function of receiving an AXI (Advanced Extensible Interface) signal or an Advanced High Performance Bus (AHB) (101, 102) are switched to the following protocol in synchronization with the same clock.

2 illustrates a protocol for performing inter-chip communication in an inter-chip communication mediation block according to the present invention.

Referring to FIG. 2, it can be seen that the two inter-chip communication mediation blocks 101 and 102 operate according to the same clock. 'Valid' is a signal indicating that command or data transmission is valid when transmitting to the other chip, that is, the receiving chip. 'Ready' indicates that the receiving chip is' command 'or' data ', and' command 'is a signal that indicates what' valid 'is currently and what the transfer' data 'means.

0 - No transaction (rest state)

1 - Address transfer to write data

2 - Address transfer to read data

3 - pass data to be written or read

4 - forward response to previous delivery

5 - means that the current valid is the last pass of read or write

6 - Interrupt source forwarding

7 - Forward Message

The inter-chip communication mediating block according to the present invention uses the above-mentioned protocol. In case of transmitting the write address of AXI or AHB, the inter-chip communication mediating block sends command 1 (address transfer to be written) . In the case of AXI or AHB read address transfer, the read address will be transmitted as inter-chip data with command 2 (address transfer to be read).

In the drawing, a and b correspond to the left chip 110 and the right chip 120 shown in FIG. 1, respectively. Therefore, a2b denotes a signal transmitted from the chip 110 on the left side to the chip 120 on the right side, and b2a is the opposite.

FIG. 3 shows an embodiment of functional blocks constituting one inter-chip communication mediation block constituting the inter-chip communication mediation apparatus according to the present invention.

3, the inter-chip communication mediation block 101/102 constituting the inter-chip communication mediator 100 according to the present invention includes an address re-mapping block 310, a bus ID remapping block 320, A control signal pattern processing block 330, a message monitor block 340, an interrupt monitor block 350 and a transmission / reception interface 360, 370.

A Bus Control Signal (Bus Control Signal: Bus ID, Burst, Size, R / W ...) is provided between the bus master I / F 301 and the inter- And a bus data signal (Bus Data Signal) are transmitted and received between the processor interface 302 and the processor I / F 302. The processor interface 302 transmits a message generated by a processor such as an ARM, To the communication mediator 100, and the interrupt interface (303, Interrupt I / F) transfers all the interrupt signals generated in a certain chip to the inter-chip communication mediator 100.

The address re-mapping block 310 re-maps an address designating a constituent element of a neighboring chip among a plurality of signals applied from the bus master interface 301 according to an appointment.

The internal components applied to each chip are different from each other. In consideration of this difference, in order for a certain chip (transmitting chip) to access a functional block at an address of a specific area of another chip (receiving chip) , It is natural that the target area will not be accessible due to the address conflict. For example, the unique addresses assigned to DDR, Flash, CPU, and Video Codec are different on chip A and chip B. Therefore, in order to perform normal communication of the two chips A and B, there must be a promise of address remapping.

The remapping process can be variously implemented, for example, remapping by changing the upper bits of the address according to an appointment. Although not shown in detail in FIG. 3, it is preferable that a remapping appointment table to be referred to when performing remapping is included in the address re-mapping block 310.

The bus ID remapping block 320 performs a bus ID remapping to match the bus ID signal applied from the bus master interface 301 with the width (Width) of the bus ID signal of the adjacent chip (reception chip).

Since the AXI bus standard has separate address channels and data channels, address-to-data pairs can be matched using bus IDs, since address and data can not be interconnected in a numerical access scheme. For example, if the 'write address, control' request is sent to the address channel with AWID 3, the corresponding 'write data' will be matched only if the ID is equal to WID 3. Due to the use of such a bus ID, the bus ID width may be different for each configuration of the bus layer. The different chips are composed of different bus systems. It is a result. Therefore, bus ID widths must be matched for bus communication between different chips, which means that bus ID widths are expanded or decreased as needed.

Like the address re-mapping, the bus ID widths must be in agreement with each other, and a remapping table may also be included in the bus ID remapping block 320. [

4 illustrates the bus ID remapping process.

4, the bus ID width of 4 bits applied from the left transmission chip is converted into a signal having the bus ID width of 3 bits through the bus ID remapping block 320. [ That is, since the bus ID width of the left transmission chip is 4 bits, the width of the bus ID transmitted from the left transmission chip to the right reception chip is 4 bits. However, in order to accurately recognize the bus ID width, Bit, and this conversion must follow the rules promised in advance.

4, the bus ID width of 3 bits applied from the right transmission chip is converted into a signal having the bus ID width of 4 bits through the bus ID remapping block 320. That is, since the bus ID width of the transmission chip on the right side is 3 bits, the width of the bus ID transmitted from the transmission chip on the right side to the reception chip on the left side is 3 bits. However, Bit. ≪ / RTI >

The bus control signal pattern processing block 330 analyzes a pattern of a bus control signal among signals applied from the bus master interface 301 and outputs a bus control signal If the signals are the same, reuse the previous bus control signal.

The inter-chip communication arbiter 100 according to the present invention interfaces with a system bus in an arbitrary chip and simultaneously converts a bus master signal and a bus slave signal to a chip serving as a target. If the bus control signal applied in the immediately preceding sequence is the same as the bus control signal applied in the immediately following sequence, the previous bus control signal is reused to determine the usage rate of the I / O pin of the interchip communication interface And at the same time maximize the communication speed between chips.

5 illustrates the process of reusing the bus control signal.

5, when the same bus control signal (Control A) is continuously applied for two time periods (1st, 2nd) from one chip (transmission chip), the inter-chip communication arbiter The bus control signal pattern processing block 330 configuring the bus control signal pattern processing block 330 does not continuously transmit the same bus control signal Control A to the target chip And transmits it. That is, the bus control signal Control A is transmitted in the first time period (1st), but only the address and data (Address A2 / Data D2) are transmitted in the subsequent time period (2nd) without transmitting the bus control signal (Control A) send.

The message monitor block 340 monitors messages applied from the processor interface 302. The interrupt monitor block 350 monitors all the interrupt signals applied from the interrupt interface 303. [

Most of the chips have a central processing unit (CPU), and the CPU controls and manages the entire chip. In order to efficiently control the H / W engines in the chip, an interrupt signal is used. When there is a request to transfer an interrupt signal or a message between the CPUs to control H / W engines in a neighboring chip, the inter-chip communication intermediary apparatus 100 according to the present invention transmits a message All of the messages applied to the monitor block 340 and the interrupt interface 303 can be transferred to the target chip (receiving chip) with the highest priority.

The transmit interface 360 of the transmit and receive interfaces 360 and 370 includes an address re-mapping block 310, a bus ID remapping block 320, a bus control signal pattern processing block 330, a message monitor block 340, According to a signal output from the block 350, a signal including a bus control signal, a remapped address, a remapped bus ID width, an interrupt, and a message is transmitted to a receiving chip through a neighboring inter-chip communication mediation block.

The receiving interface 370 retransmits the signal transmitted from the neighboring chip-to-chip communication intermediary block to the bus master interface 301 and the bus slave interface 304.

6 illustrates a change in the signal output from the transmission interface.

In the upper part of FIG. 6, three bus control signals (Control) generated during an arbitrary chip (transmission chip) during three time intervals (1st, 2nd, 3rd) and applied to the interchip communication interposer 100 according to the present invention A, Control A and Control B), three addresses (Address A1, Address A2 and Address B1), three data (Data D1, Data D2 and Data D1), one interrupt signal Message is shown. Here, the same two bus control signals (Control A) are applied continuously for two time periods (1st, 2nd), an interrupt signal (Interrupt) is applied for the first time period (1st) 2 < nd >) is being applied.

A plurality of signals applied during the three time intervals are converted into signals such as those shown in the lower portion of Fig. 6, while passing through the inter-chip communication intermediation apparatus according to the present invention.

Referring to the lower portion of FIG. 6, the first chip 1 receives a bus control signal (Control A), an address (Address A1) and data (Data D1) (Address A2) and data (Data D2) not including the bus control signal (Control A) are stored in the interval (2nd) and a third bus control signal (Control B) and address B1) and data (Data D1). An interrupt signal and a message to be transmitted with the highest priority are inserted and transmitted at the leading end of the immediately following time interval. That is, an interrupt signal generated in the first time interval (1st) is inserted between the first time interval (1st) and the second time interval (2nd) at the time of transmission, (Message) is inserted and transmitted between the second time interval (2nd) and the third time interval (3rd).

Referring to FIG. 6, only one of the same bus control signals (Control A) applied successively is reflected, and it can be seen that the interrupt signal and the message signal are transmitted with priority as soon as they are generated.

FIG. 7 illustrates a technical field in which the interchip communication intermediary apparatus according to the present invention can be used.

7 shows that the chip-to-chip communication mediator according to the present invention can be implemented using a plurality of FPGAs (Field Programmable Gate Arrays) before mass production of ASIC chips made specifically according to the request of the purchaser, The embodiment shows an embodiment in which a system is implemented through a plurality of inter-chip connections performing different functions. In the example of a system in which a plurality of identical chips are connected in parallel on the right side, it can be used for realizing high performance.

While the present invention has been described in connection with what is presently considered to be the most practical and preferred embodiment, it is to be understood that the invention is not limited to the disclosed embodiments. It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the scope of the present invention.

101, 102: inter-chip communication mediation block
310: address re-mapping block 320: bus ID remapping block
330: Bus control signal pattern processing block 340: Message monitor block
350: Interrupt monitor block 360: Transmission interface
370: receiving interface

Claims (6)

A first inter-chip communication mediating block for processing commands and data applied from the transmitting chip and transmitting commands and data from the receiving chip to the transmitting chip; And
A second inter-chip communication mediating block for transferring processed commands and data transmitted from the first inter-chip communication mediating block to a receiving chip, processing commands and data applied from the receiving chip and transmitting the processed commands and data to the first inter-chip communication mediating block; / RTI >
Wherein each of the first inter-chip communication mediation block and the second inter-chip communication mediation block comprises:
A function of converting the address of the functional block of the receiving chip specified by the transmitting chip into a predetermined function and transmitting the address to the receiving chip when designating the address of the functional block installed in the receiving chip in the transmitting chip;
A function of converting the bus ID width between the transmitting chip and the receiving chip into a system in which the bus ID width is prearranged;
A function of not duplicating and transmitting the same bus control signal; And
Transmitting at least one message and an interrupt signal generated in the transmitting chip to the receiving chip when the receiving chip transmits the at least one message and the interrupt signal; medium
Perform at least one,
Wherein each of the first inter-chip communication mediation block and the second inter-chip communication mediation block comprises:
An address re-mapping block for re-mapping, according to an appointment, an address designating a component of a receiving chip among a plurality of signals applied from a bus master interface connected to the transmitting chip;
A bus ID remapping block for performing bus ID remapping to match the bus ID signal applied from the bus master interface with the bus ID signal of the receiving chip;
A bus control unit for analyzing a pattern of a bus control signal among signals applied from the bus master interface and for reusing a previous bus control signal when a bus control signal applied in a subsequent sequence is the same as a bus control signal applied immediately before, A signal pattern processing block;
A message monitor block for monitoring a message applied from a processor interface connected to the transmitting chip;
An interrupt monitor block for monitoring all interrupt signals applied from an interrupt interface connected to the transmitting chip;
In response to a signal output from the address re-mapping block, the bus ID remapping block, the bus control signal pattern processing block, the message monitor block, and the interrupt monitor block, a bus control signal, a remapped address, A transmission interface for transmitting a signal including a bus ID width, an interrupt signal and a message to a neighboring inter-chip communication mediation block; And
And a receiving interface for retransmitting a signal transmitted from a neighboring chip-to-chip communication intermediary block to the bus master interface and the bus slave interface. delete The method according to claim 1,
Wherein each of the first inter-chip communication mediation block and the second inter-chip communication mediation block comprises:
Further comprising a predetermined re-mapping table referred to when the address re-mapping block and the bus ID re-mapping block perform the remapping function. The method according to claim 1,
Wherein the address re-mapping block comprises:
And performs the address re-mapping by changing the upper bits of the applied address in accordance with an appointment. The method according to claim 1,
Wherein the transmission interface comprises:
Wherein the interrupt signal and the message issued in a predetermined time interval are transmitted in a time interval following the arbitrary time interval. The method according to claim 1,
The first inter-chip communication mediating block and the second inter-chip communication mediating block,
Chip communication intermediation device.
KR1020150174050A 2015-12-08 2015-12-08 A communication mediating device for chips KR101808776B1 (en)

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Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014007695A (en) 2012-06-27 2014-01-16 Canon Inc Cascade-connection-based communication system and communication device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014007695A (en) 2012-06-27 2014-01-16 Canon Inc Cascade-connection-based communication system and communication device

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