KR101804270B1 - CMOS stacked FET antenna switch on high resistivity silicon substrate - Google Patents

CMOS stacked FET antenna switch on high resistivity silicon substrate Download PDF

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KR101804270B1
KR101804270B1 KR1020150040072A KR20150040072A KR101804270B1 KR 101804270 B1 KR101804270 B1 KR 101804270B1 KR 1020150040072 A KR1020150040072 A KR 1020150040072A KR 20150040072 A KR20150040072 A KR 20150040072A KR 101804270 B1 KR101804270 B1 KR 101804270B1
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Prior art keywords
terminal
antenna switch
transistor
substrate
transistors
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KR1020150040072A
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Korean (ko)
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KR20160113851A (en
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임동구
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전북대학교산학협력단
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • H03K17/6871—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • H03K17/693—Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/38—Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving
    • H04B1/40—Circuits
    • H04B1/44—Transmit/receive switching

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

The present invention realizes an antenna switch by using a transistor laminated on a substrate having a high resistance so that an overvoltage is applied to a transistor disposed at an initial stage of an input signal among a plurality of transistors constituting the antenna switch so as not to be damaged, We propose a CMOS laminated transistor antenna switch based on a high-resistivity semiconductor substrate that isolates and isolates barrier ribs between transistors and lowers production costs compared to conventional GaAs processes and SOI CMOS processes. To this end, a conductive substrate is formed on a high-resistance semiconductor substrate, a unit transistor constituting an antenna switch is formed on the conductive substrate, and an N-well is formed between the conductive substrate and the high-resistance substrate.

Figure R1020150040072

Description

[0001] The present invention relates to a CMOS stacked FET antenna switch on a high resistivity semiconductor substrate,

The present invention relates to a CMOS laminated transistor type antenna switch, and more particularly, to a CMOS laminated transistor antenna switch based on a high resistance semiconductor substrate that minimizes leakage current toward a substrate and improves isolation of the transistor.

[Background Art] [0002] With the trend toward smaller and slimmer portable terminals, an RF front-end module (FEM) mounted on a portable terminal such as a smart phone is required to be made smaller and inexpensive. In general, the RF front-end module mounted on a portable terminal is implemented as a multi-chip based on GaAs HBT, GaAs p-HEMT, SiGe, SOI CMOS and standard CMOS process, and a single-pole multi And a single-pole mutli-throw antenna switch. This will be described with reference to Fig.

FIG. 1 shows a circuit diagram according to an example of a single-pole multi-drop antenna switch according to an example of a conventional RF front-end module, and FIG. 2 is a reference diagram showing an example of an output waveform of the antenna switch of FIG. Respectively.

Referring to FIGS. 1 and 2, a conventional single-pole multi-drop antenna switch includes a plurality of switch cells 30 and 40 (switch cells) each including a serial switch 10 and a parallel switch 20, Lt; / RTI > A transmitter or a receiver may be connected to each of the antenna switch terminals 31 and 41. (Figure 1 Correction)

In the conventional single-pole multi-drop antenna switch, a parallel switch 20 is connected together with the series switch 10 in order to enhance the isolation between the terminals 31 and 41. For example, when the path between the TX terminal 31 and the antenna 50 is connected, the serial switch 10 in the switch cell 30 is turned on and the parallel switch 20 is turned off, When the path between the TX terminal 31 and the antenna 50 is cut off, the serial switch 10 is turned off and the parallel switch 20 is turned on. Each transistor 10a to 10n is connected between the gate terminal G and the body terminal B in order to keep the turn-on transistor ON even when a signal having a large voltage amplitude is applied in the turn- A floating gate / body technique may be applied in which a resistor having a high resistance between the gate and the body is connected. On the other hand, in the transistor which is in an OFF state, the gate of each transistor (for example, 10a to 10n) and the body terminal A negative voltage other than 0v may be applied.

On the other hand, in order to increase the output of the antenna, the transistors (for example, 10a to 10n) need to have a laminated structure.

When a low-voltage swing that is beyond the breakdown voltage that can be tolerated by the single transistor 10a to 10n is required, the single transistor 10a to 10n may be destroyed by the input voltage (breakdown voltage). However, as shown in FIG. 2, when a plurality of transistors 10a to 10n are stacked in series, the voltage amplitude is divided by the number of stacked layers (n) so that a signal having a large voltage amplitude can be received .

Regarding such an antenna switch, Patent Document 10-0325087 discloses a structure in which an insulating film is formed on an electrode formed on a GaAs substrate to provide a cover electrode, and the potential of the cover electrode is controlled externally, Switch. However, the GaAs substrate is expensive to manufacture even when compared with the standard CMOS process and the SOI CMOS process, and there is a problem that the antenna switch controller needs to be separately fabricated through a standard CMOS process due to limitations of transistor integration.

An object of the present invention is to provide a CMOS laminated transistor antenna switch based on a high resistance semiconductor substrate which minimizes the leakage current of an antenna switch and implements an antenna switch by stacking transistors on a high resistance substrate and isolating each of the stacked transistors .

According to an aspect of the present invention, there is provided a semiconductor device comprising: a conductive substrate formed on a high-resistance semiconductor substrate; a unit transistor forming an antenna switch formed on the conductive substrate; And the drain terminal and the source terminal of the transistor are connected in series to the source terminal and the drain terminal of the neighboring other unit transistors, respectively.

Here, the unit transistors can be isolated by STI (Shallow Trench Isolation) with other neighboring unit transistors.

In addition, in the unit transistor on the conductive substrate, a gate terminal and a body terminal are formed, a floating resistor is connected between the gate terminal and the body terminal, and a negative voltage can be applied through the floating resistor .

Here, an N-well terminal connected to the N-well is formed on the conductive substrate, and a DC voltage higher than the supply voltage VDD can be generated from the DC-DC converter and applied to the N-well terminal.

Here, the resistance ratio of the high-resistance semiconductor substrate may be a value between 500 Ω / cm 2 and 2 kΩ / cm 2.

Here, the unit transistor closest to the input to which the signal of the lamination transistor is applied is composed of a gate terminal G, a source terminal S, a gate terminal G, a drain terminal D, a body terminal B, And a capacitor connected between the drain terminal D, the body terminal B, the small terminal S, and the source terminal S and the drain terminal D, respectively.

According to the present invention, a conductive substrate is formed on a high-resistance semiconductor substrate, a unit transistor constituting an antenna switch is formed on the conductive substrate, and the conductive substrate and the high-resistance substrate are isolated by N-well. By applying a DC voltage equal to or higher than the supply voltage (VDD) applied to the N-well terminal, isolation between the conductive substrate, the N-well, and the high resistance substrate is maximized. A plurality of unit transistors previously implemented are connected in series to form a laminated transistor, and the neighboring unit transistors are isolated by STI to enable ideal laminated transistor operation.

The small leakage current and the STI between the unit transistors caused by the high resistance substrate enable an ideal stacked transistor operation and can prevent the breakdown by reducing the voltage stress of the transistor disposed at the beginning of the place where the high power signal is applied. This, in turn, enables the implementation of a high-power antenna switch through standard CMOS processes, which can significantly reduce the production cost of a high-output antenna switch implemented through conventional expensive GaAs to SOI CMOS processes.

FIG. 1 shows a circuit diagram according to an example of a single-pole multi-drop antenna switch according to an example of a conventional RF front-end module.
Fig. 2 shows a reference diagram of an example of the output waveform of the antenna switch of Fig.
FIGS. 3 and 4 illustrate cross-sectional views of an antenna switch substrate formed according to a standard CMOS process and an SOI CMOS process, respectively.
5 is a cross-sectional view of a substrate of a CMOS laminated transistor antenna switch based on a high-resistance semiconductor substrate according to an embodiment of the present invention.
FIG. 6 shows an example of an input terminal transistor in the laminated transistor implemented in FIG.

Hereinafter, the present invention will be described in detail with reference to the drawings.

FIGS. 3 and 4 illustrate cross-sectional views of an antenna switch substrate formed according to a standard CMOS process and an SOI CMOS process, respectively. FIG. 5 is a cross- Switch (hereinafter, referred to as a high-resistance substrate CMOS antenna switch). Fig. 3 to Fig. 5 together will be described below.

First, FIG. 3 illustrates an example of implementing a stacked transistor in the standard CMOS process shown.

In a standard CMOS process, when transistors are stacked for antenna switch formation, each transistor 50, 60 is isolated by N-wells 52, 62. However, each of the transistors 50 and 60 isolated by the N-wells 52 and 62 is connected to the N-well 52, the P-well 53, and the N-well 52, The equal voltage may not be distributed to each of the transistors 50 and 60 to be stacked due to the leakage current path formed toward the substrate 51 having the diode capacitance and the low resistance ratio. If the signal is initially applied to the transistor 50 and the voltage of the applied signal exceeds the tolerance of the transistor 50, the transistor 50 may be damaged by the stress applied to the transistor 50 . The feature of such a CMOS process is that it is difficult to implement a high output antenna switch.

Next, FIG. 4 shows an example of implementing a stacked transistor in an SOI (Silicon On Insulation) CMOS process.

Referring to FIG. 4, when compared with the standard CMOS process described with reference to FIG. 3, a BOX (Buried Oxide) layer 71 and a high resistivity (5002? To 2? / Cm2, preferably 1? / Cm2) Due to the high-resistance substrate, the degree of isolation of each of the transistors 70a to 70n increases, enabling the operation of the ideal stacked transistor, and uniform voltage can be applied to each of the transistors 70a to 70n. However, there is a drawback that the price of a CMOS antenna switch produced due to a high price compared to a standard CMOS process increases.

Applicants have combined the advantages of a standard CMOS process with the advantages of a low production cost and the advantages of a SOI CMOS process with high isolation characteristics so that each transistor of the stacked structure maintains high isolation characteristics while maintaining good productivity and ratios. A high-resistance substrate CMOS antenna switch structure is proposed. 5 shows a CMOS antenna switch structure proposed by the present applicant. Hereinafter, a CMOS antenna switch according to an embodiment will be described with reference to FIG.

5, a CMOS antenna switch according to an embodiment includes a conductive substrate 120 formed on a high resistivity substrate (P-type substrate) having a range of 500-cm to 2-cm, An N-well 130 may be formed between the substrate 100 and the substrate 101 to isolate the transistors 100a, 100b, and 100c. Each of the transistors 100a, 100b and 100c may be formed by forming a doping region by doping a conductive substrate 120 with a p-type or an n-type to connect the electrodes to the formed doping region to form an electrode on the conductive substrate 120 have . 5, a source terminal S, a gate terminal G, a drain terminal D, a body terminal B, and an N-well terminal DN are formed on a conductive substrate 120.

 Small leakage currents due to the high resistance substrate and the STI between the unit transistors enable the ideal stacked transistor operation and reduce the voltage stress of the transistors disposed at the first stage where the high power signal is applied to the transistors 100a, 100b and 100c Which means that even voltage can be applied.

This implies that the high-resistance substrate CMOS antenna switch according to the embodiment implemented on the P-type substrate 101 similar to the CMOS process can achieve higher power driving efficiency and efficiency than the antenna switch produced according to the standard CMOS process do.

In addition, like the antenna switch produced according to the CMOS process of the SOI substrate, the generation of the leakage current path between the substrate 101 and the transistors 100, 100b and 100c is cut off or minimized to constitute a CMOS antenna switch, When applied, an equal voltage can be applied to each of the transistors 100a, 100b and 100c to be directly connected. As a result, it shows a similar performance to the high output antenna switch realized through the existing expensive GaAs to SOI CMOS process, and the production cost can be greatly reduced.

Meanwhile, a DC voltage may be applied to an N-well terminal (for example, reference numeral DN) of each of the transistors 100a, 100b, and 100c so that the transistors 100a, 100b, and 100c maintain a high degree of isolation. In this case, a DC voltage higher than the driving voltage of each of the transistors 100a, 100b, and 100c can be applied to the N-well terminal (for example, reference numeral DN) of each of the transistors 100a, 100b, and 100c.

FIG. 6 shows an example of an input stage transistor in a stacked transistor of the high resistance substrate CMOS antenna switch implemented in FIG.

6, a plurality of transistors 200a to 200n are directly connected to the antenna switch 200a to 200n, and the transistor 200a is connected to a source terminal to form an input terminal IN The transistor 200a located closest to the input IN is connected to the gate terminal G through the source terminal S, the gate terminal G and the drain terminal D, the body terminal B, The capacitors C1 to C4 and CSD can be disposed between the terminal D, the body terminal B, the source terminal S, and the source terminal S and the drain terminal D, respectively. In this case, the capacitors to be disposed may be formed in the order of sequentially adjacent to the input terminal IN of the transistors 200a to 200n constituting the CMOS antenna switch according to the embodiment, It is preferable that the process is simultaneously performed in the process of manufacturing the switch.

When the capacitors C1 to C4 and CSD are formed in the transistor 200a, the size of the signal driven by the transistor 200a can be partially reduced. By this damping effect, Lt; / RTI >

It should be noted that the embodiments of the present invention disclosed in the present specification and drawings are only illustrative of the present invention in order to facilitate description of the present invention and to facilitate understanding of the present invention and are not intended to limit the scope of the present invention. It will be apparent to those skilled in the art that other modifications based on the technical idea of the present invention are possible in addition to the embodiments disclosed herein.

100a, 100b, 100c: transistor 101: substrate
120: conductive substrate 130: N-well

Claims (6)

In the antenna switch device,
An output terminal of a transmission signal;
antenna; And
And an antenna switch positioned between the output terminal and the antenna,
The antenna switch
A high-resistance semiconductor substrate;
A plurality of conductive substrates formed on the high-resistance semiconductor substrate;
A plurality of N-wells formed between the high-resistance semiconductor substrate and the conductive substrates to isolate the high-resistance semiconductor substrate from the conductive substrates,
A plurality of transistors each formed on the conductive substrates and performing an antenna switch function,
Wherein the transistors are stacked in series, wherein the drain terminal and the source terminal are connected in series to a source terminal and a drain terminal of other unit transistors adjacent to each other, respectively. The method according to claim 1,
The unit transistor includes:
Wherein the first and second transistors are isolated by neighboring unit transistors and STI (Shallow Trench Isolation). The method according to claim 1,
In the unit transistor on the conductive substrate,
A gate terminal and a body terminal are formed,
Wherein a floating resistor is connected between the gate terminal and the body terminal and a negative voltage is applied through the floating resistor. The method according to claim 1,
In the conductive substrate,
An N-well terminal connected to the N-well is formed,
DC voltage is higher than the supply voltage (VDD) from the DC-DC converter and is applied to the N-well terminal. The method according to claim 1,
The high-resistance semiconductor substrate includes:
Wherein the resistance ratio is a value between 500 Ω / cm 2 and 2 kΩ / cm 2. The method according to claim 1,
A unit transistor positioned closest to an input to which the signal of the lamination transistor is applied,
A gate terminal G, a source terminal S, a gate terminal G, a drain terminal D, a body terminal B, a drain terminal D, a body terminal B, And a capacitor connected between the drain terminal (D) and the (S) -drain terminal (D).
KR1020150040072A 2015-03-23 2015-03-23 CMOS stacked FET antenna switch on high resistivity silicon substrate KR101804270B1 (en)

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KR102034620B1 (en) * 2018-05-17 2019-11-18 베렉스 주식회사 High Isolation RF Switch Robust to Parasitic Wire-Bonding Inductor Effect
KR102603803B1 (en) 2020-10-12 2023-11-17 한국전자통신연구원 Apparatus for mixing frequency
KR20220067137A (en) 2020-11-17 2022-05-24 전북대학교산학협력단 Enhanced Low Noise Transistor for Low Noise Amplifier and Low Noise Amplifier including the same

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US5598369A (en) 1994-06-28 1997-01-28 Advanced Micro Devices, Inc. Flash EEPROM array with floating substrate erase operation
US6134150A (en) 1999-07-23 2000-10-17 Aplus Flash Technology, Inc. Erase condition for flash memory
US20060091465A1 (en) * 2004-10-29 2006-05-04 Shiao-Shien Chen Layout of semiconductor device with substrate-triggered esd protection
US7272067B1 (en) 2003-08-22 2007-09-18 Altera Corporation Electrically-programmable integrated circuit antifuses
US7307334B2 (en) 2004-07-29 2007-12-11 Nxp B.V. Integrated circuit having features to limit substrate current
WO2011156289A2 (en) 2010-06-07 2011-12-15 Skyworks Solutions, Inc. Devices and methodologies related to cmos rf

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5598369A (en) 1994-06-28 1997-01-28 Advanced Micro Devices, Inc. Flash EEPROM array with floating substrate erase operation
US6134150A (en) 1999-07-23 2000-10-17 Aplus Flash Technology, Inc. Erase condition for flash memory
US7272067B1 (en) 2003-08-22 2007-09-18 Altera Corporation Electrically-programmable integrated circuit antifuses
US7307334B2 (en) 2004-07-29 2007-12-11 Nxp B.V. Integrated circuit having features to limit substrate current
US20060091465A1 (en) * 2004-10-29 2006-05-04 Shiao-Shien Chen Layout of semiconductor device with substrate-triggered esd protection
WO2011156289A2 (en) 2010-06-07 2011-12-15 Skyworks Solutions, Inc. Devices and methodologies related to cmos rf

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