KR101802001B1 - Method and apparatus for combining interleaver and tone-mapper in wireless communication system - Google Patents

Abstract

A method and apparatus for efficiently combining an interleaver and a tone mapper in a wireless communication system are disclosed. A method of combining an interleaver and a tone mapper using a memory structure according to an exemplary embodiment of the present invention includes: identifying a Low-Density Parity Check (LDPC) code or a Binary Convolution Coding (BCC) code; At least one LLR (Log Likelihood Ratio) is stored in a plurality of addresses of a plurality of piece memories included in a transceiver, the plurality of piece memories supporting tone mapping for the LDPC code and interleaving for the BCC code. ; And reading the plurality of pieces of memory based on the identification result.

Description

[0001] The present invention relates to a method and apparatus for efficiently combining an interleaver and a tone mapper in a wireless communication system,

The following embodiments relate to a method and apparatus for efficiently combining an interleaver and a tone mapper in a wireless communication system.

A wireless LAN is basically an access point (AP) serving as an access point of a distribution system (DS) and a basic service set (APS) composed of a plurality of wireless terminals (STA) (BSS) mode or an independent BSS (IBSS) mode which is composed only of a STA. (Hereinafter, AP and STA will collectively be referred to as "terminal").

In a wireless communication system using multiple antennas, that is, a multiple input multiple output (MIMO) system, channel capacity increases with an increase in the number of antennas, thereby increasing frequency efficiency. The MIMO system can be classified into two types as follows. The first is SU-MIMO, which transmits multiple streams only to a single user. The second is MU-MIMO, which transmits multiple streams to multiple users by eliminating interference between users in the AP.

The MU-MIMO has an advantage that the multi-user diversity gain can be obtained as the channel capacity increases. Also, the MU-MIMO scheme can transmit multiple streams to multiple users at the same time using the same frequency band, thereby increasing the throughput as compared with the conventional communication scheme. In general, although the throughput of the wireless communication system can be increased by increasing the frequency band, there is a disadvantage that the system cost increases as the frequency band increases. On the other hand, although the MU-MIMO scheme does not increase the frequency band, the complexity of the MU-MIMO scheme can be greatly increased compared to the existing communication scheme. Accordingly, standards such as 802.11ac adopts a method of simultaneously applying MU-MIMO technology while using a variable frequency depending on the surrounding situation.

In a wireless LAN system using an OFDM (Orthogonal Frequency Division Multiplexing) modulation scheme, when data is transmitted by performing internal interleaving on a transmitting side, a frequency null Is spread over the entire frequency band, it is possible to improve the performance degradation due to frequency nulls generated in the multipath fading channel environment.

In a wireless communication system, a codeword may be interleaved over a full frequency band in order to obtain a frequency diversity gain and maximize an interleaving effect. In general, when the used frequency band increases, the coding gain and the diversity gain can be obtained by performing coding and interleaving by increasing the codeword and the interleaver to the frequency band size. In IEEE802.11ac, when encoding and interleaving are performed over a plurality of segment frequency bands, a technique of efficiently transmitting the interleaving length by using segment interleaving and segment parsers without increasing the length of the interleaver to a plurality of segment lengths has been adopted. In particular, in the case of LDPC, an LDPC tone mapper for transmitting an LDPC codeword over an entire band is newly added to the standard by using IEEE802.11n LDPC as it is for compatibility.

Embodiments of the present invention can provide a method and apparatus for efficiently combining an interleaver for a BCC code and a tone mapper for an LDPC code using a single memory structure.

A method of combining an interleaver and a tone mapper using a memory structure according to an exemplary embodiment of the present invention includes: identifying a Low-Density Parity Check (LDPC) code or a Binary Convolution Coding (BCC) code; At least one LLR (Log Likelihood Ratio) is stored in a plurality of addresses of a plurality of piece memories included in a transceiver, the plurality of piece memories supporting tone mapping for the LDPC code and interleaving for the BCC code. ; And reading the plurality of pieces of memory based on the identification result.

The number of the plurality of pieces of memory may correspond to a plurality of bandwidths.

The number of the at least one LLR stored in any one of the plurality of addresses may correspond to a modulation scheme.

Wherein storing the at least one LLR in the plurality of addresses may store the at least one LLR in a longitudinal direction from a first address of a first piece memory of the plurality of piece memories to an end address of a last piece memory .

The step of storing at least one LLR in the plurality of addresses when the BCC code is identified comprises: determining whether the IFFT (Inverse Fast Fourier Transform) output received by the receiver of the transceiver is a bit reversing order ; And reordering the at least one LLR stored in the plurality of addresses using a ROM table when the IFFT output is the bit reversing order as a result of the determination.

Storing the at least one LLR in the plurality of addresses when the BCC code is identified may further include storing the at least one LLR in the plurality of addresses by applying a cyclic shift.

In the case of identifying the LDPC code, the step of reading the plurality of pieces of memory based on the identification result may laterally read the plurality of piece memories.

Wherein the step of reading the plurality of pieces of memory based on the identification result when the BCC code is identified comprises reading out a plurality of block data from the plurality of pieces of memory using an address of the plurality of addresses, Each of the plurality of block data including at least one LLR corresponding to the one of the addresses; And a second step of sequentially identifying values corresponding to a last LLR from values corresponding to a first LLR based on at least one LLR included in each of the plurality of block data.

And the step of reading the plurality of pieces of memory based on the identification result may further include the step of repeatedly performing the first step and the second step from the first address to the last address of the plurality of addresses .

The interleaver and tone mapper combining apparatus using the memory structure according to an exemplary embodiment may include a code identifying unit for identifying an LDPC code or a BCC code; A fragment memory store for storing at least one LLR in a plurality of addresses of a plurality of fragment memories included in a transceiver, the plurality of fragment memories supporting tone mapping for the LDPC code and interleaving for the BCC code; ; And a fragment memory read unit that reads the plurality of fragment memories based on the identification result.

The number of the plurality of pieces of memory may correspond to a plurality of bandwidths.

The number of the at least one LLR stored in any one of the plurality of addresses may correspond to a modulation scheme.

The piece memory store may store the at least one LLR in a longitudinal direction from a first address of a first piece memory of the plurality of piece memory blocks to an end address of a last piece memory.

Wherein the fragment memory storing unit comprises: a bit reversing order determiner for determining whether the IFFT output received by the receiver of the transceiver is a bit reversing order; And an LLR reordering unit for reordering the at least one LLR stored in the plurality of addresses using the ROM table when the IFFT output is the bit reversing order as a result of the determination.

When the BCC code is identified, the fragment memory storing unit may further include a cyclic shift applying unit for applying the cyclic shift to store the at least one LLR in the plurality of addresses.

When the LDPC code is identified, the fragment memory read unit can read the plurality of fragment memories in the horizontal direction.

The BCC code is read out from the plurality of block memories by using any one of the plurality of addresses, and each of the plurality of block data is read from the one And at least one LLR corresponding to an address of the first reading unit; And a second reading unit for sequentially identifying values corresponding to a last LLR from values corresponding to a first LLR based on at least one LLR included in each of the plurality of block data.

The fragment memory reading unit may further include the step of repeatedly performing the first reading unit and the second reading unit from the first address to the last address of the plurality of addresses.

Embodiments of the present invention can provide a method and apparatus for efficiently combining an interleaver for a BCC code and a tone mapper for an LDPC code using a single memory structure.

1 is a flowchart illustrating a method of combining an interleaver and a tone mapper using a memory structure according to an exemplary embodiment of the present invention.
2 is a block diagram illustrating a transceiver combining a BCC interleaver and an LDPC tone mapper according to an embodiment.
3 is a diagram for explaining a plurality of piece memories according to an embodiment.
FIG. 4 is a diagram for explaining a process of reading a plurality of fragment memories in the case of a BCC code according to an embodiment.
5 is a block diagram illustrating an interleaver and a tone mapper combining apparatus using a memory structure according to an exemplary embodiment of the present invention.

Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to or limited by the embodiments. In addition, the same reference numerals shown in the drawings denote the same members.

1 is a flowchart illustrating a method of combining an interleaver and a tone mapper using a memory structure according to an exemplary embodiment of the present invention.

Referring to FIG. 1, an interleaver and a tone mapper combining method using a memory structure according to an exemplary embodiment (hereinafter referred to as an interleaver and a tone mapper combining method) can identify an LDPC code or a BCC code. The combining method of the interleaver and tone mapper can support both tone mapping (hereinafter referred to as LDPC tone mapping) for LDPC codes and interleaving (hereinafter referred to as BCC interleaving) for BCC codes using one hardware.

Specifically, when a BCC code is used in a WLAN system, BCC interleaving can be performed on an OFDM symbol basis, and the size of data bits allocated to the symbol can be changed according to the size of the bandwidth and the modulation scheme. As a specific example, in the IEEE 802.11a wireless LAN system, a bandwidth of 20 MHz can be used, and data can be transmitted in 48 subcarriers. In IEEE 802.11n, 52 carriers can be used in a 20 MHz bandwidth and 108 carriers in a 40 MHz bandwidth. IEEE 802.11ac supports 234 in the 80MHz band and 234x2 subcarriers in the 160MHz band while supporting all of the above modes for compatibility. The width of the interleaving block for the above modes is 16 for Legacy 20 MHz bandwidth, 13 for IEEE 802.11n / ac 20 MHz bandwidth, 18 for IEEE 802.11n / ac 40 MHz bandwidth, For an 80 MHz bandwidth, it may have a column of 26 interleaving blocks. In the case of the LDPC code used in 802.11n, the codeword length is larger than the OFDM symbol unit, and the codeword can obtain the frequency diversity gain. However, 802.11ac adds 80MHz 256-QAM, May be smaller in length than the OFDM symbol unit. To overcome this, 802.11ac adopts a specification to further apply tone mapping in the case of using LDPC codes.

More specifically, the BCC interleaving may be performed on an OFDM symbol and stream basis. After the BCC encoded codeword is parsed on a stream basis, the interleaving can be performed by dividing it into symbol units. At this time, the input bits are rearranged into predetermined columns and rows to perform block interleaving to change the order of writing and the order of reading . At this time, the number of rows of the grid block may differ depending on the modulation method. For example, BPSK may be one row, QPSK may be two rows, 16-QAM may be four rows, 64-QAM may be six rows, and 256-QAM may be eight rows. And, BCC interleaving can be written bit by bit, in row order, and can be read in column order. For example, when the modulation scheme is 256-QAM, the number of rows of the grid block may be 8 rows, and the number of columns may be 12 columns. In this case, it is possible to use the same number as 0_0, 1_0, 2_0, 3_0, ... 11_0, 12_0, 0_1, 1_1, 2_1, ... 11_1, 12_1, ..., 0_7, 1_7, You can write a grid block in order. , 13_7, ..., 39_0, 39_1, ..., 39_7, ..., 12_0, 12_1, ..., 12_0, ..., 0_0, 0_2, ..., 0_6, 0_7, 13_0, , 12_7, ..., 51_0, 51_1, ..., 51_7. After writing the grid block, columns in one grid block can be cyclically shifted according to the modulation scheme, and cyclic shifted grid blocks can be read in the column sequence.

In the case of LDPC tone mapping, stream parsing is performed on the encoded bits, and modulation is performed in the input order to generate BPSK, QPSK 16-QAM, 64-QAM, or 256-QAM signals. Then, the generated signal can be transmitted after performing LDPC tone mapping. Specifically, the tone mapping of the modulated signal can also be represented in the form of a grid block. In this case, each grating may be a modulated signal and may be a complex number. The tone mapping can also be written in row order and read in column order. For example, if the indices of each grid of 4 × 13 grid blocks sequentially increase from 0 to 51 according to the column order, 0, 1, 2, ..., 11, 12, ..., 39 , 40, ..., 50, 51, and the modulation signal is written in the order of 0, 13, 26, 39, 1, 14, 27, 40, Readable. This BCC interleaving and LDPC tone mapping can be done in the same way only by varying the size of the grating block at various bandwidths. In general, BCC interleaving and LDPC tone mapping may be implemented in separate hardware, thereby increasing complexity. However, the combining method of the interleaver and tone mapper can effectively combine LDPC tone mapping and BCC interleaving using one memory structure to reduce the size and complexity of the hardware. Thus, in one piece of hardware, if an LDPC code is identified, LDPC tone mapping can be performed and BCC interleaving can be performed if BCC interleaving is identified.

Also, the interleaver and tone mapper combining method may store 120 at least one LLR in a plurality of addresses of a plurality of fragmented memories included in the transceiver. Here, the plurality of fragment memories can support interleaving for tone mapping and BCC codes for LDPC codes. Specifically, the combining method of the interleaver and tone mapper can constitute a plurality of fragmented memories to support 20MHz, 40MHz or 80MHz BCC interleaving and LDPC tone mapping together in one hardware. At this time, the number of pieces of the piece memory can be 26 pieces. This may be due to the number of columns in the interleaving block when the bandwidth is 80 MHz. Thus, the number of pieces of piece memory can correspond to a plurality of bandwidths. For example, eighteen pieces of 26 pieces of piece memory can be used at 40 MHz, and thirteen pieces of pieces of pieces of 26 pieces of piece memory can be used at 20 MHz.

The number of at least one LLR stored in any one of the plurality of addresses may correspond to the modulation scheme. Specifically, one address may include a plurality of block data. The combining method of the interleaver and the tone mapper may store the LLRs in each of the plurality of block data. For example, when the modulation scheme is BPSK, one LLR can be stored in one address, and in case of QPSK, two LLRs can be stored in one address. In the case of 16-QAM, four LLRs can be stored in one address. In the case of 64-QAM, six LLRs can be stored in one address. In the case of 256-QAM, eight LLRs can be stored.

And, the combining method of the interleaver and tone mapper can write a plurality of fragment memories in a row order (e.g., portrait direction) such as a BCC interleaving or an LDPC tone mapper. Thus, the combining method of the interleaver and tone mapper may store at least one LLR in the longitudinal direction from the first address of the first piece memory to the last address of the last piece memory of the plurality of piece memories. For example, after storing at least one LLR in the first address of the first fragment memory, at least one LLR may be stored in the second address of the first fragment memory. Then, after storing at least one LLR in the last address of the first piece memory, at least one LLR may be stored in the first address of the second piece memory. And, in this order, at least one LLR can be stored up to the last address of the last piece memory.

When the BCC code is identified, the combining method of the interleaver and the tone mapper can determine whether the IFFT output received by the receiving end of the transceiver is a bit reversing order. In general, LLRs can be received from the Detector at the receiving end in the order of data tones. However, if it is determined that the IFFT output is a bit reversing order, then the interleaver and tone mapper combining method may reorder at least one LLR stored in the plurality of addresses using the ROM table at the interleaver input.

And, when the BCC code is identified, the combining method of the interleaver and the tone mapper can apply the cyclic shift to store at least one LLR in a plurality of addresses. Thereby, the combining method of the interleaver and the tone mapper can read a block having a cyclic shift in a block of a plurality of fragment memories.

In addition, the combining method of the interleaver and tone mapper can read 130 the plurality of piece memories based on the identification result. At this time, LDPC tone mapping and BCC interleaving may differ in the process of reading a plurality of fragment memories.

Specifically, when the LDPC code is identified, the combining method of the interleaver and the tone mapper can read the plurality of pieces of memory in the horizontal direction. This may mean reading a plurality of fragment memories in a column sequence. For example, a method of combining an interleaver and a tone mapper may read a plurality of piece memories corresponding to a first address, and then a plurality of pieces memories corresponding to a second address.

When the BCC code is identified, the combining method of the interleaver and the tone mapper can perform a process of extracting a corresponding bit while simultaneously reading a plurality of fragment memories. More specifically, it is possible to simultaneously read a plurality of block data from a plurality of piece memories using any one of a plurality of addresses. Here, each of the plurality of block data may include at least one LLR corresponding to any one of the addresses. Then, based on at least one LLR included in each of the plurality of block data, values corresponding to the first LLR can be sequentially identified from the values corresponding to the last LLR. The above process can be repeatedly performed from the first address to the last address among a plurality of addresses. For example, in the case of 20 MHz, a plurality of block data of the first address of thirteen pieces of memory can be simultaneously read, and all the values corresponding to the first LLR among them can be bound and transmitted. Then, 13 values corresponding to the second LLR can be transmitted by binding. Thus, all the values corresponding to the last LLR can be bound and transmitted, and the above process can be repeatedly performed from the second address to the last address.

As described above, by applying different controls according to the LDPC code or the BCC code identified in one memory structure, the combining method of the interleaver and the tone mapper can simultaneously support the LDPC tone mapper and the BCC interleaver.

2 is a block diagram illustrating a transceiver combining a BCC interleaver and an LDPC tone mapper according to an embodiment.

Referring to FIG. 2, the transceiver may include a transmitter 210 and a receiver 220. Generally, when LDPC tone mapping is performed, it is possible to perform stream parsing for encoded bits and perform modulation in an input order. Then, LDPC tone mapping can be performed on the generated signal. However, when using a transceiver according to one embodiment, it is possible to perform LDPC tone mapping at the bit column end before the QAM mapper, such as BCC interleaving. Specifically, when BCC interleaving is performed, BCC coding is performed on the transceiver through the BCC encoder 211, and the BCC encoded codeword is parsed on a stream basis and then divided into symbols and transmitted to the BCC interleaver / LDPC tone mapper 213 BCC interleaving can be performed. The LDPC tone mapping also performs LDPC encoding through the LDPC encoder 212, parses the LDPC-encoded codeword on a stream-by-stream basis, and divides the LDPC-encoded codeword on a per symbol basis to perform interleaver / LDPC tone mapper 213 to perform LDPC tone mapping. The receiving end 220 can also combine the BCC deinterleaver and the LDPC tone mapper using the BCC deinterleaver / LDPC tone mapper 223.

3 is a diagram for explaining a plurality of piece memories according to an embodiment.

Referring to FIG. 3, a transmitting end and a receiving end supporting 20 MHz can use thirteen pieces of 26 piece memories 310. If the modulation scheme is 16-QAM, the fragment memory 310 may use up to the fourth address, and one address 311 of one fragment memory may include eight block data. Specifically, the combining method of the interleaver and the tone mapper can write thirteen piece memories in the order of the LLRs received from the detector in both the LDCP code and the BCC code. For example, in the order of mem0_0 (address 0), mem0_0 (address 1), mem0_0 (address 2), mem0_0 (address 2), mem0_1 You can write.

And, when the LDPC code is identified, the interleaver and tone mapper combination method can read 13 piece memories in the horizontal direction. For example, mem0_0 (address 0), mem0_1 (address 0), ..., mem0_12 (address 0), ..., mem0_0 (address 1), ..., mem0_12 You can read 13 pieces of memories in the order mem0_0 (address 3), ..., mem0_12 (address 3).

FIG. 4 is a diagram for explaining a process of reading a plurality of fragment memories in the case of a BCC code according to an embodiment.

Referring to FIG. 4, a transmitting end and a receiving end supporting 80 MHz can use 26 piece memories 410. If the modulation scheme is BPSK, one LLR can be stored per address, and in case of QPSK, two LLRs can be stored. In the case of 16-QAM, four LLRs can be stored. In the case of 64-QAM, six LLRs can be stored. In the case of 256-QAM, eight LLRs can be stored.

Specifically, the interleaver and tone mapper combination device can simultaneously read block data of address 0, which is the first address of the 26 pieces memories 410, when the BCC code is identified and the bandwidth is 80 MHz. Then, all the values corresponding to the first LLRs are collected, and then the 26 LLRs are combined and transmitted. Then, all the values corresponding to the second LLRs are collected, and the 26 LLRs can be bound and transmitted. The output block 420 may be generated by binding together the values corresponding to the eighth LLR. By repeating the above process from the second address to the last address, all of the pieces memory 410 can be read and BCC interleaving can be performed using the same.

5 is a block diagram illustrating an interleaver and a tone mapper combining apparatus using a memory structure according to an exemplary embodiment of the present invention.

Referring to FIG. 5, the code identification unit 510 may identify an LDPC code or a BCC code.

In addition, the fragment memory storage 520 may store at least one LLR in a plurality of addresses of a plurality of fragment memories included in the transceiver.

In addition, the fragment memory read section 530 can read a plurality of fragment memories based on the identification result.

The contents of the interleaver and tone mapper combining apparatus using the memory structure according to the embodiment shown in FIG. 5 can be applied as they are in FIGS. 1 to 4, and therefore, detailed description will be omitted.

The method according to an embodiment may be implemented in the form of a program command that can be executed through various computer means and recorded in a computer-readable medium. The computer-readable medium may include program instructions, data files, data structures, and the like, alone or in combination. The program instructions to be recorded on the medium may be those specially designed and configured for the embodiments or may be available to those skilled in the art of computer software. Examples of computer-readable media include magnetic media such as hard disks, floppy disks and magnetic tape; optical media such as CD-ROMs and DVDs; magnetic media such as floppy disks; Magneto-optical media, and hardware devices specifically configured to store and execute program instructions such as ROM, RAM, flash memory, and the like. Examples of program instructions include machine language code such as those produced by a compiler, as well as high-level language code that can be executed by a computer using an interpreter or the like. The hardware devices described above may be configured to operate as one or more software modules to perform the operations of the embodiments, and vice versa.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. For example, it is to be understood that the techniques described may be performed in a different order than the described methods, and / or that components of the described systems, structures, devices, circuits, Lt; / RTI > or equivalents, even if it is replaced or replaced.

Therefore, other implementations, other embodiments, and equivalents to the claims are also within the scope of the following claims.

Claims (9)

Identifying a Low-Density Parity Check (LDPC) code or a Binary Convolution Coding (BCC) code;
At least one LLR (Log Likelihood Ratio) is stored in a plurality of addresses of a plurality of piece memories included in a transceiver, the plurality of piece memories supporting tone mapping for the LDPC code and interleaving for the BCC code. ; And
Reading the plurality of piece memories based on the identification result
Lt; / RTI >
Wherein storing the at least one LLR comprises:
Determining whether an Inverse Fast Fourier Transform (IFFT) output received by the receiver of the transceiver is a bit reversing order; And
Rearranging the at least one LLR stored in the plurality of addresses using a ROM table according to the determination result;
And combining the tone mapper with an interleaver using a memory structure. The method according to claim 1,
Wherein storing the at least one LLR comprises:
Storing the at least one LLR in a longitudinal direction from a first address of the first piece memory to an end address of the last piece memory of the plurality of piece memories. delete The method according to claim 1,
Wherein storing the at least one LLR comprises:
And applying the cyclic shift to store the at least one LLR in the plurality of addresses. The method according to claim 1,
Wherein the reading of the plurality of piece memories comprises:
And reading the plurality of piece memories in a horizontal direction. The method according to claim 1,
Wherein the reading of the plurality of piece memories comprises:
Simultaneously reading a plurality of block data from the plurality of fragment memories using any one of the plurality of addresses; And
Sequentially identifying values corresponding to each LLR based on at least one LLR included in each of the plurality of block data;
A method of combining an interleaver and a tone mapper using a memory structure comprising: The method according to claim 6,
Wherein the reading of the plurality of piece memories comprises:
Repeatedly reading the plurality of block data from the first address to the last address of the plurality of addresses at the same time and sequentially identifying values corresponding to the LLRs
And a tone mapper combining method using the memory structure. The method according to claim 1,
Wherein the number of the plurality of piece memories corresponds to a plurality of bandwidths. The method according to claim 1,
And the number of the at least one LLRs stored in any one of the plurality of addresses corresponds to a modulation scheme.

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