KR101800447B1 - Sense amplification circuit, output circuit, nonvolatile memory device, memory system and memory card having the same, and data outputting method thereof - Google Patents

Abstract

Here, an output circuit of a nonvolatile memory device is provided. The output circuit of the present invention includes page buffer latches for latching data read from memory cells, sub-data lines for receiving voltages corresponding to the latched data in response to latch addresses, A data line connecting the data lines; A reference data line on which a current path is formed during the sensing operation, and a sense amplifier circuit for differentially sensing the reference data line and the data line during the sensing operation and outputting data corresponding to the sensing result. The nonvolatile memory device according to the present invention can perform a data output operation at a high speed by outputting data by a differential sensing method. In addition, the nonvolatile memory device according to the present invention can reduce the area of the layout by differential sensing between the data lines and the corresponding reference data lines.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an amplifying circuit, an output circuit having the amplifying circuit, a nonvolatile memory device, a memory system, and a memory card, and a data output method thereof. BACKGROUND OF THE INVENTION METHOD THEREOF}

The present invention relates to an amplifier circuit, an output circuit having the same, a nonvolatile memory device, a memory system and a memory card, and a data output method thereof.

Semiconductor memory devices are typically the most essential microelectronic devices for digital logic designs such as computers and applications based on microprocessors ranging from satellites to consumer electronics technologies. Advances in semiconductor memory fabrication techniques, including process enhancements and technology development through scaling for high integration and high speed, can help establish performance criteria for other digital logic families.

Semiconductor memory devices are roughly divided into volatile semiconductor memory devices and nonvolatile semiconductor memory devices. The nonvolatile semiconductor memory device can store data even when the power is turned off. The data stored in the nonvolatile memory is either permanent or reprogrammable, depending on the memory fabrication technique. Non-volatile semiconductor memory devices are used for storage of programs and microcode in a wide range of applications such as computers, avionics, communications, and consumer electronics technology industries.

A representative example of a non-volatile memory device is a flash memory device. In recent years, as the demand for highly integrated memory devices has increased, multi-bit memory devices that store multi-bits in one memory cell have become popular.

It is an object of the present invention to provide a nonvolatile memory device that performs a data output operation at a high speed.

It is yet another object of the present invention to provide a nonvolatile memory device that reduces the area of the layout.

An output circuit of a non-volatile memory device according to an embodiment of the present invention includes: page buffer latches for latching data read from memory cells; Sub data lines receiving voltages corresponding to the latched data in response to latch addresses; A data line connecting the sub data lines in a sensing operation; A reference data line in which a current path is formed in the sensing operation; And a sense amplifier circuit for differentially sensing the reference data line and the data line during the sensing operation and outputting data corresponding to the sensing result.

In an embodiment, the apparatus further comprises a column selection circuit for sequentially connecting the sub data lines to the data lines in response to column addresses.

In an embodiment, the column selection circuit includes column select transistors for coupling each of the sub data lines to the data line in response to the column addresses.

In an embodiment, the reference data line has a load element corresponding to a load of the data line.

In an embodiment, the sense amplifier circuit may include: a precharger that precharges the reference data line and the data line; A current path generator for forming the current path on the reference data line after the reference data line and the data line are precharged; And a differential sense amplifier for sensing a voltage difference between the reference data line and the data line.

In an embodiment, the precharger includes at least one PMOS transistor for applying a power supply voltage to the reference data line and the data line in response to a precharge signal.

In an embodiment, the current path generator electrically connects the reference data line to a ground terminal during the sensing operation.

In one embodiment, the current path generator varies the voltage of the reference data line during the sensing operation.

In the embodiment, the current path generator may lower the voltage of the reference data line during the sensing operation, and when the latched data is data that lowers the voltage of the data line, the voltage of the reference data line falls The slope is smaller than the slope at which the voltage of the data line falls.

In an embodiment, the voltage change amount of the reference data line is smaller than the voltage change amount of the data line.

In an embodiment, the voltage change amount of the reference data line is a value between two voltage values corresponding to the latched data at the time of performing the sensing operation.

In an embodiment, the current path generator includes at least one current pass transistor having a gate to receive a trim code, the transistor being connected between the reference data line and the pass node; And a path forming transistor for connecting the pass node and the ground terminal in response to an inverted signal of the precharge signal.

In an embodiment, the trim code varies according to the address that determines the physical location of the page buffer.

In an embodiment, the trim code is implemented with at least one of an e-fuse, a laser fuse, an anti-fuse, and a register setting.

In an embodiment, the differential sense amplifier includes: a first PMOS transistor coupled between a power supply stage and an output node and having a gate coupled to the inverted output node; A second PMOS transistor connected between the power supply terminal and the inverting output node and having a gate connected to the output node; A first NMOS transistor coupled to the output node and a bias node, the first NMOS transistor having a gate coupled to the inverted output node; A second NMOS transistor connected to the inverting output node and the bias node and connected to the output node; And a third NMOS transistor for connecting the bias node and the ground terminal during the sensing operation.

A non-volatile memory device according to an embodiment of the present invention includes a memory cell array including at least one memory block having memory cells connected to bit lines; Page buffers for latching data read from memory cells corresponding to each of the bit lines; Sub data lines receiving voltages corresponding to data latched in the page buffers in response to latch addresses; A column selection circuit connecting the sub data lines and corresponding data lines in response to column addresses; And an output driver for outputting data by detecting a voltage difference between the data lines and corresponding reference data lines in a sensing operation, and a current path is formed in each of the reference data lines in the sensing operation.

In an embodiment, the at least one memory block is implemented in an all-bit line structure.

In an embodiment, at least one memory block is implemented with an even-odd bit line structure.

In an embodiment, each of the page buffers includes a page buffer latch, wherein even or odd bit lines of the bit lines are coupled to the one page buffer latch, and the page buffer latch is read Latches data read from a corresponding one of the memory cells during operation or latches data input from the outside during a program operation.

In an embodiment, each of the page buffers includes a first page buffer latch and a second page buffer latch, wherein the first page buffer latch is coupled to even ones of the bit lines, And latching data read from a corresponding one of the even bit lines, wherein the second page buffer latch is coupled to odd bit lines of the bit lines, And latches the data read from the memory cell.

In an embodiment, the sense amplification circuit includes a precharger that precharges the reference data lines and the data lines in response to a precharge signal; A current path generator for causing a predetermined current to flow in the reference data lines in response to an inversion signal of the precharge signal; And a differential sense amplifier for differential sensing the reference data lines and the data lines in response to the differential sense signal.

In one embodiment, one read cycle for outputting the latched data to each of the page buffers comprises a precharge period for precharging the reference data lines and the data lines, a precharge period for precharging the page buffers to the corresponding data lines And a sensing period for sensing a voltage difference between the developed data lines and the reference data lines.

In an exemplary embodiment, in the precharge period, a power supply voltage is applied to the reference data lines and the data lines in response to the precharge signal.

In an embodiment, in the development period, the sub data lines are connected to corresponding data lines in response to the column addresses, and in response to the latch addresses, the page buffers are connected to corresponding sub data lines And transmits the latched data.

In an embodiment, in the sensing period, a voltage difference between the data bit lines and corresponding reference data lines is sensed in response to the differential sensing signal.

In an embodiment, the data processing apparatus further includes an input / output buffer for temporarily storing the data output from the sense amplifier circuit or temporarily storing data input from the outside.

The embodiment may further include a randomization circuit for randomizing data input from the outside during an input operation or for demarcating the data output from the sense amplifier circuit during an output operation.

A data output method of a nonvolatile memory device according to an embodiment of the present invention includes: latching data of memory cells through corresponding bit lines; Transmitting voltages corresponding to the latched data to a data line; And sensing a voltage difference between the data line and the reference data line, wherein the sensing includes forming a current path in the reference data line.

In an embodiment, the step of latching data of the memory cells comprises: precharging the bit lines; And sensing a change in the precharged bit lines.

A memory system according to an embodiment of the present invention includes: a nonvolatile memory device; And a memory controller for controlling the nonvolatile memory device, wherein the nonvolatile memory device includes a plurality of data lines for sequentially transmitting voltages corresponding to data read in a read operation and corresponding reference data lines, And forms a current path on each of the reference data lines, and the output data is input to the memory controller.

A sense amplifier circuit according to an embodiment of the present invention includes a precharger that precharges a reference data line and a data line in response to a precharge signal; A current path generator for generating a current path in the reference data line in response to an inverted signal of the precharge signal; And a differential sense amplifier for sensing a voltage difference between the reference data line and the data line in response to a sense signal, wherein data to be sensed during a sensing operation is transmitted to the precharged data line, When the voltage of the data line is lowered, the slope at which the voltage of the reference data line is lowered is smaller than the slope at which the data line is lowered.

A data output method of a nonvolatile memory device according to an embodiment of the present invention includes: transmitting output data to a data line; Varying a voltage of a reference data line to generate a reference voltage having a predetermined slope; And differentially detecting a voltage difference between the reference voltage and the data line.

In one embodiment, the method further comprises applying a pre-charge voltage to the data line and the reference data line before output data is transmitted to the data line.

In another embodiment of the present invention, the step of varying the voltage of the reference data line may include a step of lowering the voltage of the reference data line when the output data falls the voltage of the data line, .

In one embodiment of the present invention, the step of varying the voltage of the reference data line includes the step of increasing the voltage of the reference data line when the output data increases the voltage of the data line, .

In an embodiment, the differential sensing further comprises discharging the data line and the reference data line.

Another non-volatile memory device according to an embodiment of the present invention includes a plurality of output units, each of the plurality of output units including: page buffer latches for latching data read from memory cells; Sub data lines receiving voltages corresponding to the latched data in response to latch addresses; A data line connecting the sub data lines in a sensing operation; A reference data line connected to at least one current sink activated in the sensing operation; And a sense amplifier circuit for differentially sensing the reference data line and the data line during the sensing operation and outputting data corresponding to the sensing result.

In an embodiment, data output from each of the plurality of output units is output to the outside via one input / output line.

In an embodiment, data output from at least two of the plurality of output units is output to the outside via one input / output line.

In one embodiment, the data processing apparatus further includes an input / output buffer that outputs data output from the sense amplifier circuit to the outside or receives data from the outside.

In one embodiment, the input / output buffer includes: the first input / output buffer operating in a single-ended transmission mode in response to a first transmission mode selection signal; And a second input / output buffer operating in a differential transmission mode in response to a second transmission mode selection signal.

In an embodiment, the apparatus further comprises a transmission mode selector for generating the first and second transmission mode selection signals.

In an embodiment, the transmission mode selector generates the first and second transmission mode selection signals according to a user or e-fuse setting.

A memory card according to an embodiment of the present invention includes at least one nonvolatile memory device for storing user data; A buffer memory device for temporarily storing data generated during operation; And a memory controller for controlling the at least one non-volatile memory device and the buffer memory device, the at least one non-volatile memory device comprising: page buffer latches for latching data read from the memory cells; Sub data lines receiving voltages corresponding to the latched data in response to latch addresses; A data line connecting the sub data lines in a sensing operation; A reference data line in which a current path is formed in the sensing operation; And a sense amplifier circuit for differentially sensing the reference data line and the data line during the sensing operation and outputting data corresponding to the sensing result.

The nonvolatile memory device according to the present invention can perform a data output operation at a high speed by outputting data by a differential sensing method.

The nonvolatile memory device according to the present invention can reduce the area of the layout by differential sensing between the data lines and the corresponding reference data lines.

1 is a block diagram illustrating a non-volatile memory device in accordance with an embodiment of the present invention.
FIG. 2 is a view showing a first embodiment of the memory block shown in FIG. 1. FIG.
FIG. 3 is a view showing a second embodiment of the memory block shown in FIG. 1. FIG.
FIG. 4 is a view showing a first embodiment of the output operation of the nonvolatile memory device shown in FIG. 1. FIG.
5 is a view showing a second embodiment of the output operation of the nonvolatile memory device shown in FIG.
FIG. 6 is a view showing an embodiment of the pre-charger shown in FIG.
FIG. 7 is a view showing an embodiment of the current path generator shown in FIG. 4. FIG.
8 is a timing chart for explaining the operation of the current path generator shown in FIG.
9 is a diagram showing an embodiment of the differential sense amplifier shown in FIG.
10 is a timing chart showing a data output operation according to an embodiment of the present invention.
11 is a view showing another embodiment of the output operation of the nonvolatile memory device shown in FIG.
12 is a view showing still another embodiment of the output operation of the nonvolatile memory device shown in FIG.
13 is a flowchart illustrating a data output method according to an embodiment of the present invention.
14 is a view showing a second embodiment of a nonvolatile memory device according to an embodiment of the present invention.
15 is a view showing a third embodiment of a nonvolatile memory device according to an embodiment of the present invention.
16 is a view showing a fourth embodiment of a nonvolatile memory device according to an embodiment of the present invention.
FIG. 17 is a circuit diagram showing an equivalent circuit for any one of the memory blocks shown in FIG. 16. FIG.
18 is a block diagram illustrating a memory system in accordance with an embodiment of the present invention.
19 is a block diagram of a memory card according to an embodiment of the present invention.
20 is a block diagram of a Moving NAND according to an embodiment of the present invention.
21 is a block diagram of an SSD according to an embodiment of the present invention.
22 is a block diagram of a computing system having the SSD shown in FIG.
23 is a block diagram of an electronic apparatus having the SSD shown in FIG.
24 is a block diagram of a server system using the SSD shown in FIG.
25 is an exemplary illustration of a portable electronic device according to the present invention.

Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art can easily carry out the technical idea of the present invention.

A nonvolatile memory device according to an embodiment of the present invention may include a NAND flash memory, a vertical NAND flash memory, a NOR flash memory, a resistive random access memory (RRAM) , A phase change memory (PRAM), a magnetoresistive random access memory (MRAM), a ferroelectric random access memory (FRAM), a spin transfer random access memory (STT) -RAM) or the like. Hereinafter, the nonvolatile memory device will be referred to as a NAND flash memory device for convenience of explanation.

1 is a block diagram illustrating a non-volatile memory device in accordance with an embodiment of the present invention. 1, a non-volatile memory device 100 includes a memory cell array 110, a page buffer circuit 120, a column select (or Y-select) circuit 130, a sense amplifier circuit 140, And an input / output buffer 150.

The memory cell array 110 includes a plurality of memory blocks MB0 to MBi. Where i is a natural number. The plurality of memory blocks MB0 to MBi share the bit lines BL0 to BLn. Where n is a natural number. Each of the plurality of memory blocks MB0 to MBi includes a plurality of memory cells (not shown) for storing data.

The page buffer circuit 120 reads and temporarily stores data from memory cells corresponding to the bit lines BL0 to BLn in a selected memory block among the memory blocks MB0 to MBi during a read operation, And temporarily stores the data. The page buffer circuit 120 includes page buffers corresponding to each of the bit lines BL0 to BLn, though not shown.

Each of the page buffers includes a plurality of latches (not shown). Wherein at least one of the plurality of latches (in other words, the page buffer latch) is coupled to the corresponding sub data line SDL in response to a corresponding latch address LA.

Each of the page buffers also includes a precharge circuit (not shown) for precharging the corresponding bit line, and a sense circuit (not shown) for sensing data from the memory cell connected to the corresponding bit line. Here, the sensing circuit may be a voltage sensing circuit or a current sensing circuit.

A more detailed description of the page buffer circuit will be described in US Serial No. 7,379,333, filed by Samsung Electronics and incorporated by reference.

The column selection circuit 130 connects any one of the sub data lines SDL to the corresponding data lines DL in response to column addresses YA.

The sense amplifier circuit 140 differential senses the data lines DL and the reference data lines DLref in response to the differential sense signal DSS to generate a plurality of data IO < 7: 0 > ). Where each of the reference data lines DLref is connected to an equivalent load. Where the equivalent load 135 will have the same load as the load connected to each of the data lines DL (e.g., column select circuit 130, sub data line SDL, ....). For example, such loads will include resistors, capacitors, reactors, and the like.

In an embodiment, each of the reference data lines DLref will be implemented with the same length as the corresponding data lines DL.

Further, the reference data lines DLref are formed by the sense amplification circuit 140 during the sensing operation. Hereinafter, the formation of the current path for convenience of explanation will be described as meaning that each of the reference data lines DLref is electrically connected to the ground terminal. If each of the reference data lines DLref is in the precharged state, the voltage of each of the reference data lines DLref begins to fall because a current path is formed in the sensing operation. In other words, each of the reference data lines DLref falls from the precharge voltage to a predetermined voltage in the sensing operation. Here, the predetermined voltage may be half of the maximum value at which the voltage of the data lines DLref may fall. For example, the data lines DLref may drop to the ground voltage from the maximum supply voltage.

In another embodiment, each of the reference data lines DLref may be electrically coupled to a voltage terminal having a voltage higher than a voltage precharged to the reference data lines DLref and the data lines DL during a sensing operation .

The input / output buffer 150 receives data I0 <7: 0> output from the sense amplifier circuit 140 during a read operation and outputs the data I0 <7: 0> to the outside, To the latch circuit 140.

The nonvolatile memory device 100 according to the embodiment of the present invention can perform a high-speed data sensing operation by differential sensing data.

In addition, the nonvolatile memory device 100 according to the embodiment of the present invention can largely reduce the area of the layout by differential sensing using the reference data lines DLref connected to the equivalent load 135.

FIG. 2 is a view showing a first embodiment of the memory block shown in FIG. 1. FIG. Referring to FIG. 2, the memory block MBj (j is any integer from 0 to i) includes a plurality of cell strings. Each of the cell strings includes a string selection transistor SST connected to a string selection line SSL and a plurality of memory cells MC0 to MCn connected to a plurality of word lines WL0 to WLm, MCm, and a ground selection line GST connected to a ground selection line GSL.

The string selection transistor SST is connected to a plurality of bit lines BL0 to BLn and the ground selection transistor GST is connected to a common source line CSL. Here, the common source line GSL can receive a ground voltage or a CSL voltage (e.g., a power supply voltage) from a CSL driver (not shown).

Each of the plurality of memory cells MC0 to MCm stores 1-bit data or multi-bit data.

The memory block MBj shown in FIG. 2 is implemented with an all bitline architecture. In the embodiment, all bit lines (BL0 to BLn, n are natural numbers) can be selected at the same time during a read or program operation. However, the bit lines of the present invention do not necessarily have to be selected at the same time during a read operation or a program operation.

A more detailed description of the all-bit line structure will be described in US Serial No. 7,379,333, filed by Samsung Electronics and incorporated by reference.

FIG. 3 is a view showing a second embodiment of the memory block shown in FIG. 1. FIG. Referring to FIG. 3, the memory block MBj_1 (j is any integer from 0 to i) includes even bit lines BLe0 to BLen and odd bit lines BLo0 to BLon. The memory block MBk shown in FIG. 3 is implemented with an even-odd bitline architecture. In an embodiment, even bit lines BLe0 to BLen may be selected first and odd bit lines BLo0 to BLon may be selected later during a read or program operation. In other embodiments, odd bit lines (BLo0-BLon) may be selected first and even bit lines (BLe0-BLen) may be selected later during a read or program operation.

A more detailed description of the Ibn-aOD bitline structure will be given in US registration number US 7,379,333, filed by Samsung Electronics and incorporated by reference.

FIG. 4 is a diagram showing a first embodiment of the output operation of the nonvolatile memory device 100 shown in FIG. In the following, only the data sensing method of the output operation (or the read operation) will be described for convenience of explanation. In the output operation, the page buffer circuit 120, the column selection circuit 130, and the sense amplification circuit 140 shown in FIG. 1 will be referred to as an output circuit. Here, the output circuit includes a plurality of output units OPTU0 to OPTU7, and each of the output units OPTU0 to OPTU7 outputs data (I0 <0> to IO <7>) by differential detection of data in the page buffer do. Here, the respective data IO <0> to IO <7> are outputted to the outside through the input / output data lines.

It is to be understood by those skilled in the art that although the number of output units OPTU0 to OPTU7 is limited to eight for convenience of explanation, it is to be understood that the number of output units of the present invention need not be limited.

The first output unit OPTU0 will be described below.

The page buffer circuit unit 120_0 includes a plurality of page buffers (PB0 to PBp + q, p and q are integers of one or more). (SDL0 to SDLr, r is an integer equal to or greater than one) corresponding to a predetermined number of the plurality of page buffers (PB0 to PBp + q). For example, the page buffers PB0 to PBp are connected to the first sub data line SDL0, and the page buffers PBq to PBp + q are connected to the rth sub data line SDLr. The page buffer circuit 120 shown in FIG. 1 is composed of a plurality of page buffer circuit units.

Each of the page buffers PB0 to PBp + q includes a page buffer latch CLAT, a first NMOS transistor NM1, and a second NMOS transistor NM2. Hereinafter, for convenience of description, the first page buffer PB0 connected to the first bit line BL0 will be described. One end of the page buffer latch CLAT is connected to the first bit line BL0 in response to the bit line select signal BLS and the other end is connected to the gate of the first NMOS transistor NM1. And includes a first NMOS transistor NM1 and a second NMOS transistor NM2 connected in series between the ground and the first sub data line SDL0. Here, the first latch address (LA < 0 >) is input to the gate of the second NMOS transistor NM2. That is, in response to the first latch address LA < 0 >, the data of the page buffer latch CLAT is transferred to the first sub data line SDL0.

In FIG. 4, one cache latch (CLAT, hereinafter referred to as "page buffer latch") is shown in each of page buffers (PB0 to PBp + q) for convenience of explanation. Although not shown, each of the page buffers PB0 to PBp + q of the present invention includes a plurality of latches in addition to a page buffer latch (CLAT).

The column selection circuit unit 130_0 includes a plurality of column selection transistors YST0 to YSTr. Each of the column select transistors YST0 to YSTr is connected between the corresponding sub data lines SDL0 to SDLr and the data line DL0. Here, each of the gates of the column select transistors YST0 to YSTr receives corresponding column addresses (YA <0> to YA <r>). Thus, the plurality of sub data lines SDL0 to SDLr may be sequentially connected to the first data line DL0 in response to the column addresses YA <0> to YA <r>.

The sense amplifier circuit unit 140_0 includes a precharger 141, a current path generator 142, and a differential sense amplifier 143. [ The sense amplifier circuit unit 140_0 outputs the data IO < 0 > by differential sensing the data latched in the page buffers PB0 to PBp + q in response to the differential sense signal DSS. Here, the data I0 < 0 > will be output to the outside through the corresponding input / output data line. On the other hand, the sense amplifier circuit 140 shown in FIG. 1 includes a plurality of sense amplifier circuit units.

The precharger 141 is connected between the data line DL0 and the reference data line DLref0 and is responsive to the precharge signal PS when sensing data latched in the page buffers PB0 to PBp + Thereby precharging the data line DL0 and the reference data line DLref0. In the embodiment, the data line DL0 and the reference data line DLref0 can be precharged to the power supply voltage.

In an embodiment, the reference data line DLref0 is connected to an equivalent load 135_0. Here, the equivalent load 135_0 will be implemented (e.g., equally) to correspond to the load connected to the data line DL. In an embodiment, the equivalent load 135_0 may be implemented as a transistor as shown in FIG.

The current path generator 142 forms a current path in the reference data line DLref0 when sensing the data lines DL0 and DLref0. Current path generator 142 is inactive when precharging reference data line DLref0 and data line DL0 and active when sensing data on data line DL0. That is, the current path generator 142 blocks the current path of the reference data line DLref0 when precharging the data lines DL0 and DLref0, and the current path of the precharged reference data line DLref0 in the sensing operation .

In particular, the current path generator 142 forms a current path so that the ratio of the voltage variation of the data line DL0 to the voltage variation of the reference data line DLref0 is maintained at a predetermined value during the sensing operation. For example, the current path generator 142 may be implemented so that the amount of change of the reference data line DLref0 is smaller than the amount of change of the data line DL0. In particular, the amount of change of the reference data line DLref0 can be realized to be half the amount of change of the data line DL0. That is, the current path generator 142 may be implemented such that a voltage change amount is generated according to the following equation.

Here, V _DLref is a voltage variation of the reference data line (DLref0), V _{DL _ max} is the maximum voltage of the data line (DL0), _{DL _} V _min is the minimum voltage of the data line (DL0).

The current path generator 142 constantly adjusts the voltage of the reference data line DLref0 irrespective of the voltage of the data line DLref0 (in other words, regardless of the data latched in the page buffers PB0 to PBp + q) Change / change (rise or fall). That is, the current path generator 142 lowers the voltage of the reference data line DLref0 constantly regardless of the voltage of the data line DLref0 in the sensing operation.

In an embodiment, current path generator 142 may be implemented with at least one current sink that is activated during a sensing operation.

In another embodiment, current path generator 142 may be implemented with at least one current source that is activated during a sensing operation.

The differential sense amplifier 143 outputs data IO < 0 > by differential sensing between the data line DL0 and the reference data line DLref0 in response to the differential detection signal DSS. That is, the differential sense amplifier 143 determines whether the latched data is '0' or '1' by detecting the voltage difference between the data line DLref0 and the falling voltage of the reference data line DLref0 during the sensing operation . The details of the differential sense amplifier 143, on the other hand, will be described in the US registration number US 6,574,129, which is incorporated herein by reference.

Although the first output unit OPTU0 has been described above, the remaining output units OPTU1 to OPTU7 will be implemented to have the same function or operation. Each of the output units OPTU0 to OPTU7 according to the embodiment of the present invention outputs data by differential sensing between one data line and one reference data line.

In Fig. 4, data output from one of the output units OPTU0 to OPTU7 to one input / output data line is output. However, it will be understood by those skilled in the art that the present invention is not limited thereto. Data outputted to one input / output data line from at least two output units may be output.

5 is a diagram showing a second embodiment of the output operation of the nonvolatile memory device 100 shown in FIG. Referring to FIG. 5, the first output unit OPTU0 through tth output unit OPTUt, where t is a natural number, outputs data IO <i> output to one input / output line. The description of the first output unit OPTU0 will be omitted because it has been described with reference to FIG.

FIG. 6 is an exemplary view showing the pre-charger 141 shown in FIG. Referring to FIG. 6, the precharger 141 includes first, second, and third PMOS transistors PM1 to PM3. The first PMOS transistor PM1 is connected between the power supply terminal VDD and the data line DL and the second PMOS transistor PM2 is connected between the power supply terminal VDD and the reference data line DLref0 , And the third PMOS transistor PM3 is connected between the data line DL0 and the reference data line DLref0. The precharge signal PS is input to the gates of the first through third PMOS transistors PM1 through PM3. The precharger 141 applies the power supply voltage to the data line DL0 and the reference data line DLref0 in response to the precharge signal PS.

FIG. 7 is a diagram showing an embodiment of the current path generator 142 shown in FIG. Referring to FIG. 7, the current path generator 142 includes a plurality of current path transistors CPT0 to CPTs and a path forming transistor PDT.

Each of the plurality of current path transistors CPT0 to CPTs is connected between the reference data line DLref0 and the pass node ND. Here, the corresponding trim codes (TRM <0>, ..., TRM <s>) are input to the gates of the current pass transistors CPT0 to CPTs.

In an embodiment, the trim codes (TRM <0>, ..., TRM <s>) can be fixed.

In other embodiments, the trim codes (TRM <0>, ..., TRM <s>) may be variable. For example, the trim codes (TRM <0>, ..., TRM <s>) may vary depending on the address for selecting the memory block. Also, the trim codes (TRM <0>, ..., TRM <s>) may vary depending on the address that determines the physical location of the page buffer.

In practice, the trim codes (TRM <0>, ..., TRM <s>) may be used for e-fuses, laser fuses, anti- And a register setting.

The path forming transistor PDT is connected between the pass node ND and the ground terminal. Here, the precharge signal PS is input to the gate of the path forming transistor PDT. That is, the path forming transistor PDT is turned on in response to the precharge signal PS. For example, when the precharge signal PS is at the low level, the path forming transistor PDT is turned off, and when the precharge signal PS is at the high level, the path forming transistor PDT is turned on.

Consequently, the current path generator 142 generates the trim codes TRM <0>, ..., TRM <s> when the path forming transistor PDT is turned on (at the high level of the precharge signal PS) To provide a current path to the reference data line DLref0.

The current path generator 142 shown in FIG. 7 can be seen as a kind of current sink. Here, the current sink is activated in response to the precharge signal PS.

The current path generator 142 shown in Fig. 7 includes a plurality of current path transistors CPT0 to CPTs. However, it will be appreciated by those skilled in the art that the current path generator according to embodiments of the present invention need not necessarily be limited to include a plurality of current pass transistors. The current path generator according to an embodiment of the present invention may include at least one current pass transistor.

8 is a timing chart for explaining the operation of the current path generator 142 shown in FIG. 8, no current flows through the reference data line DLref0 when the precharge signal PS is at the low level and a current flows through the reference data line DLref0 when the precharge signal PS is at the high level .

FIG. 9 is a diagram showing an embodiment of the differential sense amplifier 143 shown in FIG. 9, the differential sense amplifier 143 includes first and second PMOS transistors P1 and P2, first through third NMOS transistors N1 through N3, first and second PMOS transistors N1 through N3, (TG1, TG2).

The first PMOS transistor P1 is connected between the power supply terminal VDD and the data node DN and the second PMOS transistor P2 is connected between the power supply terminal VDD and the inverted data node DNb . Here, the gate of the first PMOS transistor P1 is connected to the inverted data node DNb, and the gate of the second PMOS transistor P2 is connected to the data node DN. Here, the data IO < 0 > is output from the data node DN. In another embodiment, data IO < 0 > may be output at the inverted data node DNb.

The first NMOS transistor N1 is connected between the data node DN and the bias node BN and the second NMOS transistor N2 is connected between the inverted data node DNb and the bias node BN , And the third NMOS transistor N3 is connected between the bias node BN and the ground terminal. The gate of the first NMOS transistor N1 is connected to the inverted data node DNb and the gate of the second NMOS transistor N2 is connected to the data node DN. Receives the differential detection signal DSS.

The first transgate TG1 electrically couples the data line DL0 to the data node DN in response to the differential sense signal DSS and the second transgate TG2 responds to the differential sense signal DSS Thereby electrically connecting the reference data line DLref0 to the inverted data node DNb.

The differential sense amplifier 143 senses the voltage difference between the data line DL0 and the reference data line DLref0 in response to the differential detection signal DSS and outputs the sensed result as data.

10 is a timing chart showing a data output operation according to an embodiment of the present invention. In Fig. 10, the operation of outputting data latched in the first page buffer PB0 and the second page buffer PB1 is shown for convenience of explanation. 4 to 9, the read cycle t0 is divided into a precharge period t1, a development period t2, and a sensing period t3. In an embodiment, the precharge period t1 may be 5 ns, the advance period t2 may be 3 ns, and the sensing period t3 may be 2 ns. However, the times corresponding to the precharging interval t1, the advance interval t2, and the sensing interval t3 of the present invention are not limited thereto.

First, the operation of outputting the latched data to the page buffer latch (CLAT) of the first page buffer PB0 will be described.

In the precharge period t1, the data lines DL0 and DLref0 are precharged in response to the low level of the precharge signal PS. Here, the data lines DL0 and DLref0 may be precharged to the power source voltage.

The first latch address LA < 0 > and the first column address YA < 0 > are at a high level in the advance interval t2. The page buffer latch CLAT of the first page buffer PB0 is connected to the sub data line SDL0 in response to the first latch address LA <0> of high level. Thus, a voltage corresponding to the data latched in the page buffer latch (CLAT) of the first page buffer PB0 is applied to the sub data line SDL0. For convenience of explanation, it is assumed that the data latched in the page buffer latch CLAT of the first page buffer PB0 is data '1', and the voltage corresponding to the data '1' is the ground voltage.

Further, the sub data line SDL0 is connected to the data line DL0 in response to the high level column address YA <0>. Since the voltage of the sub data line SDL0 is the ground voltage and the voltage of the data line DL0 is the power supply voltage, the voltage of the data line DL0 starts to fall. At the same time, since the current path is formed in the reference data line DLref0, the voltage of the reference data line DLref0 also falls. At this time, since the reference data line DLref0 is implemented so that half of the value of the current flowing through the data line DL0 flows, the slope of the voltage of the reference data line DLref0 falls is the voltage of the data line DL0 falls Lt; / RTI &gt; Accordingly, the voltage of the reference data line DLref0 is higher than the voltage of the data line DL0 at the time t2 in the advanced period. That is, the voltage difference Vdiff obtained by subtracting the voltage of the data line DL0 from the voltage of the reference data line DLref0 is positive voltage.

The first latch address LA <0> and the first column address YA <0> maintain the high level and the data sensing signal DSS becomes the high level in the sensing period t3. The differential sense amplifier 143 senses the voltage difference Vdiff between the reference data line DLref0 and the data line DL0 in response to the high level data sense signal DSS. At this time, since the voltage difference Vdiff is a positive voltage, a voltage (e.g., a ground voltage) corresponding to data '1' is output to the data node DN.

Thereafter, the data latched in the page buffer latch CLAT of the second page buffer PB1 will be output in a similar manner.

In the precharge period t1, the data lines DL0 and DLref0 are precharged in response to the low level of the precharge signal PS. Here, the data lines DL0 and DLref0 may be precharged to the power source voltage.

The second latch address LA < 1 > and the first column address YA < 0 > in the rise interval t2 are at a high level.

The page buffer latch CLAT of the second page buffer PB1 is connected to the sub data line SDL0 in response to the second latch address LA <1> of the high level. Thus, a voltage corresponding to the data latched in the page buffer latch (CLAT) of the second page buffer PB1 is applied to the sub data line SDL0. Hereinafter, for convenience of explanation, it is assumed that data latched in the page buffer latch CLAT of the second page buffer PB1 is data '0', and that a voltage corresponding to data '0' is a power supply voltage.

Further, the sub data line SDL0 is connected to the data line DL0 in response to the high level column address YA <0>. Since the voltage of the sub data line SDL0 is the power supply voltage and the voltage of the data line DL0 is the power supply voltage, the voltage of the data line DL0 is kept constant. At the same time, since the current path is formed in the reference data line DLref0, the voltage of the reference data line DLref0 falls. Therefore, the voltage of the reference data line DLref0 is lower than the voltage of the data line DL0 at the time t2 in the advanced period. That is, the voltage difference Vdiff obtained by subtracting the voltage of the data line DL0 from the voltage of the reference data line DLref0 is a negative voltage.

The advance interval t3 can be regarded as a period in which the reference voltage of the reference data line DLref0 is discharged at a predetermined slope. Here, the predetermined slope is a value larger than the slope at which the voltage of the data line DL0 falls. In this respect, the current path former 142 shown in FIG. 6 may be regarded as a kind of discharge circuit.

The second latch address LA <1> and the first column address YA <0> maintain the high level and the data sensing signal DSS becomes the high level in the sensing period t3. The differential sense amplifier 143 senses the voltage difference Vdiff between the reference data line DLref0 and the data line DL0 in response to the high level data sense signal DSS. At this time, since the voltage difference Vdiff is a negative voltage, a voltage (for example, a power supply voltage) corresponding to data '0' is output to the data node DN.

The data output method of the nonvolatile memory device according to the embodiment of the present invention can quickly detect the data according to whether the voltage difference Vdiff between the reference data line DLref0 and the data line DL0 is a positive voltage or a negative voltage can do.

The data output method shown in Fig. 10 includes precharging the reference data line DLref0 and the data line DL0. It will be appreciated by those skilled in the art, however, that the data output method of the present invention need not include precharging the reference data line and the data line. The present invention can detect and output data without precharging operation of the reference data line and the data line. For example, when the output data raises the voltage of the data line, the data output method will be implemented so that the slope at which the voltage of the reference data line rises is smaller than the slope at which the data line rises. Accordingly, data transmitted to the data line during the sensing operation can be detected and output. Thereafter, the reference data line and the data line will be discharged for the next cycle of data output.

11 is a diagram showing another embodiment of the output operation of the nonvolatile memory device 100 shown in FIG. Referring to FIG. 11, the output operation is divided into a data output operation corresponding to an even bit line and a data output operation corresponding to an odd bit line, as compared with the output operation shown in FIG. For example, the data output operation may be performed by connecting an even bit line to a corresponding page buffer latch in response to an even bit line select signal (BLSe), or by connecting an odd bit line to a corresponding page buffer in response to an odd bit line select signal (BLSo) Connect to the latch. In addition, the output operation will be performed similarly to the output operation shown in Figs.

As shown in FIG. 11, each of the page buffers is connected to one page buffer latch (CLAT), one even bit line and the corresponding odd bit line. However, the page buffers of the present invention are not necessarily limited thereto. Each of the page buffers of the present invention may include a page buffer latch for an even bit line and a page buffer latch for an odd bit line.

12 is a diagram showing another embodiment of the output operation of the nonvolatile memory device 100 shown in FIG. Referring to FIG. 12, each of the page buffers includes a first page buffer latch CLAT1 for an even bit line and a second page buffer latch CLAT2 for an odd bit line. For example, the data output operation may be performed by connecting an even bit line to a corresponding first page buffer latch CLAT1 in response to an even bit line select signal BLSe, or by connecting an odd bit line &lt; RTI ID = 0.0 &gt; To the corresponding second page buffer latch CLAT2. In addition, the output operation will be performed similarly to the output operation shown in Figs.

13 is a flowchart illustrating a data output method of a nonvolatile memory device according to an embodiment of the present invention. 1 to 13, a data output method of the nonvolatile memory device is as follows.

The data of the memory cells connected to the selected word line at the time of the data output operation (or at the time of the read operation) is latched in the page buffer latches of each of the page buffers through the corresponding bit lines BL at step S110.

The voltages corresponding to the data latched in the page buffer latches are transferred to the sub data lines SDL in response to latch addresses LA <0>, LA <1>, ...., (SDL) is connected to the data line DL in response to the column addresses YA (S120). Thereby, the data stored in the page buffer latches is transferred to the data line DL.

The voltage difference between the reference data line DLref and the data line DL is sensed in response to the data sense signal DSS (S130). Here, the reference data line DL forms a current path during the sensing operation. On the other hand, the sensed data will be temporarily buffered and then output to the outside.

A data output method according to an embodiment of the present invention is a method of outputting page buffers by connecting the page buffers to which the data is latched to the data lines DL and detecting a voltage difference between the reference data lines DLref and the data lines DL And outputs the data.

The nonvolatile memory device according to an embodiment of the present invention may randomize and store input data, and may output the stored data in a random manner.

14 is a diagram illustrating a second embodiment of a non-volatile memory device 200 according to an embodiment of the present invention. Referring to Fig. 14, the non-volatile memory device 200 further includes a randomization circuit 235 as compared to the non-volatile memory device 100 shown in Fig. Here, the randomizing circuit 235 randomizes the data (DATA) input from the input / output circuit 240 during the input operation, and derandomizes the data output from the sense amplifier circuit 130 during the output operation. Other components will perform the same configuration and operation as the components shown in FIG.

Further details of the randomization circuit 235 will be described in U.S. Publication Nos. US 2010-0229001, US 2010-0229007, and US 2010-0259983 filed by Samsung Electronics and incorporated by reference.

The nonvolatile memory device 200 according to the embodiment of the present invention can improve the reliability of data by randomizing data at the time of data input / output.

The sense amplifier circuit according to the embodiment of the present invention is applicable to SDR (Single Data Rate) NAND or DDR (Double Data Rate) NAND. SDR NAND is disclosed in ONFI's home page (http://onfi.org/specifications/) and will be incorporated by reference in this application. Further, details of the DDR NAND are disclosed in the Samsung Electronics homepage (http://www.samsung.com/global/business/semiconductor/products/flash/Products_Toggle_DDR_NANDFlash.html) Will be.

The nonvolatile memory device according to an embodiment of the present invention may be selectively used in either a single-ended transfer mode suitable for SDR NAND or a differential transfer mode suitable for DDR NAND in a data input / output operation have.

15 is a diagram illustrating a third embodiment of a non-volatile memory device 300 according to an embodiment of the present invention. 15, the non-volatile memory device 300 includes a memory cell array 110, a page buffer circuit 120, a column selection circuit 130, a sense amplifier circuit 140, an input / output buffer 350, And a mode selector 360. Here, the memory cell array 110, the page buffer circuit 120, the column selection circuit 130, and the sense amplification circuit 140 will be implemented to have the same function or operation as those shown in FIG.

The input / output buffer 350 receives data output from the sense amplifier circuit 140 and outputs the data to the outside, or receives data from the outside and outputs the data to the data lines DL. The input / output buffer 350 includes a single-ended input / output buffer 351 and a differential input / output buffer 352.

The single-ended input / output buffer 351 inputs and outputs data in a single-ended transmission mode in response to the first transmission mode selection signal.

The differential input / output buffer 352 inputs and outputs data in the differential transmission mode in response to the second transmission mode selection signal.

The transmission mode selector 360 generates first and second transmission mode selection signals. In an embodiment, the transmission mode selector 360 may be implemented to generate first and second transmission mode selection signals in accordance with user or e-fuse (or register) settings.

The details of selectively inputting / outputting data in either the single-ended transmission mode or the differential transmission mode will be described in U.S. Patent Application No. 2008/0273623, filed by Samsung Electronics and incorporated herein by reference.

The nonvolatile memory device 300 according to the embodiment of the present invention can apply both a single-ended transfer mode and a differential transfer mode at data input / output.

The present invention is also applicable to a vertical semiconductor memory device (or 3D or VNAND). 16 is a view showing a fourth embodiment of a nonvolatile memory device according to an embodiment of the present invention. 16, a non-volatile memory device 400 includes a memory cell array 410, a driver 420, an input / output circuit 430, and control logic 440.

The memory cell array 410 includes a plurality of memory blocks BLK1 to BLKz. Each of the memory blocks BLK1 to BLKz includes a plurality of memory cells. Each of the memory blocks BLK1 to BLKz has a vertical structure (or a three-dimensional structure).

In the embodiment, each of the memory blocks BLK1 to BLKz includes structures extended along the first to third directions. Further, in the embodiment, each of the memory blocks BLK1 to BLKz includes a plurality of vertical strings NS extending along the second direction. Also, in the embodiment, each of the memory blocks BLK1 to BLKz includes a plurality of vertical strings NS along the first and third directions. Wherein each of the first to third directions are perpendicular to each other.

Each of the vertical strings NS includes one bit line BL, at least one string select line SSL, at least one ground select line GSL, one word line WL, Line CSL. That is, each of the memory blocks BLK1 to BLKz includes a plurality of bit lines BL, a plurality of string selection lines SSL. A plurality of ground selection lines GSL, a plurality of word lines WL, and a plurality of common source lines CSL.

The driver 420 is connected to the memory cell array 210 through a plurality of word lines WL. Driver 420 is implemented to operate in response to control of control logic 440. [ The driver 420 receives an address ADDR from the outside.

The driver 420 is implemented to decode the input address ADDR. Using the decoded address, the driver 420 selects one of the plurality of word lines WL. Driver 420 is implemented to apply voltages to selected and unselected word lines. In an embodiment, during a program operation, a read operation, or an erase operation, the driver 420 may apply a program voltage associated with the program operation, a read voltage associated with the read operation, or an erase voltage associated with the erase operation to the word lines WL . The driver 420 includes a word line driver 421, a select line driver 422, and a common source line driver 4223.

The input / output circuit 430 is connected to the memory cell array 410 through a plurality of bit lines BL. The input / output circuit 430 operates in response to control of the control logic 440. The input / output circuit 430 is implemented to select a plurality of bit lines BL.

In the embodiment, the input / output circuit 430 receives data (DATA) from the outside, randomizes the input data (DATA), and stores the randomized data (DATA) in the memory cell array 410. The input / output circuit 430 reads data (DATA) from the memory cell array 410 and di-randomizes or bypasses the read data (DATA).

The input / output circuit 430 may read data from the first storage area of the memory cell array 410 and store the read data in the second storage area of the memory cell array 410. In an embodiment, the input / output circuit 430 is implemented to perform a copy-back operation.

In an embodiment, the input / output circuit 430 includes well known components such as a page buffer (or page register), a column select circuit, a data buffer, and the like. In another embodiment, the input / output circuit 430 may include well known components such as a sense amplifier, a write driver, a column select circuit, a data buffer, and the like.

The control logic 440 is implemented to control all operations of the non-volatile memory device 400. The control logic 440 operates in response to externally transmitted control signals CTRL.

The details of the vertical type semiconductor memory device are disclosed in U.S. Publication Nos. US 2009-0306583, US 2010-0078701, US 2010-0117141, US 2010-0140685, US 2010-02135527, US 2010-0224929, US 2010-0315875, US 2010-0322000, US 2011-0013458, US 2011-0018036.

17 is a circuit diagram showing an equivalent circuit for any one of the memory blocks BLKi shown in Fig. 16 and 17, there are vertical strings NS11 to NS31 between the first bit line BL1 and the common source line CSL. The first bit line BL1 is extended in the third direction Lt; / RTI &gt; There are vertical strings NS12, NS22, and NS32 between the second bit line BL2 and the common source line CSL. And the second bit line BL2 corresponds to the conductive material extending in the third direction. Between the third bit line BL3 and the common source line CSL, the vertical strings NS13, NS23 and NS33 exist. And the third bit line BL3 corresponds to the conductive material extending in the third direction.

The string selection transistor SST of each vertical string NS is connected to the corresponding bit line BL. The ground selection transistor GST of each vertical string NS is connected to the common source line CSL. The memory cells MC are present between the string selection transistor SST and the ground selection transistor GST of each vertical string NS.

In the following, vertical strings NS are defined in units of rows and columns. Vertical strings NS connected in common to one bit line form one column. In the embodiment, the vertical strings NS11 to NS31 connected to the first bit line BL1 correspond to the first column. The vertical strings NS12 to NS32 connected to the second bit line BL2 correspond to the second column. The vertical strings NS13 to NS33 connected to the third bit line BL3 correspond to the third column.

Vertical strings NS connected to one string selection line SSL form one row. In the embodiment, the vertical strings NS11 to NS13 connected to the first string selection line SSL1 form a first row. And the vertical strings NS21 to NS23 connected to the second string selection line SSL2 form the second row. The vertical strings NS31 to NS33 connected to the third string selection line SSL3 form the third row.

In each vertical string NS, a height is defined. In the embodiment, in each vertical string NS, the height of the memory cell MC1 adjacent to the ground selection transistor GST is one. In each vertical string NS, the height of the memory cell increases as the string selection transistor SST is adjacent to the string selection transistor SST. In each vertical string NS, the height of the memory cell MC7 adjacent to the string selection transistor SST is seven.

Vertical strings NS in the same row share a string selection line (SSL). Vertical strings NS of different rows are connected to different string select lines SSL. The memory cells at the same height of the vertical strings NS in the same row share the word lines. At the same height, the word lines WL of the vertical strings NS of the different rows are connected in common. In an embodiment, the word lines WL may be connected in common in a layer to which conductive materials extending in a first direction are applied. In an embodiment, the conductive materials extending in the first direction may be connected to the upper layer through the contacts. The conductive materials extending in the first direction in the upper layer may be connected in common.

Vertical strings NS in the same row share the ground selection line GSL. Vertical strings NS of different rows are connected to different ground selection lines GSL.

The common source line CSL is connected in common to the vertical strings NS. In an embodiment, in the active region on the substrate, the first through fourth doped regions may be connected. In an embodiment, the first through fourth doped regions may be connected to the upper layer through a contact. In the upper layer, the first to fourth doped regions may be connected in common.

As shown in Fig. 17, the word lines WL having the same depth are connected in common. Thus, when a specific word line WL is selected, all the vertical strings NS connected to a specific word line WL are selected. Vertical strings NS of different rows are connected to different string select lines SSL. Therefore, by selecting the string selection lines SSL1 to SSL3, the vertical strings NS of the unselected rows among the vertical strings NS connected to the same word line WL are selected from the bit lines BL1 to BL3 Can be separated. That is, by selecting the string selection lines SSL1 to SSL3, a row of vertical strings NS can be selected. Then, by selecting the bit lines BL1 to BL3, the vertical strings NS of the selected row can be selected in units of columns.

1 to 17, the sense amplifier circuit is described as being used in a non-volatile memory device. However, it will be understood by those skilled in the art that it is not necessary to limit the sense amplification circuit according to the embodiment of the present invention to be used only for a nonvolatile memory device. The sense amplifier circuit according to the embodiment of the present invention is also applicable to a volatile memory device.

18 to 25 show various applications of the nonvolatile memory device according to the embodiment of the present invention.

18 is a block diagram illustrating a memory system in accordance with an embodiment of the present invention. 18, the memory system 1000 includes a non-volatile memory device 1100 and a memory controller 1200. The non-

The non-volatile memory device 1100 includes the non-volatile memory device 100 shown in Fig. 1, the non-volatile memory device 200 shown in Fig. 14, the non-volatile memory device 300 shown in Fig. 15, Volatile memory device 400 shown in FIG. 4A.

The memory controller 1200 includes at least one central processing unit 1210, a buffer memory 1220, an error correction circuit 1230, a ROM 1240, a host interface 1250, and a memory interface 1260. The memory system 1000 of the present invention is applicable to PPN (Perfect Page New).

A more detailed description of the memory system will be described in U.S. Publication No. US 2010-0082890, filed by Samsung Electronics and incorporated by reference.

19 is a block diagram of a memory card according to an embodiment of the present invention. 19, memory card 2000 includes at least one flash memory device 2100, a buffer memory device 2200, and a memory controller 2300 that controls them.

The flash memory device 2100 includes the nonvolatile memory device 100 shown in Figure 1, the nonvolatile memory device 200 shown in Figure 14, the nonvolatile memory device 300 shown in Figure 15, (Non-volatile memory device 400).

The buffer memory device 2200 is a device for temporarily storing data generated during operation of the memory card 2000. The buffer memory device 2200 may be implemented as a DRAM or an SRAM.

The memory controller 2300 is connected between the host and the flash memory 2100. In response to a request from the host, the memory controller 2300 accesses the flash memory device 2100.

The memory controller 2300 includes at least one microprocessor 2310, a host interface 2320, and a flash interface 2330.

The microprocessor 2310 is implemented to operate firmware. The host interface 2320 interfaces with the host via a card (e.g., MMC) protocol for exchanging data between the host and the flash interface 2330.

Such a memory card 2000 can be applied to a multimedia card (MMC), a security digital (SD), a miniSD, a memory stick, a SmartMedia, a TransFlash card, .

A more detailed description of the memory card 2000 will be described in U.S. Publication No. US 2010-0306583, filed by Samsung Electronics and incorporated by reference.

20 is a block diagram of a Moving NAND according to an embodiment of the present invention. Referring to FIG. 20, a Moving NAND 3000 may include a NAND flash memory device 3100 and a controller 3200. MOBYNAND (3000) supports MMC 4.4 (in other words, eMMC) specification.

The NAND flash memory device 3100 may include single NAND flash memory devices. In the embodiment, single NAND flash memory devices may be stacked in one package (for example, FBGA, Fine-pitch Ball Grid Array). The single NAND flash memory device may be a nonvolatile memory device The nonvolatile memory device 300 shown in FIG. 15 and the nonvolatile memory device 400 shown in FIG. 16 have the same configuration or operation as the nonvolatile memory device 100 shown in FIG. 14, the nonvolatile memory device 200 shown in FIG. 14, (Function).

The controller 3200 includes at least one controller core 3210, a host interface 3220, and a NAND interface 3230. The controller core 3210 controls the overall operation of the mobile NAND 3000. The host interface 3220 performs MMC (Multi Media Card) interfacing with the controller 3210 and the host. The NAND interface 3230 performs the interfacing of the NAND flash memory device 3100 and the controller 3200.

The mobile NAND 3000 receives the power supply voltages Vcc and Vccq from the host. Here, the power supply voltage Vcc (3.3V) is supplied to the NAND flash memory device 3100 and the NAND interface 3230, and the power supply voltage Vccq (1.8V / 3.3V) is supplied to the controller 3200.

The Moving NAND 3000 according to the embodiment of the present invention is advantageous not only for storing a large amount of data, but also has improved read operation characteristics. The MOBYNAND 3000 according to the present invention can be applied to mobile products (for example, Galaxy S, iPhone, etc.) which require small size and low power.

Meanwhile, the present invention is applicable to a solid state drive (SSD).

21 is a block diagram of an SSD according to an embodiment of the present invention. Referring to FIG. 21, the SSD 4000 includes a plurality of flash memory devices 4100 and an SSD controller 4200.

Each of the flash memory devices 4100 includes a nonvolatile memory device 100 shown in Figure 1, a nonvolatile memory device 200 shown in Figure 14, a nonvolatile memory device 300 shown in Figure 15, Volatile memory device 400 shown in FIGS. 16A and 16B.

The SSD controller 4200 controls the plurality of flash memory devices 4100. The SSD controller 4200 includes at least one central processing unit 4210, a host interface 4220, a buffer 4230, and a flash interface 4240.

The host interface 4220 exchanges data with the host in an ATA protocol manner under the control of the central processing unit 4210. Here, the host interface 4220 is any one of a SATA (Serial Advanced Technology Attachment) interface, a PATA (Parallel Advanced Technology Attachment) interface, and an ESATA (External SATA) interface. Data input from the host via the host interface 4220 or data to be transmitted to the host is transmitted through the cache buffer 4230 without passing through the CPU bus under the control of the central processing unit 4210. [

The buffer 4230 temporarily stores movement data between the outside and the flash memory devices 4100. The buffer 4230 is also used to store a program to be operated by the central processing unit 4210. [ The buffer 4230 may be implemented as a DRAM (DRAM) or an SRAM (SRAM). In FIG. 21, the buffer 4230 is included in the SSD controller 4200, but the present invention is not necessarily limited thereto. The buffer according to the present invention may be included outside the SSD controller 4200.

Flash interface 4240 performs interfacing between SSD controller 4200 and flash memory devices 4100 used as storage devices. Flash interface 4240 may be configured to support NAND flash memory, One-NAND flash memory, multi-level flash memory, and single-level flash memory.

The SSD 4000 according to the present invention improves the reliability of data by storing random data during a program operation. As a result, the SSD 4000 of the present invention can improve the reliability of stored data. A more detailed description of SSDs will be given in US patent application Ser. No. 2010-0082890, filed by Samsung Electronics and incorporated by reference.

22 is a block diagram of a computing system having the SSD 4000 shown in FIG. 22, the computing system 5000 includes at least one central processing unit 5100, a ROM 5200, a RAM 5300, an input / output unit 5400, and at least one SSD 5500 .

At least one central processing unit 5100 is coupled to the system bus. The ROM 5200 stores data necessary for operating the computing system 5000. Such data may include a start command sequence, or a basic input / output operation system (e.g., BIOS) sequence. The RAM 5300 temporarily stores data generated when the central processing unit 5100 is executed.

In the embodiment, the input / output device 5400 is connected to the system bus through an input / output device interface, such as a keyboard, a pointing device (mouse), a monitor, a modem, and the like.

The SSD 5500 is a readable storage device and is implemented in the same manner as the SSD 4000 shown in FIG.

23 is a block diagram of an electronic apparatus having the SSD 4000 shown in FIG. Referring to Figure 23, the electronic device 6000 includes at least one processor 6100, a ROM 6200, a RAM 6300, a host interface 6400, and at least one SSD 6500.

At least one processor 6100 accesses the RAM 6300 to execute firmware code or any code. In addition, the processor 6100 accesses the ROM 6200 to execute fixed instruction sequences, such as an initiation instruction sequence or basic input / output operation system sequences. The flash interface 6400 performs interfacing between the electronic device 6000 and the SSD 6500.

The SSD 6500 can be attached to or detached from the electronic device 6000. The SSD 6500 is implemented in the same manner as the SSD 4000 shown in FIG.

The electronic device 6000 of the present invention may be a cellular phone, a personal digital assistants (PDAs), a digital camera, a camcorder, and a portable audio player (e.g., MP3), a PMP, or the like.

24 is a block diagram of a server system using the SSD 4000 shown in FIG. Referring to FIG. 24, the server system 7000 includes a server 7100 and at least one SSD 7200 that stores data necessary to operate the server 7100. As shown in FIG. Here, the SSD 7200 is implemented in the same configuration and the same operation as the SSD 4000 shown in FIG.

The server 7100 includes an application communication module 7110, a data processing module 7120, an upgrade module 7130, a scheduling center 7140, a local resource module 7150, and a repair information module 7160.

Application communication module 7110 is configured to communicate with server 7100 and a computing system connected to the network or to communicate with server 7100 and SSD 7200. The application communication module 7110 transmits the applied data or information to the data processing module 7120 through the user interface.

Data processing module 7120 is linked to local resource module 7150. [ Where the local resource module 7150 applies a list of repair shops / dealers / technical information to the user based on the data or information entered into the server 7100.

The upgrade module 7130 interfaces with the data processing module 7120. The upgrade module 7130 upgrades the firmware, the reset code, the diagnostic system upgrade, or other information to the appliance based on the data or information transmitted from the SSD 7200.

The scheduling center 7140 allows the user a real-time option based on the data or information input to the server 7100. [

The repair information module 7160 interfaces with the data processing module 7120. Repair information module 7160 is used to apply repair related information (e.g., audio, video, or document file) to the user. The data processing module 7120 packages related information based on information transmitted from the SSD 7200. This information is then transmitted to the SSD 7200 or displayed to the user.

The non-volatile memory device according to the present invention is also applicable to tablet products (e.g., Galaxy Tab, iPad, etc.).

25 is an exemplary illustration of a portable electronic device 8000 according to the present invention. 25, a portable electronic device 8000 generally includes at least one computer readable medium 8020, a processing system 8040, an input / output subsystem 8060, a radio frequency circuit 8080 and an audio circuit 8100 ). Each component can be connected to at least one communication bus or signal line 8030.

The portable electronic device 8000 may be any portable electronic device including, but not limited to, a handheld computer, a tablet computer, a mobile phone, a media player, a personal digital assistant (PDA), and the like, . Wherein at least one computer readable medium 8020 includes at least one nonvolatile memory device 100 shown in FIG. A more detailed description of the portable electronic device (8000), on the other hand, will be described in U.S. Registration No. US 7,509,588, incorporated by reference.

The memory system or storage device according to embodiments of the present invention may be implemented using various types of packages. In an embodiment, a memory system or storage device according to an embodiment of the present invention may include a package on package (PoP), ball grid arrays (BGAs), chip scale packages (CSPs), plastic leaded chip carriers -Line Package (PDIP), Die in Waffle Pack, Die in Wafer Form, COB, Ceramic Dual In-Line Package, Plastic Metric Quad Flat Pack (MQFP), Thin Quad Flatpack (TQFP) (SIP), Multi-Chip Package (MCP), Wafer-level Fabricated Package (WFP), Small Outline (SOIC), Shrink Small Outline Package (SSOP), Thin Small Outline , A Wafer-Level Processed Stack Package (WSP), and the like.

While the invention has been shown and described with reference to certain preferred embodiments thereof, it will be understood by those skilled in the art that various changes and modifications may be made therein without departing from the spirit and scope of the invention. Therefore, the scope of the present invention should not be limited to the above-described embodiments, but should be determined by the equivalents of the claims of the present invention as well as the claims of the following.

100, 200, 300, 400: Nonvolatile memory device
110: memory cell array
120: page buffer circuit
130: Thermal select circuit
135: equivalent circuit
140: sense amplifier circuit
150, 350: I / O buffer
351: Single-ended input / output buffer
352: Differential input / output buffer
DL: Data lines
DLref: Reference data lines
LA: Latch addresses
YA: column address
PS: precharge signal
DSS: data detection signal
CLAT: Page buffer latch
141: Free car
142: current path generator
143: Differential Sense Amplifier
OPU0 to OPU7: Output circuit

Claims (44)

Page buffer latches for latching data read from memory cells;
Sub data lines receiving voltages corresponding to the latched data in response to latch addresses;
A data line connected to the sub data lines;
A reference data line in which a current path is formed in the sensing operation; And
And a sense amplifier circuit for sensing a voltage difference between the reference data line and the data line in the sensing operation and outputting data corresponding to a result of the voltage difference. The method according to claim 1,
And a column selection circuit for sequentially connecting the sub data lines to the data lines in response to column addresses,
Wherein the column selection circuit comprises column select transistors for coupling each of the sub data lines to the data line in response to the column addresses. delete 3. The method of claim 2,
Wherein the reference data line has a load element corresponding to a load of the data line. The method according to claim 1,
Wherein the sense amplification circuit comprises:
A precharger for precharging the reference data line and the data line;
A current path generator for forming the current path on the reference data line after the reference data line and the data line are precharged; And
And a differential sense amplifier for sensing a voltage difference between the reference data line and the data line. delete delete 6. The method of claim 5,
Wherein the current path generator varies the voltage of the reference data line in the sensing operation. 9. The method of claim 8,
Wherein the current path generator lowers the voltage of the reference data line in the sensing operation and when the latched data is data that lowers the voltage of the data line, Lt; / RTI &gt; is less than the falling slope,
The voltage change amount of the reference data line is smaller than the voltage change amount of the data line,
Wherein the voltage change amount of the reference data line is a value between two voltage values corresponding to the latched data at the time of performing the sensing operation. delete delete 9. The method of claim 8,
Wherein the current path generator comprises:
At least one current pass transistor having a gate receiving the trim code, the at least one current pass transistor being connected between the reference data line and the pass node; And
And a path forming transistor for connecting the pass node to the ground node in response to an inverted signal of the precharge signal. delete delete 6. The method of claim 5,
The differential sense amplifier includes:
A first PMOS transistor connected between the power supply terminal and the output node and having a gate connected to the inverted output node;
A second PMOS transistor connected between the power supply terminal and the inverting output node and having a gate connected to the output node;
A first NMOS transistor coupled to the output node and a bias node, the first NMOS transistor having a gate coupled to the inverted output node;
A second NMOS transistor connected to the inverting output node and the bias node and connected to the output node; And
And a third NMOS transistor for connecting the bias node and the ground terminal in the sensing operation. delete delete delete delete delete delete delete delete delete delete delete delete Latching data of the memory cells through corresponding bit lines;
Transmitting voltages corresponding to the latched data to a data line; And
Sensing a voltage difference between the data line and a reference data line,
Wherein the sensing comprises forming a current path in the reference data line. &Lt; Desc / Clms Page number 21 &gt; 29. The method of claim 28,
The step of latching data of the memory cells comprises:
Precharging the bit lines; And
And sensing a change in the precharged bit lines. delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete

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