KR101796439B1 - signal analyzing apparatus and method for WCDMA - Google Patents

signal analyzing apparatus and method for WCDMA Download PDF

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KR101796439B1
KR101796439B1 KR1020160006382A KR20160006382A KR101796439B1 KR 101796439 B1 KR101796439 B1 KR 101796439B1 KR 1020160006382 A KR1020160006382 A KR 1020160006382A KR 20160006382 A KR20160006382 A KR 20160006382A KR 101796439 B1 KR101796439 B1 KR 101796439B1
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data
signal
sequence
descrambled
scrambling code
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KR20170086853A (en
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정진섭
이주형
임용훈
김태범
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주식회사 이노와이어리스
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J13/00—Code division multiplex systems
    • H04J13/0003—Code application, i.e. aspects relating to how codes are applied to form multiplexed channels
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J13/00—Code division multiplex systems
    • H04J13/0007—Code type
    • H04J13/004—Orthogonal
    • H04J13/0044—OVSF [orthogonal variable spreading factor]
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J13/00—Code division multiplex systems
    • H04J13/16—Code allocation
    • H04J13/18—Allocation of orthogonal codes
    • H04J13/20—Allocation of orthogonal codes having an orthogonal variable spreading factor [OVSF]

Abstract

The present invention relates to a signal analyzing apparatus and method for a WCDMA system capable of shortening the time required for signal analysis by allowing descrambling and despreading procedures for all possible combinations of WCDMA reception data to be performed collectively will be.
A signal analyzing apparatus of a WCDMA system according to an aspect of the present invention includes: a signal analyzer for analyzing a WCDMA received signal; A m-sequence x (n) table previously calculated and stored by the scrambling code n, which is an m-sequence x used for descrambling; An OVSF code table in which all OVSF codes are pre-calculated and stored; A descrambler for performing descrambling using the m-sequence x stored in the m-sequence x (n) table as a parallel processing unit for a WCDMA receive signal, and a descrambler for performing descrambling by the OVSF code stored in the OVSF code table Comprising: a plurality of processors, each processor comprising: A controller for collectively processing descrambling and de-spreading by controlling each processor based on a command or parameter input from the signal analyzer; A baseband IQ buffer for storing baseband IQ data; a descrambled IQ buffer for storing descrambled IQ data output from the descrambler; and a symbol buffer for storing symbol data output from the despreader.

Description

The present invention relates to a signal analyzing apparatus and method for a WCDMA system,

The present invention relates to an apparatus and a method for analyzing a signal in a WCDMA system, and in particular, to reduce the time required for signal analysis by performing descrambling and despreading procedures for all possible combinations of WCDMA reception data To a signal analysis apparatus and method for a WCDMA system.

As is well known, the Universal Mobile Telecommunication System (UMTS) is a European type mobile communication system, which is an asynchronous Wideband Code Division Multiple Access (WCDMA) system based on a Global System for Mobile communication (GSM) .

In UMTS, a method of assigning different scrambling codes to each base station is used to distinguish each base station. That is, each of cells constituting a WCDMA base station system, for example, 512 base stations, is allocated a different scrambling code among 512 scrambling codes, and uses the scrambling code as a code for distinguishing itself. Since a base station transmits a signal using a scrambling code for distinguishing itself, a user equipment (UE) must be able to identify a scrambling code of the base station so that it can normally receive a signal provided by the base station. The process of identifying a code is commonly referred to as a cell search process.

However, in order for the user terminal to search for the base station to which the user terminal belongs, all of the 512 base stations constituting the UMTS must be searched for, so that it takes a considerable amount of time to search for the cell to which the user terminal belongs.

In consideration of this, for example, 512 base stations belonging to UMTS are divided into a predetermined number of groups, for example, 64 groups (Group 0 to Group 63), and each base station group is divided into 8 base stations again, Cell search is possible. Here, 64 different base station groups are given different group identification codes, and each of the 8 base stations is also assigned a different cell specific code, so that the user terminal finally searches for the base station to which the base station belongs can do.

The multi-stage cell search process can be performed in the following three steps. First, a first-stage cell search process is a process in which a user terminal receives a Primary Synchronization CHannel (P-SCH) signal transmitted from a base station and finds and synchronizes a slot timing received at a maximum power among the received signals. In the second-stage cell search process, the user terminal receives the slot timing information found in the first-stage cell search process, and transmits frame synchronization and its own base station group through a second synchronization channel (S-SCH) . The third stage cell search process is a process in which the user terminal finally searches for a base station to which the user terminal belongs based on the common pilot channel (CPICH) signal transmitted from the base station based on the frame synchronization and base station group information found in the second- to be.

On the other hand, in the WCDMA system, the spreading of each channel consists of a channelization operation followed by a scrambling operation. In the channelization operation, each data symbol is transformed into a number of so-called chips by multiplying the number of chips per data symbol by a spreading factor ( SF). The channelization code is usually an Orthogonal Variable Spreading Factor (OVSF) with spreading factors of up to 512. As a result, the scrambling code is used to identify the base station or cell, while the channelization code is used to distinguish the different physical channels (user terminals) in each cell.

Next, the timing structure of the WCDMA system will be described. A chip is transmitted within a TTI (Transmission Time Interval), and each TTI consists of one to eight radio frames. Each radio frame has a duration of 10 ms and is divided into 15 slots. The slot contains 2560 chips. Thus, the TTI may include 15 to 120 slots.

On the other hand, in analyzing the WCDMA signal, it is general to sequentially down-convert an RF signal inputted in hardware into an intermediate frequency signal and a baseband IQ signal, and process the signal analysis thereafter by software.

In WCDMA, user information is spread over a wide band by a spreading code, i.e., an OVSF code, and multiplied by a scrambling code. Therefore, the WCDMA signal analysis includes a descrambling and a descrambling process in which a base station processes a spreading code and a scrambling code used in a signal transmission process inversely, and when a spreading code and a scrambling code used in a base station are unknown, We need to deal with all combinations. However, in the conventional WCDMA signal analyzer, since the above-described operations are all performed in software, it takes much time to process the WCDMA signal of one frame, for example, more than two seconds, for example, about 2-5 seconds. There is a problem in that the time required for the operation is long.

Prior Art 1: 10-2004-0070693 Disclosure of the Invention (Synchronous Acquisition Device and Method in Asynchronous Next Generation Mobile Communication System) Prior Art 2: 10-2010-0006111 Disclosure of the Invention (Title of the Invention: Signal Analysis Method of Mobile Communication System) Prior Art 3: 10-2010-0130659 (Patent Title: METHOD AND APPARATUS FOR TIME TRACKING FOR CHANNEL ESTIMATION OF MOBILE COMMUNICATION RECEIVER)

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and it is an object of the present invention to reduce the time required for signal analysis by allowing descrambling and despreading procedures for all possible combinations of WCDMA reception data to be performed collectively And a signal analysis apparatus and method for a WCDMA system.

A signal analyzing apparatus of a WCDMA system according to an aspect of the present invention includes: a signal analyzer for analyzing a WCDMA received signal; A m-sequence x (n) table previously calculated and stored by the scrambling code n, which is an m-sequence x used for descrambling; An OVSF code table in which all OVSF codes are pre-calculated and stored; A descrambler for performing descrambling using the m-sequence x stored in the m-sequence x (n) table as a parallel processing unit for a WCDMA receive signal, and a descrambler for performing descrambling by the OVSF code stored in the OVSF code table Comprising: a plurality of processors, each processor comprising: A controller for collectively processing descrambling and de-spreading by controlling each processor based on a command or parameter input from the signal analyzer; A baseband IQ buffer for storing baseband IQ data; a descrambled IQ buffer for storing descrambled IQ data output from the descrambler; and a symbol buffer for storing symbol data output from the despreader.

In the above-described configuration, the signal analysis unit is implemented by software means, and the control unit and the processor are implemented by hardware means.

And the m-sequence x (n) table and the OVSF table are respectively provided in a plurality of the processors.

A signal analysis method of a WCDMA system according to another aspect of the present invention includes a m-sequence x (n) table storing a result of LFSR operation of an m-sequence x by a signal analysis unit and a scrambling code n, (P-SCH) included in the baseband IQ data transmitted from the base station, and a second synchronization channel (P-SCH) included in the baseband IQ data transmitted from the base station in cooperation with a control unit comprising hardware means having an OVSF code table storing the OVSF code values. (A) detecting a scrambling code group (j) using a synchronization channel (S-SCH) signal; (B) requesting a symbol output for all k (scrambling code classification parameters) while identifying and delivering an OVSF code to a control unit to search for a scrambling code used in a transmitting base station;

The control unit performs descrambling using the m-sequence x (n) read from the m-sequence x (n) table corresponding to all k to output the descrambled IQ data, and in the step (b) (C) outputting symbol data by despreading the descrambled IQ data by an OVSF; (D) analyzing the descrambled IQ data and the symbol data to detect a scrambling code used in a transmitting base station; (E) requesting a control section to output a symbol for all combinations of SF / idx while transmitting a scrambling code detected in step (d) to find a physical channel used for signal analysis sub-data transmission; (F) of performing despreading on the descrambled IQ data corresponding to the scrambling code received from the signal analyzer in combination with all of SF / idx and outputting the symbol data, and the signal analyzing unit And analyzing the symbol data to detect a used physical channel (g).

In the above-described configuration, the OVSF code specified in the step (b) is C ch, 256 , 0 .

In step (f), the controller performs descrambling using the m-sequence x (n) read from the m-sequence x (n) table corresponding to the scrambling code received from the signal analysis unit, Is obtained.

The controller extracts the descrambled IQ data corresponding to the scrambling code received from the signal analyzer from among the descrambled IQ data output in step (c), and then performs step (f).

According to the signal analysis apparatus and method of the WCDMA system of the present invention, descrambling and despreading procedures for all possible combinations of WCDMA receive data are collectively performed using descrambling and despreading accelerators optimized for WCDMA systems. The time required for the overall signal analysis can be shortened.

1 is a block diagram of a signal analysis apparatus of a WCDMA system according to an embodiment of the present invention;
2 is a block diagram of a signal analysis apparatus of a WCDMA system according to another embodiment of the present invention.
3 is a flowchart illustrating a signal analysis method of a WCDMA system according to the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings.

1 is a block diagram of a signal analysis apparatus of a WCDMA system according to an embodiment of the present invention. As shown in FIG. 1, the signal analysis apparatus of the WCDMA system of the present invention mainly comprises: a signal analysis unit 100 for analyzing a WCDMA received signal; A plurality of processors (120: 120-1, ..., 120-n), each of which is comprised of a descrambling accelerator (122) and a despreading accelerator (124) for performing descrambling and despreading, , 120-n); A controller (not shown) for collectively processing descrambling and de-spreading while minimizing the intervention of the signal analyzer 100 by controlling each processor 120 based on commands or parameters received from the signal analyzer 100 110); A baseband IQ buffer 130 for storing baseband IQ data; A descrambled IQ buffer 140 for storing the descrambled IQ data output from the descrambling accelerator 122 and a symbol buffer 150 for storing the symbol data output from the display accelerator 124. [

In the above-described configuration, the signal analysis unit 100 may be implemented by, for example, signal analysis software installed in a PC. The controller 110 and the processor 120 may be implemented as a hardware block, for example, an IP block inside a field programmable gate array (FPGA).

The controller 110 receives commands or parameters from the signal analyzer 100 and can operate any of the processors 120 or simultaneously operate all of the processors 120. [

Processor 120 is preferably provided with a possible range of scrambling code segmentation parameter k, e. G., Eight, as described below. The descrambling accelerator 100 provided in each processor 120 has a table m-sequence x (n) which is a memory block in which all maximal length sequences x (n) And a descrambler 122a for descrambling the m-sequence by using the m-sequence x (n) table 122b. For example, in processing one frame with a clock cycle of 38400 (2560 chips * 15 slots), the time taken for eight ks, for example, when employing eight processors 120 using a clock of 122.88 ㎒ (1) < / RTI >

Figure 112016005904223-pat00001

In this regard, in the scrambling process of the WCDMA system, there is a process of operating an LFSR (Linear Feedback Shift Register) by an n value which is a scrambling code for an m-sequence x (usually 18 bits) Can be a multiple of 16 between 0 and 8192 * 3.

Figure 112016005904223-pat00002

In the above equation, n denotes a scrambling code, j denotes a scrambling code group classification parameter, k denotes a scrambling code classification parameter, and m denotes a scrambling code classification parameter used in the compressed mode transmission.

On the other hand, since the initial condition x (0) of the m-sequence x is constant, the m-sequence x (n) generated by operating the LFSR by the scrambling code n is also constant. Therefore, if the m-sequence x (n) is previously calculated and stored in the m-sequence x (n) table 122b, the calculation process for generating the m-sequence x (n) in the descrambling process can be omitted The size of the required memory is (8192 * 3) / 16 * 18 bits = 3.375KB.

Once the value of the scrambling code n, that is, j, k, and m, is determined, the address of the m-sequence x (n) table is obtained as shown in Equation 3 below and the desired scrambling code is quickly obtained And descrambling can be performed directly on the basis of this value.

Figure 112016005904223-pat00003

Next, the de-spreading accelerator 124 generates an OVSF code table 124b and an OVSF code table 124b, which are memory blocks in which OVSF codes Cch, SF, and idx, which are channelization codes, And a despreader 124a for obtaining a desired OVSF code and then performing despreading. For example, in processing one frame with a clock cycle of 38400 (2560 chips * 15 slots), for example, when employing eight processors 120 using a clock of 122.88 ㎒, The time required is approximated by Equation (4) below.

Figure 112016005904223-pat00004

In this regard, the OVSF code used in the despreading is fixed according to the SF / idx value. Therefore, the OVSF code generation process can be omitted by preliminarily calculating and storing these values. The OVSF code table 124b is a memory block that stores OVSF code values for the case where the SF is 512. The OVSF code values for the case where SF is smaller than 512 due to the characteristics of the OVSF code are not required to be stored separately using a memory block, It can be simply extracted from the OVSF code table 124b according to the SF / idx value, and the capacity of the memory block can be reduced by doing so. The required memory size is 512 * 512 bits = 32KB.

On the other hand, once the SF / idx value is determined, the desired OVSF code Cch, SF, and idx values can be obtained by obtaining the address value of the OVSF code table as shown in Equation 5 below.

Figure 112016005904223-pat00005

As described above, according to the present invention, since the WCDMA signal of one frame can be processed, i.e., descrambled and descrambled within approximately 50 ms, the total analysis time for the WCDMA signal can be greatly shortened.

2 is a block diagram of a signal analysis apparatus of a WCDMA system according to another embodiment of the present invention. The same reference numerals are assigned to the same parts as those in FIG. 1, and a detailed description thereof will be omitted. 2, in this embodiment, the descrambler 122 'and the despreader 124' of each of the plurality of processors 120 ': 120'-1, ..., 120'-n are m- The sequence x (n) table 126 and the OVSF code table 128 are commonly used. Sequence x (n) table 126 and the OVSF code table 128 according to the number of input / output ports supported by the memory blocks constituting the m-sequence x (n) table 126 and the OVSF code table 128. As a result, The number of descramblers 122 'and the number of despreaders 124' that are capable of concurrent access to the processor 128 will be determined.

3 is a flowchart for explaining a signal analysis method of the WCDMA system of the present invention. As shown in FIG. 3, according to the signal analysis method of the WCDMA system of the present invention, the analyzer first receives an RF signal from a base station, downconverts it into an intermediate frequency and baseband IQ signal in hardware, And then stores the baseband IQ signal in the baseband IQ buffer 130. [0031] In this state, the signal analysis unit 100 uses the first synchronization channel (P-SCH) and the second synchronization channel (S-SCH) signals included in the baseband IQ data stored in the baseband IQ buffer 130 And detects a scrambling code group j (step S10).

Next, the signal analyzing unit 100 finds a scrambling code used in the transmitting base station In step S 20, the CPICH (Common PIlot CHannel) is fixed to the channelization code C ch, 256 , 0 in the WCDMA system. (OVSF) code to C ch, 256,0 and transmits it to the control unit 110 in order to find it.

Sequence x (n) for all k can be expressed as m (n) by simultaneous driving (in the case of the embodiment of FIG. 1) or sequential driving (in the embodiment of FIG. 2) - The descrambled IQ data obtained by outputting from the sequence table and performing descrambling using the descrambled IQ data is stored in the descrambled IQ buffer 140. The control unit 110 also decodes the descrambled IQ data stored in the descrambled IQ buffer 140 using the OVSF code of C ch, 256 , 0 and stores the result in the symbol buffer 150 Step S30).

Next, the signal analyzer 100 analyzes the descrambled IQ data and symbol data stored in the descrambled IQ buffer 140 and the symbol buffer 150 and detects a scrambling code used in the transmitting base station (step S40) Then, in order to find the physical channel used for data transmission, the control unit 110 is requested to output a symbol for all SF / idx combinations (step S50) while transferring the scrambling code detected in step S40.

In response to this, the control unit 110 reads the m-sequence x (n) corresponding to the scrambling code received from the signal analysis unit 100 from the m-sequence x (n) table using any one processor 120 And stores the resulting descrambled IQ data in the descrambled IQ buffer 140 (step S60).

Next, the controller 110 performs despreading on the disjointed IQ data stored in the descrambled IQ buffer 140 with all SF / idx combinations stored in the OVSF code table, and outputs the outputted symbol data to the symbol buffer (Step S70). Finally, the signal analyzer 100 analyzes the stored symbol data to detect a used physical channel (step S80), and then performs necessary analysis.

In the above description, only the case of m = 0 in the normal mode frame, that is, the case of m = 0 in Equation (3) has been described. However, in the case of m = 1 and m = 2 in the compression mode frame, It can be used as it is. In step S60, instead of performing descrambling, the controller 110 reads the descrambled IQ data already stored in the descrambled IQ buffer 140 corresponding to the scrambling code in step S30, and performs step S70 It might be.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to those precise embodiments and various modifications may be made without departing from the scope of the invention. . Accordingly, the scope of the present invention should be determined by the following claims.

100: signal analysis unit, 110, 110 ': control unit,
120, 120 ', 120-1, 120'-1, 120-n, 120'-
130: baseband IQ buffer, 140: descrambled IQ buffer,
150: Symbol buffer

Claims (7)

delete delete delete (N) table storing the result of performing the LFSR operation of the m-sequence x by the scrambling code n and the OVSF code table storing the OVSF code value A control unit consisting of a plurality of control units,
(A) detecting a scrambling code group (j) using a first synchronization channel (P-SCH) and a second synchronization channel (S-SCH) signal included in baseband IQ data transmitted from a signal analysis unit ;
(B) requesting a symbol output for all k (scrambling code classification parameters) while identifying and delivering an OVSF code to a control unit to search for a scrambling code used in a transmitting base station;
The control unit performs descrambling using the m-sequence x (n) read from the m-sequence x (n) table corresponding to all k to output the descrambled IQ data, and in the step (b) (C) outputting symbol data by despreading the descrambled IQ data by an OVSF;
(D) analyzing the descrambled IQ data and the symbol data to detect a scrambling code used in a transmitting base station;
(E) requesting a control section to output a symbol for all combinations of SF / idx while transmitting a scrambling code detected in step (d) to find a physical channel used for signal analysis sub-data transmission;
(F) of performing despreading on the descrambled IQ data corresponding to the scrambling code received from the signal analyzer in combination with all SF / idx to output symbol data, and
And analyzing the symbol data to detect a used physical channel (g). 5. The method of claim 4,
Wherein the OVSF code specified in step (b) is C ch, 256 , 0 . The method according to claim 4 or 5,
In step (f), the controller performs descrambling using the m-sequence x (n) read from the m-sequence x (n) table corresponding to the scrambling code received from the signal analysis unit, Wherein the signal analyzing method comprises the steps of: The method according to claim 4 or 5,
Wherein the controller extracts the descrambled IQ data corresponding to the scrambling code received from the signal analysis unit from the descrambled IQ data output in the step (c), and then performs the step (f). .
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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030215003A1 (en) * 2002-05-20 2003-11-20 Bottomley Gregory E. System and method for fast walsh transform processing in a multi-coded signal environment
US20070041433A1 (en) * 2005-08-18 2007-02-22 Gongyu Zhou Method and apparatus for compact OVSF despreading

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030215003A1 (en) * 2002-05-20 2003-11-20 Bottomley Gregory E. System and method for fast walsh transform processing in a multi-coded signal environment
US20070041433A1 (en) * 2005-08-18 2007-02-22 Gongyu Zhou Method and apparatus for compact OVSF despreading

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