KR101794192B1 - Metal-Interlayer-Semiconductor Structure on Source/Drain Contact for Low Temperature Fabrication with Monolithic 3D Integration Technology and Manufacturing Method - Google Patents

Metal-Interlayer-Semiconductor Structure on Source/Drain Contact for Low Temperature Fabrication with Monolithic 3D Integration Technology and Manufacturing Method Download PDF

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KR101794192B1
KR101794192B1 KR1020150025561A KR20150025561A KR101794192B1 KR 101794192 B1 KR101794192 B1 KR 101794192B1 KR 1020150025561 A KR1020150025561 A KR 1020150025561A KR 20150025561 A KR20150025561 A KR 20150025561A KR 101794192 B1 KR101794192 B1 KR 101794192B1
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semiconductor
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dielectric layer
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metal
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유현용
김광식
김승환
최리노
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고려대학교 산학협력단
인하대학교 산학협력단
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/3141—Deposition using atomic layer deposition techniques [ALD]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors

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Abstract

The present invention relates to a semiconductor device in which a source or a drain is formed, comprising a semiconductor layer, a metal layer forming a source or a drain of the semiconductor element, and a dielectric layer formed between the metal layer and the semiconductor layer, The present invention can provide a semiconductor device which realizes low contact resistance only by a low temperature process by controlling the doping concentration of the dielectric layer by controlling the number of times of the material supply cycle of the ALD process.

Description

[0001] The present invention relates to a metal-dielectric-semiconductor structure of a source and drain contact for a three-dimensional single-integrated low-temperature process technology,

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device in which a source or a drain is formed, and more particularly, to a semiconductor device and a manufacturing method for implementing a low contact resistance by laminating a dielectric layer between a metal layer and a semiconductor layer.

Recently, three-dimensional single integration technology has been actively developed. However, when three-dimensional process is performed, there is a disadvantage that process of each device may affect each other. Among them, the temperature plays the most critical role, for example, when the first device has weak heat characteristics, if the high temperature process is required in the upper layer process, it can not be integrated in three dimensions. Typically, a high temperature process is required to form an ohmic contact at the junction of the source and drain metal, which is a critical drawback to a three-dimensional, single integrated process technology.

Both conventional source and drain ohmic contact technology studies require high temperature processes. In addition, high-temperature processes are pointed out as fatal disadvantages to a single integrated technology. Particularly, since the three-dimensional single integration technique is performed by stacking the devices in a layer, if the latter process damages the completed device in the first half, the completed device is destroyed. In the case of silicon, a mixture such as NiSi or SiGe has been used to form an ohmic contact between the source and the drain, but the high temperature process and the pinning phenomenon have not been completely blocked. Because of these drawbacks, devices using high temperature process technologies can not be integrated into a three-dimensional single integrated process technology, which can hinder the development of the next generation technology.

Semiconductor devices, such as MOSFETs and FinFETs, consist of a gate for switching and a source and a drain (Source and Drain) formed to carry current through a channel created by switching.

In order to reduce power consumption when semiconductor devices operate, the reduction of contact resistance at the source and drain is inevitable. For this, n-type high doping is performed for NMOS and p-type high doping for PMOS. However, even with high doping, contact resistance increases due to the Schottky barrier between the metal and the semiconductor.

Schottky barriers can be solved by adjusting the work function of the metal when it is ideal, but the Schottky barrier can not be effectively reduced because there is actually a metal induced gap states (MIGS) effect between the metal and the semiconductor .

MIGS induces a density of states on the surface of a semiconductor by means of a metal bonded to the semiconductor, so that the Fermi level becomes close to the Charge Neutral Level (CNL) characteristic of each semiconductor material. This is called Fermi-level Pinning.

Korean Patent Publication "Method of forming a source / drain junction of a semiconductor device (10-1996-0009067)"

A first object of the present invention is to provide a semiconductor device having a low contact resistance by forming a dielectric layer between a metal layer and a semiconductor layer by a low temperature process.

A second problem to be solved by the present invention is to provide a method of manufacturing a semiconductor device which realizes a low contact resistance by laminating a dielectric layer between a metal layer and a semiconductor layer only by a low temperature process.

In order to solve the first problem, the present invention provides a semiconductor device in which a source or a drain is formed, comprising: a semiconductor layer; a metal layer forming a source or drain of the semiconductor element; and a dielectric layer formed between the metal layer and the semiconductor layer Wherein the dielectric layer is doped through an atomic layer deposition process to implement an ohmic contact between the source and the drain in a low temperature process by a structure in which the doped dielectric layer is inserted into the source and drain contacts, The contact resistance can be lowered by the low temperature process than when the dielectric layer is undoped.

delete

According to another embodiment of the present invention, the dielectric layer may be formed of a material having a conduction band offset (CBO) with respect to the semiconductor layer of less than a threshold value, formed of a material having a bandgap energy of a threshold value or more, And the thickness of the first insulating layer is a thickness of the second insulating layer.

delete

According to another embodiment of the present invention, when the semiconductor is an n-type semiconductor, the metal layer is formed of a metal having a difference between the electron affinity of the semiconductor layer and a threshold value or less, and when the semiconductor is a p- And the difference between the electron affinity of the layer and the sum of the band gap energy is less than or equal to a threshold value.

According to a second aspect of the present invention, there is provided a method of forming a source or a drain in a semiconductor device, comprising: stacking a dielectric layer on a semiconductor layer; Performing doping on the dielectric layer; And depositing a metal layer forming a source or drain on the dielectric layer, wherein the dielectric layer is doped through an atomic layer deposition process (ALD) to form a structure in which the doped dielectric layer is inserted into the source and drain contacts The ohmic contacts of the source and the drain are implemented in a low temperature process and the contact resistance is lowered only when the dielectric layer is not doped by the low temperature process.

delete

According to the present invention, the damage caused by the high-temperature process can be minimized by realizing a low contact resistance by the low-temperature process alone. In addition, an ohmic contact can be formed by lowering the Schottky barrier. CBOs with semiconductors can deposit a very small dielectric layer and extract a lower contact resistance when doped with the dielectric layer. Both the n-type and p-type semiconductors can form an ohmic contact by bonding a metal having a small work function to an n-type silicon introduced with an MIS structure and a metal having a large work function to the p-type silicon. Since the MIS structure can form an ohmic contact only by the deposition of the dielectric layer and minimize the damage caused by the high-temperature process, both the process convenience and the device efficiency can be improved. Since the low contact resistance can be extracted only by the low temperature process, the MIS structure can be applied to the source and drain of most semiconductor devices, which can be an effective method for the next generation process technology. In particular, It will be able to promote development.

1 is a semiconductor structure according to an embodiment of the present invention.
FIG. 2 shows the MIGS (Metal Induced Gap States) effect between a metal and a semiconductor.
FIG. 3 shows the change of MIGS (Metal Induced Gap States) effect in metal-dielectric-semiconductor.
4 to 6 show changes in contact resistance depending on the thickness of the dielectric layer.
Figs. 7 to 8 show changes in contact resistance depending on the thickness of the dielectric layer.
Figures 9 to 10 show changes in contact resistance with doping.
11 is a semiconductor structure according to an embodiment of the present invention.
12 is a flow chart of a method of fabricating a semiconductor structure according to an embodiment of the present invention.
13 is a flowchart of a method of manufacturing a semiconductor structure according to another embodiment of the present invention.

Prior to the description of the concrete contents of the present invention, for the sake of understanding, the outline of the solution of the problem to be solved by the present invention or the core of the technical idea is first given.

A semiconductor device in which a source or a drain is formed includes a semiconductor layer, a metal layer forming a source or drain of the semiconductor element, and a dielectric layer formed between the metal layer and the semiconductor layer according to an embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. It will be apparent to those skilled in the art, however, that these examples are provided to further illustrate the present invention, and the scope of the present invention is not limited thereto.

BRIEF DESCRIPTION OF THE DRAWINGS The above and other features and advantages of the present invention will become more apparent by describing in detail preferred embodiments thereof with reference to the attached drawings in which: It is possible to quote the above. In the following detailed description of the principles of operation of the preferred embodiments of the present invention, it is to be understood that the present invention is not limited to the details of the known functions and configurations, and other matters may be unnecessarily obscured, A detailed description thereof will be omitted.

1 is a semiconductor structure according to an embodiment of the present invention.

A semiconductor structure according to one embodiment of the present invention is comprised of a semiconductor layer 110, a metal layer 130, and a dielectric layer 120.

The metal layer 130 forms the source or drain of the semiconductor device.

A dielectric layer 120 is formed between the metal layer 130 and the semiconductor layer 110.

More specifically, when the dielectric layer 120 is formed between the metal layer 130 and the semiconductor layer 110, the metal layer 130 and the semiconductor layer 110 are directly contacted with each other.

The dielectric layer 120 may be formed through an atomic layer deposition process (ALD). First, the source and drain are heavily doped through a hardmask pattern, and a thin dielectric layer is deposited using an ALD (Atomic Layer Deposition) process. In the case of the atomic layer deposition process, it is possible to deposit a nano-thick film having excellent uniformity even in a complicated three-dimensional structure, which is suitable for manufacturing nano-scale semiconductor devices. The technique of supplying atoms necessary for thin film formation alternately so as to adsorb one atom layer by one, depositing a thin film made of a high-quality material such as AB by using a substance in the form of a gas such as AX and BY as a raw material, and forming a gaseous XY The atomic layer is deposited through the reaction of AX (gas) + BY (gas) -> AB (solid) + XY (gas). If the supply of raw materials is sufficient during the deposition process, the growth rate of the thin film is proportional to the number of times of the supply cycle, so that the thickness of the thin film can be precisely controlled to several Å (armstrong). It is possible to precisely adjust the thickness and composition of the thin film, to produce a thin film of good quality with few impurities and without bonding of pinholes and the like. In addition, the three-dimensional structure can be uniformly stacked and large-area deposition is also possible. When physical processing equipment such as a sputter or an evaporator is used, the characteristics of the dielectric layer are poor and the deposition rate is high, making it difficult to form a thin layer. After the dielectric layer is deposited, suitable metals are deposited according to the n-type and p-type semiconductor devices.

When the metal layer 130 and the semiconductor layer 110 are in direct contact with each other, the contact resistance increases due to a schottky barrier between the metal and the semiconductor, as shown in FIG. 2A. In addition, there is an effect of metal induced gapped states (MIGS) between the metal and the semiconductor, so that the Schottky barrier can not be effectively reduced. MIGS induces a density of states on the surface of a semiconductor by means of a metal bonded to the semiconductor, so that the Fermi level becomes close to the Charge Neutral Level (CNL) characteristic of each semiconductor material. This is called Fermi-level Pinning. MIGS is shown in Figures 2b and 2c.

In the case of silicon, CNL is on the valence band side. As can be seen in FIG. 2d, the Schottky barrier increases due to the Fermi level pinning between the n-type silicon and the metal, and the Schottky barrier increases due to the Fermi-level pinning even between the p- Can be confirmed.

The Fermi level pinning due to the MIGS phenomenon can be reduced by inserting the dielectric layer 120 between the metal layer 130 and the semiconductor layer 110 to form a MIS (Metal-Interlayer-Semiconductor) structure.

As shown in FIGS. 3A and 3B, when the dielectric layer is inserted, the MIGS can be effectively reduced, and the contact resistance can be reduced because electrons can easily pass through the tunneling. However, when the dielectric layer is thick, the contact resistance may increase again because electrons can not penetrate. Therefore, in order to solve this problem, the dielectric layer 120 may be formed to a thickness that minimizes the contact resistance, or may be formed of a material having a bandgap energy of a threshold value or more. The threshold value of the band gap energy may be set through experiments or the like, or may be preset by the manufacturer of the semiconductor device. Also, a dielectric layer can be formed using a material having the largest band gap energy among a plurality of materials.

The MIGS density decreases exponentially as it penetrates into other materials, as shown in Equation (1) below, depending on the thickness of the penetrating material and the magnitude of the bandgap energy.

Figure 112015018004496-pat00001

Deposition of a material with a high bandgap energy between the semiconductor and the metal can reduce pinning induced by the metal. Also, as can be seen from Equation (2), the S value can be expressed by the formula for the MIGS density in Equation (1). The closer the value of S is to zero, the more the pin is completely pinned to CNL.

Figure 112015018004496-pat00002

The Schottky barrier as shown in FIGS. 2B and 2C has a relative metal work function, not a metal specific work function, as shown in Equation 3, due to the pinning phenomenon.

Figure 112015018004496-pat00003

As the S value of Equation (2) approaches 1, the CNL work function in Equation (3) becomes smaller, and it can be seen that the matching is performed according to the inherent metal work function.

In the case of silicon, since the S value is about 0.3, it is likely to be pinned by CNL, and the Schottky barrier becomes larger regardless of the work function of the metal. Thin deposition of a wide band gap dielectric over silicon effectively blocks MIGS penetration, thereby reducing Fermi-level pinning and lowering the Schottky barrier.

Referring to FIG. 4, it can be seen that the contact resistance changes according to the thickness of the dielectric layer. If the thickness is too thin, the MIGS can not be sufficiently lowered, and the contact resistance is high because the Schottky barrier is still high. And thus has a high contact resistance.

FIGS. 5 and 6 are simulation results showing whether the change in contact resistance according to the thickness of the dielectric layer when the dielectric layer is deposited on the n-type semiconductor and the p-type semiconductor is consistent with FIG. n-type and the doping concentration of the p-type semiconductor source and drain are each 1 × 10 19 cm - was a simulation of three.

After the dielectric layer is deposited on the n-type silicon, a metal having a small work function should be used to make an ohmic contact. However, if a metal having the same work function is used for the p-type silicon, a metal having a large work function should be used because the Schottky barrier on the valence band side of the hole is large. That is, the n-type and p-type semiconductor devices must use metals having different work functions due to tunneling Schottky barriers that vary depending on the Fermi-level matching formed between the metal and the semiconductor. Therefore, when the semiconductor is an n-type semiconductor, the metal layer is formed of a metal having a difference between the electron affinity of the semiconductor layer and a threshold value, and when the semiconductor is a p-type semiconductor, the electron affinity and the band gap energy May be formed of a metal whose difference from the sum of the sum of the thicknesses is less than or equal to the threshold value. The threshold for selecting the metal may be set through experiments or the like, or may be preset by the manufacturer of the semiconductor device. In addition, a metal layer can be formed using a material having the smallest difference between the electron affinity of the semiconductor layer of the plurality of materials or the sum of the electron affinity and the band gap energy of the semiconductor layer.

Fig. 5 is for a source and a drain of an n-type semiconductor, which is simulated as a metal having a similar work function to the electron affinity of the semiconductor. FIG. 6 is for a source and a drain of a p-type semiconductor and is simulated as a metal having a work function similar to the sum of electron affinity and band gap energy of a semiconductor. In practice, suitable metals for n-type semiconductors include Ti and Al, and metals suitable for p-type semiconductors include Pt.

The dielectric layer 120 may be formed of a material having a conduction band offset (CBO) with respect to the semiconductor layer 110 that is lower than a critical value. When the CBO of the dielectric layer and the semiconductor is small, electrons can be easily tunneled, thereby further reducing the contact resistance. When a material having a very small semiconductor and CBO (Conduction Band Offset) is used for the dielectric layer 120, the tunneling thickness is reduced as compared with FIG. 3A as shown in FIG. In addition, when a CBO with a semiconductor material is used, the thickness of the tunneling is thin, so that the contact resistance is kept low even if the thickness is increased to some extent. There are materials such as ZnO and TiO2 as dielectric layers with very small differences between silicon and CBO. When a CBO with a semiconductor is used with a small dielectric layer, the thickness of the tunneling is thin. Therefore, as the thickness of the CBO increases, the contact resistance becomes low at the contact resistance as shown in FIG. The threshold value of the conduction band offset may be set through experiments or the like, or may be preset by the manufacturer of the semiconductor device. In addition, a dielectric layer can be formed using a material having the smallest conduction band offset from the semiconductor layer among a plurality of materials.

The dielectric layer 120 may be doped. Doping the dielectric layer 120 can achieve very low contact resistance. When CBO with semiconductors dopes small materials, the conduction band is bent and the tunneling thickness becomes thinner, and very low contact resistance can be extracted due to MIGS blocking and thin tunneling thickness. If the doping is performed on a material such as ZnO or TiO2, the conduction band is bent as shown in FIG. 9, thereby drastically reducing the tunneling thickness. FIG. 10 is a graph showing how the Schottky barrier varies according to the doping concentration of the dielectric layer and according to the thickness. When the Schottky barrier is reduced, electrons can easily pass therethrough and the contact resistance is reduced. Simulation of ZnO material with little difference between silicon and CBO shows that contact resistance is not significantly different even if the thickness is increased to some extent. However, it can be seen that as the doping concentration of ZnO increases, the contact resistance decreases.

Since the dielectric layer 120 is mostly composed of an oxide layer, if the doping is performed by a general semiconductor doping process, the dielectric layer is broken and the desired function of the present invention can not be achieved. Therefore, if plasma doping is performed, an oxygen depletion layer is formed and doping can be performed while maintaining the characteristics of the dielectric layer. In case of ZnO, if aluminum-doped ZnO (AZO) can be deposited, high-doping can be performed at the same time as deposition, which facilitates the process. However, when AZO materials are deposited by sputtering or evaporation, their characteristics are not good and it is preferable to use ALD, which is a chemical vapor deposition method.

FIG. 11 is a diagram illustrating the introduction of MIS structure to the source and drain of the MOSFET structure which is the most basic semiconductor device. In this way, inserting the dielectric layer intercepts MIGS by the metal, joining to the point corresponding to the work function of the metal, and eventually creating a low Schottky barrier.

The source and drain ohmic contact technology using the MIS structure according to the embodiment of the present invention can be realized by a low-temperature process, and the MIS structure using the low-temperature process method can be manufactured and applied to various semiconductor devices, Dimensional integrated technology. The MIS structure according to the embodiment of the present invention is not limited to a general MOSFET structure but can be applied to a semiconductor device (for example, a FinFET, a HEMT, or a JFET) requiring a source and a drain. Al2O3, SiN, ZrO2 and the like can be used for the dielectric layer material having a large band gap energy.

12 is a flow chart of a method of fabricating a semiconductor structure according to an embodiment of the present invention.

Step 1210 is a step of laminating a dielectric layer on the semiconductor layer.

More specifically, it is a step of laminating a dielectric layer at a position where a source or a drain is to be formed on the semiconductor layer. The dielectric layer may be deposited through an atomic layer deposition process (ALD). The dielectric layer may be formed of a material having a semiconductor layer and a conductive band offset (CBO) below the critical value. The dielectric layer may be formed of a material having a bandgap energy of a threshold value or more. The dielectric layer may be formed to a thickness that minimizes the contact resistance. The detailed description of this step corresponds to the detailed description in Figs. 1 to 11, and a duplicate description will be omitted.

Step 1220 is a step of laminating a metal layer forming a source or a drain on the dielectric layer.

More specifically, metal layers forming a source or a drain are stacked on a dielectric layer to form a source or a drain of the semiconductor element. In the case where the semiconductor is an n-type semiconductor, the metal layer is formed of a metal having a difference between the electron affinity of the semiconductor layer and a threshold value, and when the semiconductor is a p-type semiconductor, the sum of the electron affinity and the band gap energy May be formed of a metal having a difference from a threshold value or less. The detailed description of this step corresponds to the detailed description in Figs. 1 to 11, and a duplicate description will be omitted.

13 is a flowchart of a method of manufacturing a semiconductor structure according to another embodiment of the present invention.

Step 1310 is a step of doping the dielectric layer.

More specifically, the dielectric layer can be doped to further lower the contact resistance. In performing doping, plasma doping may be performed. The detailed description of this step corresponds to the detailed description in Figs. 1 to 11, and a duplicate description will be omitted.

As described above, the present invention has been described with reference to particular embodiments, such as specific elements, and specific embodiments and drawings. However, it should be understood that the present invention is not limited to the above- And various modifications and changes may be made thereto by those skilled in the art to which the present invention pertains.

Accordingly, the spirit of the present invention should not be construed as being limited to the embodiments described, and all of the equivalents or equivalents of the claims, as well as the following claims, belong to the scope of the present invention .

110: semiconductor layer
120: Dielectric layer
130: metal layer

Claims (13)

1. A semiconductor element in which a source or a drain is formed,
A semiconductor layer;
A metal layer forming a source or a drain of the semiconductor element; And
And a dielectric layer formed between the metal layer and the semiconductor layer,
The dielectric layer is doped through an atomic layer deposition process (ALD)
Wherein the ohmic contacts of the source and the drain are implemented in a low temperature process by the structure in which the doped dielectric layer is inserted into the source and drain contacts and the contact resistance is lowered by the low temperature process than when the dielectric layer is non- . delete The method according to claim 1,
Wherein,
And a conductive band offset (CBO) with the semiconductor layer is less than or equal to a threshold value. The method according to claim 1,
Wherein,
And is formed of a material having a bandgap energy of a threshold value or more. The method according to claim 1,
Wherein,
And is formed to have a thickness that minimizes the contact resistance. delete The method according to claim 1,
The metal layer may include,
When the semiconductor is an n-type semiconductor, a difference between the electron affinity of the semiconductor layer and the metal is less than a threshold value,
Wherein when the semiconductor is a p-type semiconductor, the difference between the electron affinity and the band gap energy of the semiconductor layer is less than or equal to a threshold value. A method of forming a source or a drain in a semiconductor device,
Stacking a dielectric layer on the semiconductor layer;
Performing doping on the dielectric layer; And
And laminating a metal layer forming a source or a drain on the dielectric layer,
The dielectric layer is doped through an atomic layer deposition process (ALD)
The ohmic contact between the source and the drain is implemented by a low-temperature process by the structure in which the doped dielectric layer is inserted into the source and drain contacts, and the contact resistance is lowered than in the case where the dielectric layer is undoped only by the low-temperature process. delete delete 9. The method of claim 8,
Wherein,
Wherein the semiconductor layer and the conductive band offset (CBO) are formed of a material that is below a threshold. 9. The method of claim 8,
Wherein,
Gt; is formed of a material having a bandgap energy of at least a threshold value. 9. The method of claim 8,
Wherein,
Wherein the contact resistance is formed to a thickness that minimizes the contact resistance.


KR1020150025561A 2015-02-24 2015-02-24 Metal-Interlayer-Semiconductor Structure on Source/Drain Contact for Low Temperature Fabrication with Monolithic 3D Integration Technology and Manufacturing Method KR101794192B1 (en)

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Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130127015A1 (en) * 2011-09-20 2013-05-23 Intermolecular, Inc. Band Gap Improvement In DRAM Capacitors

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101048996B1 (en) * 2009-01-12 2011-07-12 삼성모바일디스플레이주식회사 Thin film transistor and flat panel display having same
US10304826B2 (en) * 2012-12-28 2019-05-28 Taiwan Semiconductor Manufacturing Company Complimentary metal-oxide-semiconductor (CMOS) with low contact resistivity and method of forming same
US8927418B1 (en) * 2013-07-18 2015-01-06 Taiwan Semiconductor Manufacturing Company Limited Systems and methods for reducing contact resistivity of semiconductor devices

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130127015A1 (en) * 2011-09-20 2013-05-23 Intermolecular, Inc. Band Gap Improvement In DRAM Capacitors

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
비특허문헌 1(2011, 4)*

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