KR101793838B1 - Noise enhanced low power receiver using shared bias power supply - Google Patents

Abstract

Disclosed is a power receiver with improved noise characteristics sharing a bias power source. The power receiver according to an embodiment of the present invention includes a first converter for converting an RF signal, and a second converter for generating a base band signal based on an output signal of the first converter. The first converter and the second converter share a common bias current. The first converter includes a matching circuit including an inductor for performing at least one of power matching and noise matching. Accordingly, the present invention can reduce a 1/f noise.

Description

TECHNICAL FIELD [0001] The present invention relates to a power receiver having improved noise characteristics sharing a bias current,

The following embodiments relate to a power receiver with improved noise characteristics sharing bias power.

Receivers that receive radio frequencies in wireless communication devices such as cell phones, smart phones, tablet PCs, and healthcare systems are known as low-noise transconductors (LNGMs), current-mode passive mixers, and transimpedance amplifiers A configured receiver RF front-end structure may be used.

However, this structure has a problem in that it is not suitable for applications requiring low power because three independent blocks consume power each.

Embodiments can provide a technique of sharing 1 / f noise by sharing a bias current.

In addition, the embodiments can provide a technique for performing input power matching and noise matching using a matching circuit.

A receiver according to one side includes a first converter for converting an RF signal and a second converter for generating a baseband signal based on an output signal of the first converter, The second converter shares a common bias supply, and the first converter may include a matching circuit including an inductor for performing at least one of power matching and noise matching.

The matching circuit may be connected between the first transistor and the second transistor included in the first converter.

The matching circuit may be connected between the source of the first transistor and the source of the second transistor.

The matching circuit may further include a capacitor, and the inductor and the capacitor may be in series.

In the RF frequency domain, the second transducer acts as a load of the first transducer, and in the baseband frequency domain, the first transducer acts as a load of the second transducer.

Wherein the first converter is connected between each of the first transistor and the second transistor included in the first converter and a ground and includes a circuit element for removing flicker noise generated in the first transistor and the second transistor, And the impedance of the circuit element may be greater than the impedance of the inductor.

The circuit element may be implemented as at least one of a current source and a resistor.

The communication device according to one side may include the receiver and an antenna for transmitting the RF signal to the receiver.

1 is a schematic block diagram of a communication device according to one embodiment.
2 is a schematic structural view of the receiver shown in Fig.
3A and 3B are views for explaining an example of the circuit element shown in FIG.
FIG. 4 is a diagram for explaining an example of the matching circuit shown in FIG. 2. FIG.
5A shows an example of an equivalent circuit of a receiver according to an example of the operation of a matching circuit according to a frequency change.
5B shows another example of the equivalent circuit of the receiver according to another example of the operation of the matching circuit different from the frequency change.

It is to be understood that the specific structural or functional descriptions of embodiments of the present invention disclosed herein are presented for the purpose of describing embodiments only in accordance with the concepts of the present invention, May be embodied in various forms and are not limited to the embodiments described herein.

Embodiments in accordance with the concepts of the present invention are capable of various modifications and may take various forms, so that the embodiments are illustrated in the drawings and described in detail herein. However, it is not intended to limit the embodiments according to the concepts of the present invention to the specific disclosure forms, but includes changes, equivalents, or alternatives falling within the spirit and scope of the present invention.

The terms first, second, or the like may be used to describe various elements, but the elements should not be limited by the terms. The terms may be named for the purpose of distinguishing one element from another, for example without departing from the scope of the right according to the concept of the present invention, the first element being referred to as the second element, Similarly, the second component may also be referred to as the first component.

It is to be understood that when an element is referred to as being "connected" or "connected" to another element, it may be directly connected or connected to the other element, . On the other hand, when an element is referred to as being "directly connected" or "directly connected" to another element, it should be understood that there are no other elements in between. Expressions that describe the relationship between components, for example, "between" and "immediately" or "directly adjacent to" should be interpreted as well.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The singular expressions include plural expressions unless the context clearly dictates otherwise. In this specification, the terms "comprises ", or" having ", and the like, are used to specify one or more of the features, numbers, steps, operations, elements, But do not preclude the presence or addition of steps, operations, elements, parts, or combinations thereof.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Terms such as those defined in commonly used dictionaries are to be interpreted as having a meaning consistent with the meaning of the context in the relevant art and, unless explicitly defined herein, are to be interpreted as ideal or overly formal Do not.

Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. However, the scope of the patent application is not limited or limited by these embodiments. Like reference symbols in the drawings denote like elements.

1 is a schematic block diagram of a communication device according to one embodiment.

Referring to FIG. 1, the communication apparatus 100 may include an antenna ANT and a receiver 200.

The communication device 100 may be a low power mobile communication device or an ultra low delay communication device that performs communication in a wireless communication environment. For example, the communication device 100 may be implemented in 3GPP (3 ^rd Generation Partnership Project), Long-Term Evolution (LTE), LTE-Advanced (LTE-A), 3GPP2 and World Interoperability for Microwave Access have.

The communication device 100 may be implemented as a portable electronic device. For example, the portable electronic device may be a laptop computer, a mobile phone, a smart phone, a tablet PC, a mobile internet device (MID), a personal digital assistant (PDA) an enterprise digital assistant, a digital still camera, a digital video camera, a portable multimedia player (PMP), a personal navigation device or a portable navigation device (PND), a handheld game console, , an e-book, a smart watch, or a smart band.

The receiver 200 may receive an RF signal via an antenna ANT. That is, the antenna ANT can receive the RF signal and transmit it to the receiver 200. The RF signal may be a high frequency signal used for wireless communication. At this time, the receiver 200 may perform an overall operation for receiving the RF signal.

The receiver 200 may also generate a baseband signal based on the RF signal and transmit the baseband signal to other circuitry (e.g., ADC, modem circuitry, etc.) for communication included in the communication device 200 have.

The receiver 200 may include a first converter 210, a mixer 230, and a second converter 250. That is, the receiver 200 may be a receiver structure of an RF front-end structure including a plurality of transducers 210 and 250 and a mixer 230.

At this time, the first converter 210, the second converter 250, and the mixer 230 may share a common bias power supply VDD. That is, the power consumption of each of the components 210, 230, and 250 can be reduced by sharing the common (or one) bias power supply VDD in each of the components 210, 230, and 250 in the receiver 200 . Thus, the receiver 200 can operate with low power.

The first converter 210 may convert the RF signal. For example, the first converter 210 may convert the RF signal into a current signal or a voltage signal. Also, the first converter 210 may amplify and output the converted current signal or voltage signal. The first transducer 210 may be a low noise transconductor (LNGM) or a low noise amplifier (LNA).

The mixer 230 may convert the frequency using the output signal of the first converter 210. In this case, the mixer 230 may be an active mixer or a passive mixer. In addition, the mixer 230 may operate in a voltage mode or a current mode.

The second converter 230 may generate a baseband (or baseband) signal based on the output signal of the first converter 210, e.g., the output signal frequency-converted by the mixer 230. [ For example, the second converter 250 may be a Transimpedance Amplifier (TIA).

Each configuration 210, 230, and 250 in the receiver 200 may share a common (or one) bias current so that each configuration 210, 230, and 250 can operate simultaneously. In this structure, the receiver 200 operates as a TIA in the baseband frequency domain, reduces the influence of 1 / f noise, operates as an LNA in the RF frequency domain, and simultaneously performs power matching and noise matching. Can be performed.

Fig. 2 is a schematic structural view of the receiver shown in Fig. 1, Figs. 3a and 3b are views for explaining an example of the circuit elements shown in Fig. 2, Fig. 4 is a cross- Fig.

2 to 4, the first converter 210 includes a plurality of transistors M _N1 and M _N2 , a plurality of circuit elements 210-5 and 210-6, a matching circuit 210 -3), and a plurality of capacitors C _EX .

A plurality of transistors (M _N1, M _N2) may be NMOS (N channel Metal Oxide Semiconductor) transistor for converting the RF signal into a current.

The gate of the first NMOS transistor M _N1 and the gate of the second NMOS transistor M _N2 may be connected to each other. The input voltages V _RFM and V _RFP may be connected in parallel between the gate of the first NMOS transistor M _N1 and the gate of the second NMOS transistor M _N2 .

The plurality of circuit elements 210-3 and 210-5 can eliminate 1 / f noise, for example, flicker noise. 1 / f noise can occur in claim 1 NMOS transistors (M _N1) and the 2 NMOS transistors (M _N2). At this time, result in claim 1 NMOS transistors (M _N1) and the 2 NMOS transistors (M _N2) using a short channel (short channel), will convert the RF signal to a current, a large 1 / f noise (or flicker noise) . 1 / f noise increases as the frequency decreases, and 1 / f noise appearing in the low frequency region below 100 kHz is referred to as flicker noise.

Thus, the first circuit element 210-3 may remove the 1 / f noise generated by the first NMOS transistor is connected between the (M _N1) and the ground (ground), a first NMOS transistor _(N1 M) . In addition, the second circuit element (210-5), the second is connected between the NMOS transistors (M _N2) and the ground (ground), the second NMOS transistor 1 / f noise generated from the (M _N2) (or flicker noise) Can be removed.

3A and 3B, the plurality of circuit elements 210-3 and 210-5 may be implemented as at least one of the current source I _B and the resistor R _Deg .

The matching circuit 210-7 may perform at least one of power matching and noise matching. In this case, the matching circuit (210-7) may be connected between the NMOS transistor 1 (M _N1) and the 2 NMOS transistors (M _N2). For example, the matching circuit (210-7) may be connected between the source of the NMOS transistor 1 and the source 2 NMOS transistors (M _N2) of the (M _N1).

The matching circuit 210-7 may include an inductor for performing at least one of power matching and noise matching. As shown in FIG. 4, the matching circuit 210-7 may be implemented with at least one capacitor C _RF and an inductor (L _Deg ). At least one capacitor C _RF and an inductor L _Deg may be connected in series.

The output signal of the first transducer 210 may be transmitted to the mixer 230 via the coupling capacitor C _M and may be frequency converted by the mixer 230 and transmitted to the second transducer 250.

The second converter 250 may include a plurality of PMOS transistors M _P1 and M _P2 , a first capacitor C _FILTER , and a plurality of resistors R _FL .

The source of the first PMOS transistor M _P1 may be connected to the bias power supply VDD and the drain thereof may be connected to the drain of the first NMOS transistor M _N1 . The source of the second PMOS transistor M _P2 may be connected to the bias power supply VDD and the drain thereof may be connected to the drain of the second NMOS transistor M _N2 . The bias power supply VDD may be a bias current or a bias voltage.

The first capacitor C _FILTER may be connected between the first PMOS transistor M _P1 and the second PMOS transistor M _P2 .

The first resistor R _FL may be coupled in a feedback manner to the drain and gate of the first PMOS transistor M _P1 . The second resistor R _FL may also be coupled in feedback form to the drain and gate of the second PMOS transistor M _P2 . At this time, one end of the first resistor R _FL and one end of the second resistor R _FL may be connected to the mixer 230.

The baseband signals generated by the second converter 250, for example, the amplified voltage signals V _BBOM and V _BBOP , may be output through the output terminals OUT1 and OUT2. The first output terminal OUT1 is located between the drain of the first NMOS transistor M _N1 and the drain of the first PMOS transistor M _P1 and the second output terminal OUT2 is located between the drain of the first NMOS transistor M _N2 Drain and the drain of the second PMOS transistor M _P2 .

The sources of the PMOS transistors M _P1 and M _P2 are connected to the bias power supply VDD and the drains of the PMOS transistors M _P1 and M _P2 are connected to the NMOS transistors M _N1 and M _N2 , M _N2 ), the first converter 210 and the second converter 250 can share a common bias power supply (VDD).

In such a structure, the at least one capacitor (C _RF) and an inductor (L _Deg) matching the source and the 2 NMOS transistors (M _N2) of the circuit (210-7) of claim 1 NMOS transistors (M _N1) containing the The receiver 200 operates as a TIA in the baseband frequency domain and reduces the influence of 1 / f noise and operates as an LNA in the RF frequency domain while at the same time performing power matching and noise matching ) Can be performed.

In the RF frequency domain, the second converter 250 operates as a load of the first converter 210, and the first converter 210 can convert the RF signal. At this time, 1 / f noise may not have a significant influence on the first transducer 210. The 1 / f noise can be increased to a higher frequency when mixed by the mixer 230. Rather, in the RF frequency domain, the first converter 210 may perform power matching and noise matching simultaneously through the matching circuit 210-7.

In the baseband frequency domain, a first converter 210 may operate as a load on a second converter 250 and a second converter 250 may generate a baseband signal. The drains of the NMOS transistors M _N1 and M _N2 operate as baseband output nodes and the RF signal and the baseband signal coexist in the drains of the NMOS transistors M _N1 and M _N2 . That is, the second converter 250 can directly receive the influence of the 1 / f noise generated in each of the NMOS transistors M _N1 and M _N2 . At this time, in the baseband frequency domain, the 1 / f noise can be removed by the degeneration effect in the first converter 210 operating as a load, for example, by a plurality of circuit elements 210-3 and 210-5 have.

The operation of the receiver 200 in the RF frequency domain and the bay-band dominant domain as described above is performed by a matching circuit 210 located between the source of the first NMOS transistor M _N1 and the source of the second NMOS transistor M _N2 -7). ≪ / RTI >

In this case, the matching circuit (210-7), the inductor (L _Deg) and the capacitor (C _RF) series impedance in the baseband frequency domain, that is, the current source (I _B of a plurality of circuit devices (210-3 and 210-5) of the ) Or the resistance (R _Deg ), and may be small in the RF frequency domain.

Hereinafter, the operation of the matching circuit 210-7 according to the frequency change and the structure and operation of the receiver 200 will be described in detail.

5A shows an example of an equivalent circuit of a receiver according to an example of the operation of a matching circuit according to a frequency change.

5A, it is assumed that the receiver 200 operates in the baseband frequency domain. Referring to FIG. 5A, the impedance of the capacitor C _RF of the matching circuit 210-7 in the baseband frequency domain may be infinite. That is, in the baseband frequency domain, the capacitor C _RF is the same effect as open.

For example, the 1 NMOS transistors (M _N1) of the source 2 and the NMOS transistors (M _N2) of the source in the plurality of element circuits (210-3 and 210-5), for example, a current source (I _B) or Only the resistor (R _Deg ) can be seen. At this time, the receiver 200 may appear to operate as a TIA. The receiver 200 can be distinguished as an amplifier portion and a load portion where the second converter 250 can operate as an amplifier and the first converter 210 can operate as a load of the second converter 250 .

A plurality of circuit devices (210-3 and 210-5), that is, the current source (I _B) or resistance drain (or the first output terminal) of the first NMOS transistors (M _N1) according to the degeneration of the effect _(Deg R) and The 1 / f noise (or flicker noise) at the drain (or the second output end) of the second NMOS transistor M _N2 can be reduced.

The frequency domain is not limited to the baseband frequency domain but may be a low frequency, for example, a frequency domain around DC.

5B shows another example of the equivalent circuit of the receiver according to another example of the operation of the matching circuit different from the frequency change.

In FIG. 5B, it is assumed that the receiver 200 operates in the RF frequency domain. Referring to FIG. 5B, the impedance of the capacitor C _RF of the matching circuit 210-7 in the RF frequency domain can be approximated to zero or to zero. That is, in the RF frequency domain, the capacitor C _RF has the same effect as being shorted, and the impedance of the matching circuit may be smaller than the impedance of the plurality of circuit elements connected in parallel.

The impedance of the matching circuit (210-7) is an inductor and the impedance (L _Deg), the impedance of a plurality of circuit devices (210-3 and 210-5), for example, a current source (I _B) or the resistance (R _Deg) may only be considered greater than the impedance of the inductor (L _Deg), the inductor (L _Deg).

That is, only the inductor L _Deg of the matching circuit 210-7 can be seen at the source of the first NMOS transistor M _N1 and the source of the second NMOS transistor M _N2 .

At this time the receiver 200 may operate as an inductor source degenerated differential LNA and the second converter 250 may operate as a load of the first converter 210 have.

The receiver 200 may simultaneously perform power matching and noise matching through an inductor (L _Deg ).

The apparatus described above may be implemented as a hardware component, a software component, and / or a combination of hardware components and software components. For example, the apparatus and components described in the embodiments may be implemented within a computer system, such as, for example, a processor, a controller, an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA) , A programmable logic unit (PLU), a microprocessor, or any other device capable of executing and responding to instructions. The processing device may execute an operating system (OS) and one or more software applications running on the operating system. The processing device may also access, store, manipulate, process, and generate data in response to execution of the software. For ease of understanding, the processing apparatus may be described as being used singly, but those skilled in the art will recognize that the processing apparatus may have a plurality of processing elements and / As shown in FIG. For example, the processing unit may comprise a plurality of processors or one processor and one controller. Other processing configurations are also possible, such as a parallel processor.

The software may include a computer program, code, instructions, or a combination of one or more of the foregoing, and may be configured to configure the processing device to operate as desired or to process it collectively or collectively Device can be commanded. The software and / or data may be in the form of any type of machine, component, physical device, virtual equipment, computer storage media, or device , Or may be permanently or temporarily embodied in a transmitted signal wave. The software may be distributed over a networked computer system and stored or executed in a distributed manner. The software and data may be stored on one or more computer readable recording media.

The method according to an embodiment may be implemented in the form of a program command that can be executed through various computer means and recorded in a computer-readable medium. The computer-readable medium may include program instructions, data files, data structures, and the like, alone or in combination. The program instructions to be recorded on the medium may be those specially designed and configured for the embodiments or may be available to those skilled in the art of computer software. Examples of computer-readable media include magnetic media such as hard disks, floppy disks and magnetic tape; optical media such as CD-ROMs and DVDs; magnetic media such as floppy disks; Magneto-optical media, and hardware devices specifically configured to store and execute program instructions such as ROM, RAM, flash memory, and the like. Examples of program instructions include machine language code such as those produced by a compiler, as well as high-level language code that can be executed by a computer using an interpreter or the like. The hardware devices described above may be configured to operate as one or more software modules to perform the operations of the embodiments, and vice versa.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. For example, it is to be understood that the techniques described may be performed in a different order than the described methods, and / or that components of the described systems, structures, devices, circuits, Lt; / RTI > or equivalents, even if it is replaced or replaced.

Therefore, other implementations, other embodiments, and equivalents to the claims are also within the scope of the following claims.

Claims (8)

A first converter for converting an RF signal; And
A second converter for generating a baseband signal based on an output signal of the first converter,
Lt; / RTI >
Wherein the first transducer and the second transducer share a common bias power,
Wherein the first converter comprises:
A first transistor;
A second transistor;
A matching circuit connected between a source of the first transistor and a source of the second transistor, the matching circuit including an inductor and a capacitor for performing power matching and noise matching;
A first circuit element connected between the first transistor and a ground; And
And a second circuit element connected between the second transistor and the ground
Lt; / RTI >
Wherein the first circuit element and the second circuit element remove flicker noise.
delete delete The method according to claim 1,
Wherein the inductor and the capacitor are in series.
The method according to claim 1,
In the RF frequency domain, the second transducer acts as a load of the first transducer,
In the baseband frequency domain, the first transducer acts as a load of the second transducer
receiving set.
The method according to claim 1,
Wherein an impedance of the first circuit element and an impedance of the second circuit element are respectively greater than an impedance of the inductor.
The method according to claim 1,
Wherein the first circuit element is implemented as at least one of a current source and a resistor,
And the second circuit element is implemented as at least one of the current source and the resistor.
A receiver as claimed in claim 1; And
An antenna for transmitting the RF signal to the receiver
.

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