KR101784499B1 - Apparatus and method for fault tolerlant routing in voltage-frequency-island networks-on-chip, voltage-frequency-island networks-on-chip using the same - Google Patents

Abstract

In a routing design of a voltage-frequency-island (VFI) network-on-chip (NoC), VFI NoC provides a path between a plurality of cores, a plurality of routers matched by the cores, , Wherein a plurality of cores and routers are zoned into two or more zones each using a different voltage and frequency, and the consumed energy value per bit per packet of data according to the traffic characteristic of any application and a different Calculating an optimal path having a minimum energy consumption value based on the additional energy consumption by the communication between the zones, calculating at least one bypass path for each router assuming a failure for each link passing through the optimal path, And stores at least one bypass route in the routing table of the router.

Description

TECHNICAL FIELD The present invention relates to an apparatus and method for designing a fault-tolerant routing of a network-on-chip in a voltage-frequency-zone system, and a network-on-chip in a voltage-frequency-zone system using the same. BACKGROUND OF THE INVENTION 1. Field of the Invention , VOLTAGE-FREQUENCY-ISLAND NETWORKS-ON-CHIP USING THE SAME}

The present invention relates to an apparatus and a method for designing a routing for fault tolerant in a network-on-chip (NoC) to which a voltage-frequency-island (VFI) And VFI NoC to which this is applied.

As many-core processors become popular, communication performance between cores is becoming a dominant factor in overall chip performance and power consumption. Accordingly, a network-on-chip (NoC) based packet switching communication considering scalability has been proposed. In addition, a voltage-frequency-island (VFI) low-power design technique is being applied to segment a specific voltage-frequency in units of tiles as the NoC general trend and the proportion of power consumption by the interconnect increase.

On the other hand, in the case of the most advanced semiconductor chip, the total length of the internal metal wiring is increased to several kilometers (km), and since the line width and the operating voltage are reduced due to the process refinement, the probability of occurrence of defects due to aging and process variation It is increasing exponentially. This is due to the delay in the development of EUV (Extreme Ultra-Violet) exposure equipment and the fact that chip fabrication by optical pattern proximity correction (OPC) is also a major factor. This has led to the need for a technology that can tolerate wiring failures in a state-of-the-art system-on-chip (SoC) of a NoC structure, and a permanent fault A variety of fault tolerant routing methods have been researched to enable the transmission of packets to a destination using a bypass route when communication is not possible.

The existing fault - tolerant routing technique can be roughly classified into two types according to the range of fault information used to find the bypass path.

The first is a technique for selecting the bypass path by searching the state of all the links constituting NoC. In this case, there is an advantage that communication can be normally performed when a path exists to a destination. However, since the entire NoC fault information is received and the path is newly updated, the implementation complexity increases, and there is a disadvantage that communication is not possible while calculating a new path and reconfiguring the routing table.

The second is a technique for selecting a bypass route by utilizing only the link state of the adjacent router. In this case, since the performance is significantly reduced when the number of broken links increases in an actual chip, it is intended to tolerate a proper number of faults. Recently, in order to mitigate the overhead of the scheme proposed in the first scheme described above, fault coverage is slightly reduced considering only the state of adjacent routers, but a simple implementation and a method of calculating the bypass path in real time Has been proposed.

However, since both of the conventional fault tolerance techniques do not consider the VFI feature, energy consumption is increased in the VFI NoC, and the chip does not operate normally while updating the routing table. In other words, there is a lack of research on this fault tolerance technique for NoC with VFI technology for energy consumption optimization.

The VFI NoC is a structure optimized for a specific application. At the design stage, adjacent routers and processing cores are grouped into VFI regions (i.e., tiles) according to task characteristics, and different voltages and frequencies are assigned to each VFI region .

In this regard, Korean Patent Registration No. 10-1053903 entitled " Device and method for controlling voltage and frequency in network-on-chip ") discloses a method and apparatus for controlling the state of at least one link connecting processing elements (PEs) A storage unit including link configuration information constituting a path between PEs, a voltage and a clock information of a link according to a bandwidth, and a path between PEs for confirming link configuration information and transmitting data in the storage unit And a control device for controlling the voltages and the clocks of the links by determining the voltages and clocks of the links included in the path according to the bandwidth required for the PEs to transmit data, And updates the status information on the link of the storage unit using the voltage, clock, and bandwidth information of the changed links, It discloses a power control apparatus in: (Network On Chip NoC) on-chip.

In order to communicate between these VFI zones, a voltage level converter (VLC) and a mixed clock FIFO (mcFIFO) are required for each router, and additional energy consumption and delay time occur when the packet passes through it.

Therefore, VFI NoC calculates the routing path considering the application traffic pattern and additional logic. However, in the case of the existing fault-tolerant routing technique, it is only aimed at calculating the bypass route without considering the factors according to the VFI NoC environment characteristic and transmitting the packet to the destination. Therefore, if the existing fault-tolerant routing technique is applied to VFI NoC, it is possible to bypass the failed link, but it is possible to communicate. However, there is a problem that the number of packets passing through the additional logic and the probability that packets are concentrated in one place increase and energy consumption increases .

Therefore, there is a need for a method that can efficiently set the bypass path by minimizing energy consumption in the event of a fault in the VFI NoC environment.

In order to solve the problems of the prior art described above, an embodiment of the present invention provides a routing design apparatus and method for setting a path for failure tolerance in a VFI NoC, and a VFI NoC using the same.

It should be understood, however, that the technical scope of the present invention is not limited to the above-described technical problems, and other technical problems may exist.

According to an aspect of the present invention, there is provided a routing design apparatus for a voltage-frequency-island (VFI) network-on-chip (NoC) VFI NoC consists of a plurality of cores, a plurality of routers matched per core, and links forming paths between the routers, wherein the plurality of cores and routers are zoned into two or more zones each using a different voltage and frequency A memory storing a path setting program for setting a best path and a bypass path for the VFI NoC; And a processor for executing a program stored in the memory, the processor being configured to, according to the execution of the routing program, calculate a consumption energy value per bit per packet of data according to a traffic characteristic of an application, Calculating an optimal path having a minimum energy consumption value based on the additional energy consumption value, calculating at least one bypass path for each router on the assumption of failure occurrence for each link passing through the optimal path, And stores the bypass route in the routing table of the router.

According to another aspect of the present invention, a routing design method through a routing design apparatus of a voltage-frequency-island (VFI) network-on-chip (NoC) Is configured such that a plurality of cores, a plurality of routers matched per core, and links forming a path between the routers are configured, the plurality of cores and routers being zoned into two or more zones each using a different voltage and frequency, Calculating an optimal path having a minimum energy consumption value based on a consumption energy value per bit per packet of data according to a traffic characteristic of an arbitrary application and an additional consumption energy value by communication between different zones; Storing the optimal path in a router table of routers passing through the optimal path, respectively; Calculating at least one bypass path on the assumption that a failure occurs in a link between routers passing through the optimal path; And updating and storing the calculated bypass route in the router table for each router.

In addition, a voltage-frequency-island (VFI) network-on-chip (NoC) according to another aspect of the present invention includes a plurality of cores for processing application traffic, Wherein the plurality of cores and routers are segmented into two or more voltage-frequency zones that are set to use different voltages and frequencies, and each of the plurality of cores and routers is segmented into two or more voltage- Further comprising a clock, a voltage level converter (VLC), and a mixed clock FIFO (mcFIFO) for processing communications between the zones, the routers being connected to each other at a boundary of the two or more zones, And a routing table in which at least one bypass route is stored, The path is reset based on one of the detour paths of the routing table.

According to any one of the above-mentioned objects of the present invention, it is possible to design a routing capable of optimizing energy consumption in addition to failure tolerance in the VFI NoC. In other words, by considering VFI NoC and application characteristics globally, it is possible to calculate the optimal path considering energy consumption and the bypass path for failure tolerance.

In addition, in order to minimize the updating speed, which is a disadvantage of the conventional fault tolerant routing table, the VFI NoC simultaneously stores the optimum route and the bypass route in the routing table, It is possible to compensate the real time performance in resetting the path even if a link failure occurs.

FIG. 1 is a simplified view illustrating a structure of a VFI NoC and a routing designing apparatus according to an embodiment of the present invention. Referring to FIG.
FIG. 2 is a diagram for explaining a fault tolerant routing scheme according to an embodiment of the present invention. Referring to FIG.
3 is a diagram illustrating a configuration of a routing design apparatus according to an embodiment of the present invention.
4 is a diagram for explaining the structure of a routing table according to a router role in the VFI NoC according to an embodiment of the present invention.
FIG. 5 shows an example of a fault tolerant routing algorithm for calculating a routing path according to an embodiment of the present invention.
6 is a diagram for explaining a bypass path selection process for failure tolerance according to an embodiment of the present invention.
FIG. 7 is a flowchart illustrating a method for designing a fault-tolerant routing of a VFI NoC according to an embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings, which will be readily apparent to those skilled in the art. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. In order to clearly illustrate the present invention, parts not related to the description are omitted, and similar parts are denoted by like reference characters throughout the specification.

Throughout the specification, when a part is referred to as being "connected" to another part, it includes not only "directly connected" but also "electrically connected" with another part in between . Also, when an element is referred to as "comprising ", it means that it can include other elements as well, without departing from the other elements unless specifically stated otherwise.

Refers to a unit realized by hardware or software, a unit realized by using both hardware and software, and a unit includes two or more hardware Or two or more units may be realized by one hardware.

FIG. 1 is a simplified view illustrating a structure of a VFI NoC and a routing designing apparatus according to an embodiment of the present invention. Referring to FIG.

Hereinafter, an example in which a mesh topology is applied to a network-on-a-chip (NoC) (hereinafter referred to as "VFI NoC") 10 to which a voltage-frequency-division (VFI) technique according to an embodiment of the present invention is applied . However, the topology type of the VFI NoC (10) is not limited.

1, a VFI NoC 10 according to an embodiment of the present invention includes a plurality of processing cores 11 for processing tasks of an application, A link 13 that forms a transmission path for various control signals and data, a frequency change buffer 14, and a link 13 that are connected between the routers 12, A frequency change clock (not shown), and a voltage change module (not shown). In FIG. 1, mc FIFO (mixed clock FIFO) is included as the frequency change buffer 14. Although not shown, a voltage level converter (VLC) is included as a voltage change module. 1, the routing design apparatus 100 of the VFI NoC 10 according to an embodiment of the present invention is connected to each of the routers 12.

Specifically, the VFI NoC 10 may be designed to have a structure optimized for a specific application, and may be configured to tile two or more adjacent routers 12 and processing cores 11 according to a task characteristic executed in the application, , "VFI zone"), and assigns different voltages and frequencies to each VFI zone. 1, the VFI NoC 10 includes an mcFIFO 14 and a clock (not shown) between the VFI NoC 10 and the router 12 in the other VFI area, for communication between the VFI zones using different voltages and frequencies. And a VLC (not shown). That is, the mcFIFO 14, the clock (not shown), and the VLC (not shown) are connected to the routers 12 located at the boundary with other VFI zones. At this time, the mcFIFO 14, the clock (not shown) and the VLC (not shown) can be connected to the links between the routers 12 located at the boundary.

1 shows a VFI NoC 10 made up of nine cores C1 to C9 and nine routers R1 to R9 and shows these resources in two voltage-frequency zones (i.e., VFI zones) (V ₁ , F ₁ ) and the second VFI zone (VFI (V _z , F _z )).

For example, in FIG. 1, when a packet is transmitted through path A (C1->R1->R4->R7-> C7), a failure occurs in a link connecting R1 and R4, Packets are not transmitted. To solve this problem, a packet can be transmitted to a destination through a new path B (Path B: C1->R1->R2->R5->R4->R7-> C7) that bypasses the failed link. For reference, the original path A is the 1 VFI zone _{(VFI (V 1, F 1} )) would made to communicate in the new path B of claim 1 VFI zone _{(VFI (V 1, F 1} )) and the second VFI zone (VFI (V _z , F _z )).

To this end, routers 12 of the VFI NoC 10 according to an embodiment of the present invention are configured with routing tables capable of providing an optimal path in a normal link state and a detour path in a link failure occurrence, respectively. At this time, the routing design apparatus 100 calculates optimal and bypass routes for each router according to a failure-in-progress routing algorithm that minimizes the energy consumption in the VFI NoC 10, and calculates the calculated optimal route and one or more bypass routes And stores it in the routing table. At this time, when the routing design apparatus 100 stores the bypass route in all the routing tables, the complexity of implementation increases, so that the route can be stored in the minimum routing table.

On the other hand, in the VFI NoC 10, since the voltage and the frequency are differently applied to the VFI region even though the same router is used, the consumed energy differs. In addition, additional energy is consumed because it communicates with other VFI zones via the mcFIFO and VLC.

Hereinafter, the routing design apparatus 100 of the VFI NoC 10 calculates an optimal path and a bypass path in terms of energy consumption, and a method of processing a fault-tolerant routing design in which a path is calculated by considering the bandwidth limitation condition of each link Will be described in detail.

Before describing the routing designing apparatus and method of the VFI NoC 10 according to an embodiment of the present invention, a method of routing by applying a general failure tolerance technique to the VFI NoC 10 with reference to FIG. 2, A brief description will now be given of the difference between the routing methods according to the failure tolerance technique according to an embodiment of the invention.

FIG. 2 is a diagram for explaining a fault tolerant routing scheme according to an embodiment of the present invention. Referring to FIG.

FIG. 2 shows an optimal path for optimizing energy consumption and a detour path for bypassing a failed link in an example of a 5x5 VFI NoC in which the VFI region is divided into three regions. In FIG. 2, 'Src' and 'Dst' indicate the source and destination routers, respectively.

2 (a) shows an example of applying the existing fault tolerance routing technique to VFI NoC, and FIG. 2 (b) shows a case in which the fault tolerance routing considering the VFI NoC characteristic according to an embodiment of the present invention is applied .

Both schemes shown in Figures 2 (a) and 2 (b) can both forward packets to the destination router by bypassing the failed link. However, the general fault tolerant techniques such as in (a) of Figure 2, often a number of communicating with other VFI zone, VFI ₃ of the VFI zone (that is, VFI _n (V _i, F _j)) (V _3, F ₃ Is less than VFI ₂ (V ₂ , F ₂ ), the energy consumed in the bypass path is greater than in in-failure routing according to one embodiment of the present invention as in FIG. 2 (b). Therefore, in order to optimize the energy consumption when a failure occurs in the link of the VFI NoC, it is necessary to search for a path that minimizes the number of times via the mcFIFO and the VLC in addition to the route search to the destination, The path search should also be considered.

3 is a diagram illustrating a configuration of a routing design apparatus according to an embodiment of the present invention.

As shown in FIG. 3, the routing design apparatus 100 includes a memory 110 and a processor 120.

The memory 110 stores a path setting program for setting a best path and a bypass path for the VFI NoC 10. This routing program includes a fault tolerant routing algorithm as described below.

The processor 120 executes programs stored in the memory 110 and processes the procedures and operations accordingly.

At this time, in response to the execution of the routing program, the processor 120 transmits an optimal route and at least one bypass route for each of the routers 12 of the VFI NoC 10 calculated through the predetermined failure tolerance routing algorithm to each routing table .

As such, the procedure and operation performed by the processor 120 according to the execution of the routing program will be described in detail with reference to FIGS. 4 to 6 below.

First, the processor 120 according to an exemplary embodiment of the present invention provides a detailed description of the problem definition process in a fault-tolerant routing design that minimizes energy consumption.

는 매핑되어있는 코어를 의미하고,

은 각 코어와 연결된 라우터를 나타낸다. 또한

는 각 코어와 라우터가 어느 VFI 구역에 할당이 되어 있는지를 나타낸다. 또한

는 c_i와 c_j의 통신 관계를 나타내며,

는 c_i에서 c_j로 전송되는 데이터의 크기를 나타낸다.In order to efficiently allocate the routing path in VFI NoC, the voltage-frequency characteristics of each mapped core and the communication pattern between cores should be considered. Communication between these cores can be defined by the VFI NoC topology graph N (C, R, S, E). From here

Quot; refers to the mapped core,

Represents a router connected to each core. Also

Indicates which VFI zone each core and router is assigned to. Also

_Represents the communication relationship between c _i and c _j ,

_Represents the size of data transmitted from c _i to c _j .

The additional energy consumption that occurs when a packet is transmitted from the VFI NoC to another VFI zone can be expressed as Equation 1 below.

&Quot; (1) "

In Equation (1), E _CLK , E _VLC , and E _MCFIFO denote the energy consumed by the clock, VLC, and mcFIFO included in the VFI NoC (10), respectively.

In addition, energy per _bit (E _bit ) of a packet transmitted from c _i to c _j can be expressed as shown in Equation (2).

&Quot; (2) "

와

는 경유하는 링크와 라우터가 속하는 VFI 구역을 의미한다.In Equation (2), E _L.bit , E _{B .bit} , and E _{S .bit} denote the energy consumed in the link, buffer, and switch included in the VFI NoC,

Wow

Means the VFI zone to which the router belongs and the link through.

In this way, considering the energy consumption modeling result of the VFI NoC according to the embodiment of the present invention and the additional consumption energy consumed in communication with the other VFI zone, the objective function for calculating the route for optimizing the energy consumption is expressed by the following equation Can be defined together. At this time, it is possible to define an objective function capable of optimizing energy consumption by taking into account the bandwidth as well as the mcFIFO and VLC of VFI NoC.

&Quot; (3) "

In Equation (3), m denotes the number of VFI zones through which a packet is transmitted to a destination, and m is set to satisfy the bandwidth limiting condition as shown in Equation (4) below.

&Quot; (4) "

는 r_l과 r_m을 연결하는 링크의 실질적으로 사용 가능한 최대 대역폭을 의미한다. 이처럼, 대역폭 제한 조건을 적용함으로써 VFI NoC에서 패킷 간 병목 현상을 최소화할 수 있다.In Equation (4)

Means the substantially usable maximum bandwidth of the link connecting _rl and _rm . Thus, by applying bandwidth constraints, bottlenecks between packets can be minimized in VFI NoC.

Next, referring to FIG. 4, a failure-tolerant routing scheme according to an exemplary embodiment of the present invention will be described in more detail.

4 is a diagram for explaining the structure of a routing table according to a router role in the VFI NoC according to an embodiment of the present invention.

In the VFI NoC 10 according to the embodiment of the present invention, the calculated optimal path and detour path are stored in the routing table P10 in order to tolerate the failure occurring in the link. At this time, the routing table P10 is connected to each router 12 of the VFI NoC. This routing table P10 is used in the routing calculation process to determine the output port of the packet entering the input port of the router 12. [

In this way, by using the routing table P10, it is possible to omit the process of directly processing the routing calculation by each router 12, and when the packet can not be transmitted through the optimal route pre-stored in the routing table P10, To the destination. For reference, it can be assumed that the method of detecting a failure in the VFI NoC 10 according to an embodiment of the present invention detects the failure of the output port in real time in each router.

FIG. 4 shows a state in which the routing table is initialized by applying a predetermined failure tolerance routing algorithm. In FIG. 4, 'Src' denotes a start router for transmitting data, and 'Dst' denotes a destination router for receiving data. In FIG. 4, if a link failure occurs in the VFI NoC 10, a packet is transmitted to the next router through a path stored in port 1 of each router. If a failure occurs in the link, To the destination using the route stored in the destination. In FIG. 4, N, E, W, and S indicate north, east, west, and south directions, respectively, and may mean upper, right, left, and lower sides.

For example, r _A through the optimal path from r ₁ to r ₁₆ is stored in ports 1 and 2, respectively, and in case of r _B via bypass path, direction is stored only in port 2. However, in the case of r _C , the routing information for r ₁ and r ₁₆ is not stored because the routing path is not passed.

Accordingly, when an arbitrary link failure occurs in the operation of the VFI NoC 10, the process of calculating the bypass path and the updating of the routing table are omitted, and the failure is managed through the optimum path and the bypass path stored in advance do.

FIG. 5 shows an example of a fault tolerant routing algorithm for calculating a routing path according to an embodiment of the present invention.

That is, FIG. 5 illustrates a routing algorithm for a fault tolerant routing design process performed by the processor 120 according to an embodiment of the present invention.

을 이용하여 통신 관계가 존재하는 모든 코어 간 전송되는 데이터를 크기에 기준하여 내림차순 정렬한다.In this case, since the bandwidth limitation condition must be satisfied in the fault tolerance routing technique of the VFI NoC according to the embodiment of the present invention, as in the first line (line 1) of the algorithm of FIG. 5,

The data transmitted between all the cores in which the communication relation exists is sorted in descending order based on the size.

The optimal path means a path that satisfies the communication performance requirement of the network while minimizing the energy consumption in a situation where the link is not broken down. In the case of NoC that does not use VFI scheme, routing paths with the same number of hops in the case of ignoring the traffic have no difference in energy consumption or data throughput even if the packets are transmitted through any path. However, since VFI NoC generates additional energy consumption in VLC and mcFIFO when communicating to other VFI zones, it is necessary to calculate the optimal routing path by comparing all the possible paths as well as the shortest path.

Accordingly, in the algorithm shown in FIG. 5, a solution for optimizing the objective function of Equation (3) is searched to find the optimum path or the bypass path. As described above, the VFI NoC 10 according to the embodiment of the present invention calculates the routing path at the design time and stores the routing path in the routing table, so that the route re-searching process is not required when the failure occurs during the operation of the VFI NoC 10 .

A fault tolerant routing algorithm according to an embodiment of the present invention can apply a Dijkstra algorithm that is simple to implement as a shortest path algorithm. In the implementation of the shortest path algorithm, the vertex means a pair of router and core, and the energy consumption generated in the packet transmission process is used as a weight.

As in the second line (line 2) of the algorithm of Fig. 5, E _bit (r _i ) in Equation (2) is assigned to the link connecting r _i and r _j , The E _VFI of Equation (1) is additionally allocated.

를 이용하여 최적 경로를 계산하고, 선택된 경로가 경유하는 라우터의 라우팅 테이블과 링크의 대역폭을 갱신한다.In order to improve the data throughput and the algorithm speed of the VFI NoC as in the sixth line (line 6) of the algorithm of FIG. 5, if the bandwidth limitation condition of Equation (4) is not satisfied, the link is removed in the algorithm process . Thereafter, as in the seventh to ninth line (line 7-9) of Fig. 5,

, And updates the bandwidth of the link and the routing table of the router passing through the selected route.

6 is a diagram for explaining a bypass path selection process for failure tolerance according to an embodiment of the present invention.

FIG. 6 shows each step of the algorithm for calculating the bypass route in the state where the optimal route is allocated to each router in the VFI NoC (10).

First, as shown in FIG. 6A, a link removal and a candidate detour path are selected. That is, as in the 11th line (line 11) of the algorithm of FIG. 5, in order to minimize the number of routing tables for the bypass route, the link closest to the final destination router is removed in reverse order.

를 이용해 r_A와 r_B를 연결하는 경로를 탐색한다. 이에 따라, 도 6의 (a)에서와 같이 제 1 우회 경로(Path 1)과 제 2 우회 경로(Path 2)가 선정될 수 있다.Therefore, in FIG. 6A, it is assumed that there is no link (i.e., failure) with the router r _A adjacent to the final destination router r _B on the optimal route. At this time, as in the twelfth line (line 12) of the algorithm of FIG. 5,

To find routes connecting r _A and r _B. Accordingly, the first bypass path (Path 1) and the second bypass path (Path 2) can be selected as shown in FIG. 6 (a).

를 우회 경로로 선택한다.6 (b), in order to minimize the number of bypass paths as in the 13th and 14th lines (lines 13-14) of the algorithm of FIG. 5

As a bypass route.

로 에너지 소모가 적은 우회 경로를 선택한다.Also, if more than two candidate bypass paths are selected, as in the 16th line (line 16) of the algorithm of Figure 5,

Select a bypass path with low energy consumption.

순으로 선택될 경우 r_C처럼 동일한 목적지에 해당하는 우회 경로가 미리 존재하거나, 도 6의 (d)와 같이 경유하는 라우터의 목적지가 최종 목적지와 동일한 경우, 도 5의 알고리즘의 18번째 내지 21번째 라인(line 18-21)에서와 같이 해당 라우팅 테이블을 갱신하지 않는다.Also, if routers passing through the bypass route are selected, it is determined whether the routing table of the corresponding router is updated. As shown in FIG. 6 (c), the candidate bypass path

If the order selected by r _C a bypass path for the same destination pre-existing like or, in the case where the router destination via as in (d) of Figure 6 is equal to the final destination, and 18 of the algorithm of Figure 5 first to 21st The corresponding routing table is not updated as in the line (line 18-21).

Hereinafter, referring to FIG. 7, a method for designing a fault-tolerant routing through the routing design apparatus 100 of the VFI NoC according to an embodiment of the present invention will be described in detail.

FIG. 7 is a flowchart illustrating a method for designing a fault-tolerant routing of a VFI NoC according to an embodiment of the present invention.

First, a plurality of cores and routers are divided into a plurality of zones according to a traffic characteristic of an application, and the VFI NoC operating with different voltages and frequencies for each zone is calculated (S710).

At this time, the optimal path for each data by the traffic can be calculated using the multi-extreme shortest path algorithm.

In addition, energy per packet (i.e., E _bit (r _i ) in Equation (2)) transmitted from the starting core to the destination core is allocated to a link connecting two routers r _i and r _j in the path. At this time, when two routers are included in different VFI zones, the links connecting them are assigned the E _VFI of Equation 1, which is an additional consumption energy.

In step S710, a link that does not satisfy the bandwidth limitation condition of Equation (4) may be excluded in the calculation of the optimal path for improving the data throughput and the failure-in-progress routing algorithm.

Next, the calculated optimal path is stored in the router table of the corresponding routers passing through the optimal path, and the bandwidth per link is updated (S720).

Then, in a state where an optimal path is allocated to each router, at least one bypass path is calculated assuming that a failure occurs in a link between routers passing through the optimal path (S730).

In this case, in order to minimize the number of routing tables, it is assumed that failure occurs sequentially from the link adjacent to the final destination router in the reverse order. Also, to minimize the number of bypass routes, the bypass route is determined to pass through routers with redundant bypass routes.

If more than one candidate bypass path is selected, choose a path that consumes less energy and consumes less energy.

Then, the bypass route calculated for each router is stored in the router table (S740).

At this time, the bypass route is sequentially stored in the router table according to the calculated order. If the destination of the router or router passing through the same destination is the same as the final destination, the routing table of the corresponding router may not be updated.

Through the procedure described above, the optimum path and the bypass path can be allocated to each router for all the communication necessary for driving the application.

In this way, by storing the optimal route and bypass route minimizing the energy consumption considering the characteristics of the application in the design process of the VFI NoC in the router table for each router, even if a failure occurs in any link in the actual operation of VFI NoC, It is possible to process the traffic almost in real time without searching and resetting.

An embodiment of the present invention may be implemented in the form of a recording medium including instructions executable by a computer, such as a program module, for routing design apparatus and methods executed by a computer. Computer readable media can be any available media that can be accessed by a computer and includes both volatile and nonvolatile media, removable and non-removable media. In addition, the computer-readable medium may include both computer storage media and communication media. Computer storage media includes both volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data. Communication media typically includes any information delivery media, including computer readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave, or other transport mechanism.

It will be understood by those skilled in the art that the foregoing description of the present invention is for illustrative purposes only and that those of ordinary skill in the art can readily understand that various changes and modifications may be made without departing from the spirit or essential characteristics of the present invention. will be. It is therefore to be understood that the above-described embodiments are illustrative in all aspects and not restrictive. For example, each component described as a single entity may be distributed and implemented, and components described as being distributed may also be implemented in a combined form.

The scope of the present invention is defined by the appended claims rather than the detailed description and all changes or modifications derived from the meaning and scope of the claims and their equivalents are to be construed as being included within the scope of the present invention do.

10: Voltage-Frequency-Zone Network-on-Chip
100: Voltage-frequency-routing network-on-chip routing design device
110: Memory
120: Processor

Claims (14)

A routing design apparatus for a voltage-frequency-island (VFI) network-on-chip (NoC)
The VFI NoC comprises a plurality of cores, a plurality of routers matched by the cores, and links forming paths between the routers, wherein the plurality of cores and routers are divided into two or more zones each using a different voltage and frequency That is,
A memory storing a path setting program for setting a best path and a bypass path for the VFI NoC; And
And a processor for executing a program stored in the memory,
Wherein the processor is configured to determine, based on execution of the routing program, an optimum energy consumption value based on a consumption energy value per bit per packet of data according to a traffic characteristic of an application and an additional consumption energy value by communication between different zones, Calculating at least one bypass path for each router on the assumption that a failure occurs on a link-by-link basis via the optimal path, and calculating a bypass path for each route based on the VFI NoC of the optimum path and the at least one bypass path in the routing table of the router Routing design device.
The method according to claim 1,
The processor comprising:
Each of the routers being located at a boundary of the different zones, wherein the additional consumable energy based on a sum of each consumed energy value of a clock, a voltage level converter (VLC) and a mixed clock FIFO (mcFIFO) VFI NoC routing design device for calculating energy values.
The method according to claim 1,
The processor comprising:
The total consumed energy value based on the number of zones via which packets are transmitted between the starting router and the destination router and the consumed energy value based on the product of the data size transmitted between the core and the energy per packet bit, Calculating a path that minimizes the energy consumption value as the optimum path,
And the size of data transmitted between the cores is set to a value equal to or less than a preset bandwidth limit value.
The method according to claim 1,
The processor comprising:
And the bypass route is set assuming that a failure occurs in a reverse order from a link closest to the final destination router among the links passing through the optimal route.
The method according to claim 1,
The processor comprising:
Wherein the bypass route to the same destination among the routers whose destinations are the same as the final destination or the routers on the two or more candidate bypass routes among the routers passing through the optimal route is maintained without changing the routing table of the predetermined router.
A routing design method through a routing design apparatus of a voltage-frequency-island (VFI) network-on-chip (NoC)
The VFI NoC comprises a plurality of cores, a plurality of routers matched by the cores, and links forming paths between the routers, wherein the plurality of cores and routers are divided into two or more zones each using a different voltage and frequency That is,
Calculating an optimal path having a minimum energy consumption value based on a consumption energy value per bit per packet of data according to a traffic characteristic of an arbitrary application and an additional consumption energy value by communication between different zones;
Storing the optimal path in a router table of routers passing through the optimal path, respectively;
Calculating at least one bypass path on the assumption that a failure occurs in a link between routers passing through the optimal path; And
And updating and storing the calculated bypass route in the router table for each of the routers.
The method according to claim 6,
Wherein calculating the optimal path comprises:
Each of the routers being located at a boundary of the different zones, wherein the additional consumable energy based on a sum of each consumed energy value of a clock, a voltage level converter (VLC) and a mixed clock FIFO (mcFIFO) And calculating an energy value of the VFI NoC.
The method according to claim 6,
Wherein calculating the optimal path comprises:
The total consumed energy value based on the number of zones via which packets are transmitted between the starting router and the destination router and the consumed energy value based on the product of the data size transmitted between the core and the energy per packet bit, Calculating a path that minimizes the energy consumption value as the optimum path,
Wherein the size of the data transmitted between the cores is set to a value less than a preset bandwidth limit value.
The method according to claim 6,
Wherein the calculating the at least one bypass path comprises:
And setting the bypass path based on a failure occurring in a reverse order from a link closest to the final destination router among the links passing through the optimal route.
The method according to claim 6,
And updating and storing the calculated bypass route in the router table for each router,
Wherein the bypass route for the same destination among the routers whose destinations are the same as the final destination or the routers on the two or more candidate bypass routes among the routers passing through the optimal route is maintained without changing the routing table of the predetermined router.
In a voltage-frequency-island (VFI) network-on-chip (NoC)
A plurality of cores processing traffic of an application,
A plurality of routers matched per core, and
And a link forming a path between the routers,
Wherein the plurality of cores and routers are zoned into two or more voltage-frequency zones configured to use different voltages and frequencies,
Further comprising a clock, a voltage level converter (VLC), and a mixed clock FIFO (mcFIFO) for processing communications between the two or more zones, each of the routers connected to the two or more zones,
The plurality of routers include:
And a routing table in which an optimal path calculated according to the characteristics of the traffic and at least one bypass path are stored,
A network-on-chip voltage-frequency-area network that reestablishes a path based on one of the bypass paths in the routing table upon detecting a link failure on the path along the optimal path.
12. The method of claim 11,
Wherein the optimal path having a minimum energy consumption value calculated based on a consumed energy value per bit per packet of data according to an application traffic characteristic and an additional consumption energy value by communication between different zones is stored for each routing table, - Frequency-Zone network-on-chip.
13. The method of claim 12,
Wherein the additional consumption energy value is calculated based on a sum of the consumed energy values of the clock, VLC and mcFIFO, respectively.
13. The method of claim 12,
Based on the number of zones over which a packet is transmitted between the starting router and the destination router, for each of the routing tables, and the consumed energy value based on the product of the data size transmitted between the cores and the energy per packet bit, Wherein the optimal path is stored such that the total energy consumption value combined with energy values is minimized.

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