It is understood that the following description is provided to provide one or more different embodiments or embodiments for implementing different features of this disclosure. Specific embodiments of the components and arrangements are described below to simplify the present disclosure. These are, of course, examples only and are not intended to be limiting. In accordance with standard practice in the industry, the various features in the figures are not drawn to scale and are used for illustrative purposes only.
In some embodiments, instead of using a clock tree to distribute the clock signal to the various clocked components in an integrated circuit, two or more oscillators configured to generate an output oscillating signal having a predetermined frequency Is used. In addition, one or more synchronization mechanisms are implemented to minimize the frequency or phase difference among the oscillation signals generated by the two or more oscillators. The one or more synchronization mechanisms include magnetic coupling, master-slave fine-tuning, and pulse injection.
1 is a schematic diagram of two oscillators 100A and 100B in accordance with one or more embodiments. In some embodiments, oscillators 100A and 100B are configured to generate an oscillating signal having a predetermined frequency. In some embodiments, the frequencies of the oscillating signals from oscillators 100A and 100B are approximately the same, but are not exactly equal to the predetermined frequency. Further, in some embodiments, the phases of the oscillation signals from the oscillators 100A and 100B are not accurately synchronized. In some embodiments, synchronizing the oscillators 100A and 100B means minimizing the frequency or phase difference between the oscillating signals from the oscillators 100A and 100B. Although only two oscillators 100A and 100B are illustrated in conjunction with FIG. 1, the synchronization mechanism illustrated in this disclosure is applicable to two or more similarly configured oscillators of the same integrated circuit.
The oscillator 100A includes an inductive device 110A, a capacitive device 120A, an active feedback device 130A, a switch device 140A, an output node 152A and a complementary output node 154A. Inductive device 110A, capacitive device 120A, active feedback device 130A and switch device 140A are coupled between output node 152A and complementary output node 152B.
Active feedback device 130A includes two n-type transistors 132A and 134A. The source terminals of the transistors 132A and 134A are coupled to the ground reference node 162A. The drain terminal of the transistor 132A is coupled to the node 152A and the gate terminal of the transistor 134A and the drain terminal of the transistor 134A are coupled to the gate terminal of the node 154A and the transistor 132A. Active feedback device 130A is configured to output a first output oscillating signal at node 152A and a first complementary output oscillating signal at node 154A. The first output oscillation signal and the first complementary output oscillation signal have a predetermined frequency determined according to the electrical characteristics of the inductive device 110A and the electrical characteristics of the capacitive device 120A. In some embodiments, the inductive device 110A has an inductance of L TOTAL , the capacitive device 120A has a capacitance of C TOTAL , and the predetermined frequency FOSC (Hz) can be determined according to the equation have.
In some applications, an oscillator having a configuration similar to oscillator 100A is also known as an "LC tank oscillator ". In some embodiments, transistors 132A and 134A are p-type transistors. In some embodiments, other types of active feedback devices are also available as active feedback devices 130A.
The inductive device 110A includes an inductor 114A and an integrally formed inductor 112A as a conductive coil. Inductor 112A is coupled between node 152A and supply reference node 164A and inductor 114A is coupled between node 154A and supply reference node 164A.
Capacitive device 120A includes a coarse-tuning capacitor 122A) and a fine-tuning capacitor 124A. In some embodiments, the capacitance of the course tuning capacitor 122A is set according to a set of digital signals from the bus 126A. In some embodiments, the course tuning capacitor 122A is replaced by a set of hard wired capacitors, whereby the capacitance of the course tuning capacitor 122A is fixed, and then the bus 126A is omitted. In some embodiments, the capacitance of fine tuning capacitor 124A is set according to the analog signal from path 128A. In some embodiments, the resonant frequency of the oscillator 100A is adjustable by controlling the course tuning capacitor 122A or the fine tuning capacitor 124A.
Switch device 140A is configured to set the signal at nodes 152A and 154A at a corresponding predetermined voltage level when switch device 140A is powered on. For example, when switzerland 140A is powered up, nodes 152A and 154A are electrically coupled together. Under these circumstances, transistors 132A and 134A and inductors 112A and 114A function as voltage dividers and signals at nodes 152A and 154A are applied to the impedances of transistors 132A and 134A and inductors 112A and 114A, Is set at a voltage level that can be determined accordingly. In some embodiments, when switch device 140A is powered on, the signals at nodes 152A and 154A are set at approximately the middle of the voltage levels of supply reference node 164A and ground reference node 162A.
Switch device 140A is controlled by a signal in path 170A. In some embodiments, the control signal in path 170A is a pulse signal used to force a crossing-over of the oscillating signal at nodes 152A and 154A. Therefore, in the present application, the switch device 140A is also referred to as a reset device or a pulse injecting device. In some embodiments, the switch device 140A is a transistor. In some embodiments, switch device 140A is a p-type transistor, an n-type transistor, or a transfer gate. In some embodiments, the switch device 140A is omitted.
The oscillator 100B includes an inductive device 110B, a capacitive device 120B, an active feedback device 130B, a switch device 140B, an output node 152B and a complementary output node 154B. The oscillator 100B and the oscillator 100A have substantially the same configuration. Components of the oscillator 100B similar to those of the oscillator 100A are shown with similar reference numerals, except that the suffixes are changed from 'A' to 'B'. The features and functions of the oscillator 100B are substantially similar to those described above with respect to the oscillator 100A, and therefore the detailed description of the oscillator 100B is not repeated.
In some embodiments, the oscillator 100A and the oscillator 100B are on the same substrate, on different substrates of the same package substrate, on different substrates of the substrate stack, or on different substrates of the die stack. In some embodiments, the power distribution network is implemented so that the supply reference nodes 164A and 164B have substantially the same supply voltage level and the ground reference nodes 162A and 162B have substantially the same ground reference level. In some embodiments, the digital signals on buses 126A and 126B have the same logical value.
In some embodiments, the signals in paths 170A and 170B are provided by a distribution network based on a common signal. In some embodiments, the signals in paths 170A and 170B are synchronized signals. In some embodiments, the signals in paths 170A and 170B are pulse signals. In some embodiments, the predetermined frequency of the output oscillation signal of oscillators 100A and 100B is an integral multiple of the frequency of the signal in paths 170A and 170B.
In addition, the inductive device 110A of the oscillator 100A and the inductive device 110B of the oscillator 100B are magnetically coupled (as shown by the dotted arrow 180). The magnetic coupling between the inductive device 110A and the inductive device 110B indicates that the magnetic flux generated by operating the inductive device 110A affects the operation of the inductive device 110B and vice versa It means the same. In some embodiments, the inductive device 110A and the inductive device 110B may be fabricated on the same substrate, on different substrates on the same package substrate, in a similar manner to the locations where the oscillators 100A and 100B are located, Lt; RTI ID = 0.0 > Si, < / RTI > or on different substrates of the die stack. Inductive device 110A and inductive device 110B attenuate the out-of-phase component of the oscillating signals at node 152A of oscillator 100A and at node 152B of oscillator 100B And is configured to enhance the in-phase component. Generally, after the oscillator 100A and the oscillator 100B are enabled, the output oscillation signal at the nodes 152A and 152B is eventually stabilized to be an in-phase oscillation signal. In other words, inductive device 110A and inductive device 110B are configured to synchronize the oscillating signals generated by oscillator 100A and oscillator 100B.
In some embodiments, the inductive device 110A of the oscillator 100A and the inductive device 110B of the oscillator 100B are capable of providing enough interactions between the oscillator 100A and the oscillator 100B within a predetermined period of time - have a distance equal to or less than a predetermined distance to cause inductance. In some embodiments, the predetermined distance is one-half the wavelength of the electromagnetic wave having a predetermined frequency of the oscillation signal. In some embodiments, the predetermined frequency range of the output oscillation signal is 100 MHz to 20 GHz.
2A is a schematic diagram of a capacitor array 200 usable as a course tuning capacitor 122A or a course tuning capacitor 122B in accordance with one or more embodiments. The capacitor array 200 includes a first node 202, a second node 204, K transistors 212-I to 212-K, and 2K capacitors 222-I to 222-K and 224-I to 224 -K), where K is a positive integer. The first node 202 and the second node 204 are operable to connect to the corresponding node 152A and node 154A or to the corresponding node 152B or node 154B. The capacitors 222-I through 222-K are coupled to the first node 202 and the capacitors 224-I through 224-K are coupled to the second node 204, 212-K is coupled between the corresponding pair of capacitors 222-I through 222-K and capacitors 224-I through 224-K. The transistors 212-I to 212-K function as switches and are controlled by the control signals B [0], B [1] to B [K-1].
In some embodiments, transistors 212-I through 212-K are p-type transistors or n-type transistors. In some embodiments, transistors 212-I through 212-K are replaced by transmit gates or other types of switches. In some embodiments, capacitors 221-I to 222-K and capacitors 224-I to 224-K are metal-oxide-metal capacitors or metal-insulator-metal capacitors.
In some embodiments, one of the transistors 212-I through 212-K, including a corresponding one of the capacitors 222-I through 222-K and a corresponding one of the capacitors 224-I through 224- , The total capacitance of each path has the same value. Under these circumstances, the control signal B [0: K-1] is coded in a unary coding format. In some embodiments, the total capacitance of each path as defined above corresponds to one of 2 0 , 2 1 , ... 2 K - 1 times the predetermined unit capacitance value. Under this alternative environment, the control signal B [0: KI] is coded in a binary coding format.
Figure 2B is a schematic diagram of a varactor 250 that can be used as the fine tuning capacitor 124A or fine tuning capacitor 124B in Figure 1 in accordance with one or more embodiments. The varactor 250 includes a first node 252, a second node 254, a control node 256, and transistors 262 and 264. The first node 252 and the second node 254 are operable to be coupled with the corresponding node 152A or node 154A or coupled with the corresponding node 152B or node 154B. The transistor 262 has a drain terminal and a source terminal coupled to the first node 252. Transistor 262 has a gate terminal coupled to control node 256. The transistor 264 has a drain terminal and a source terminal coupled to the second node 254. The transistor 264 has a gate terminal coupled to the control node 256. Control node 256 is configured to receive the control signal at analog control signal V CAP , e.g., path 128A or 128B. The total capacitance between nodes 252 and 254 is adjustable in response to the voltage level of the control signal V CAP . In some embodiments, transistors 262 and 264 are p-type transistors or n-type transistors.
In Fig. 1, only two oscillators 100A and 100B are shown. However, in some embodiments, there are more than two oscillators to generate a clock in the integrated circuit. In addition, the inductive device 110A or 110B of the oscillator 100A or 100B may be magnetically coupled to more than two inductive devices of the at least two oscillators.
For example, FIG. 3 is a schematic diagram of six oscillators 300A-300F in accordance with one or more embodiments. The oscillators 300A to 300F have a configuration similar to that of the oscillator 100A described above. Among other things, oscillators 300A-300F have corresponding inductive devices 310A-310F. Other details of the oscillators 300A to 300F are omitted.
As shown in FIG. 3, inductive devices 31OA and 310B are magnetically coupled (dotted arrow 380A) and inductive devices 310B and 310C are magnetically coupled The inductive devices 310D and 310E are magnetically coupled (dotted arrow 380C) and the inductive devices 310E and 310F are magnetically coupled The inductive devices 310A and 310D are magnetically coupled (dotted arrow 380E) and the inductive devices 310B and 310E are magnetically coupled 380F), inductive devices 310C and 310F are magnetically coupled (dotted arrow 380G). In this embodiment, mutual-inductive couplings 380A-380G are configured to generate oscillating signals whose oscillators 300A-300F have approximately the same predetermined frequency and approximately the same phase.
In some embodiments, inductive devices 310A-310F are formed on the same substrate, on different substrates of the same package substrate, on different substrates of the substrate stack, or on different substrates of the die stack. In some embodiments, the distance between two of the inductive devices 310A-310F corresponding to one of the magnetic couplings 38A-380G is less than or equal to one-half the wavelength of the electromagnetic wave having a predetermined frequency to be. In some embodiments, the predetermined frequency range of the output oscillation signal is 100 MHz to 20 GHz.
4 is a functional block diagram of a set of master-slave fine tuning units 400 in accordance with one or more embodiments. The set of master-slave fine tuning units 400 is coupled to the master oscillator 402 and the slave oscillator 404 and based on the comparison of the output oscillation signals of the master oscillator 402 and the slave oscillator 404 So that the resonance frequency of the slave oscillator 404 can be controlled. 1, the slave oscillator 404 corresponds to the oscillator 100A and the resonant frequency of the slave oscillator 404 is the same as that of the fine tuning capacitor 124A ).
The set of master-slave fine adjustment units 400 includes a first phase comparator 412, a second phase comparator 414, a control unit 416, a first conductive path 422, a second conductive path 424, And includes a first frequency divider 432 and a second frequency divider 434.
A first frequency divider 432 is disposed adjacent to the master oscillator 402 and is electrically coupled to the master oscillator. The first frequency divider 432 is configured to receive the output oscillation signal CLK_M from the master oscillator 402 and to generate the reference signal CLK_MR by frequency dividing the output oscillation signal CLK_M at a predetermined rate N. [ In some embodiments, N is a positive integer. In some embodiments, the N range is 4-16. A second frequency divider 434 is disposed adjacent to the slave oscillator 402 and is electrically coupled to the slave oscillator 402. The second frequency divider 434 is configured to receive the output oscillation signal CLK_S from the slave oscillator 404 and to generate the reference signal CLK_SR by frequency dividing the output oscillation signal CLK_S at a predetermined rate N. [
In some embodiments, the first frequency divider 432 and the second frequency divider 434 are omitted, and the oscillation signals CLK_M and CLK_S are used as the reference signal CLK_MR and the reference signal CLK_SR.
The first phase comparator 412 is disposed adjacent to the master oscillator 402. The second phase comparator 414 is disposed adjacent to the slave oscillator 404. The first conductive path 422 and the second conductive path 424 are disposed between the master oscillator 402 and the slave oscillator 404. The first phase comparator 412 receives the first phase error signal 442 according to the reference signal CLK_MR from the master oscillator 402 and the reference signal from the slave oscillator 404 transmitted via the first conductive path 422, To generate a delayed version CLK_SR 'of CLK_SR. The second phase comparator 422 receives the second phase error signal 444 in accordance with the reference signal CLK_SR from the slave oscillator 404 and the reference signal from the master oscillator 402 transmitted via the second conductive path 424, To generate a delayed version CLK_MR 'of CLK_MR.
The control unit 416 is configured to generate a tuning signal V TUNE to the slave oscillator 404 in accordance with the first phase error signal 442 and the second phase error signal 444. [ In some embodiments, the tuning signal V TUNE is usable as an analog control signal V CAP in FIG. 2B or as an analog control signal to adjust the fine tuning capacitor 124A performed by path 128A in FIG.
5 is a schematic diagram of a pulse distribution network 500 in accordance with one or more embodiments. In some embodiments, the pulse distribution network 500 provides a control signal to the switch device 140A of the oscillator 100A via path 170A and a control signal to the switch device 140B of the oscillator 100B via path 170B, Lt; RTI ID = 0.0 > 140B. ≪ / RTI >
The pulse distribution network 500 includes a pulse generator 510, a driver 520, and one or more conductive paths arranged to have an H-tree configuration. Two or more oscillators 532 and 534 are coupled to two of the ends of the H-tree. In some embodiments, oscillator 532 corresponds to oscillator 100A in FIG. 1, and oscillator 532 corresponds to oscillator 100B.
The pulse generator 510 is configured to generate a usable pulse signal as a control signal for a switching device or a reset device of the corresponding oscillator. In some embodiments, the pulse signal has a pulse frequency, and the predetermined frequency of the output oscillation signal of the oscillators 532 and 534 is an integral multiple of the pulse frequency. The pulse signal is transmitted to the oscillators 532 and 534 to set the output oscillation signal at a predetermined voltage level by the corresponding switch device of the oscillator responsive to the pulse signal. Therefore, the timing of the rising edge or the falling edge of the output oscillation signal of the oscillators 532 and 534 is synchronized in accordance with the pulse signal.
The H-tree shown in FIG. 5 includes a first level conductive path 541 of one (2 0 ), two (2 1 ) second level conductive paths 543a coupled to corresponding ends of path 541 And 543b, four (2 2 ) third level conductive paths 545a, 545b, 545c and 545d coupled to corresponding ends of paths 543a and 543b, corresponding ends of paths 545a through 545d, to couple the fifth level conductive path of the fourth level conductive paths (547a to 547i), and a path corresponding coupled to 16 ((24) at the ends of the (547a to 547i) of a ring of eight (2 3) Level conductive paths 549a through 549p include fifth-level conductive paths 549a through 549p that have ends connected to the corresponding switch devices of the various oscillators. One end of the fifth level conductive path 539a through 539p is connected to the oscillator 532 and one end of the path 549b is coupled to the oscillator 534. In some embodiments, The conductive paths leading to the corresponding terminals of the fifth level conductive path 549a through 549p in the driver 520 are subjected to substantially the same delay as the pulse signal during transmission and distribution of the pulse signal. .
Driver 520 is configured to provide sufficient current drive capability to transfer the pulse signal generated by pulse generator 510 to various ends of fifth level conductive paths 549a through 549p. In some embodiments, additional drivers 552, 554, 556, and 558 are at the ends of second level conductive paths 543a and 543b. In some embodiments, additional drivers 552, 554, 556 and 558 are omitted. Additional drivers 552, 554, 556, and 558 are placed at corresponding ends of different levels of conductive paths in the H-tree.
Therefore, there are at least three different schemes for synchronizing the output oscillation signals of two or more oscillators, e.g., oscillators 100A and 100B in FIG. 1: magnetic coupling (illustrated with reference to FIGS. 1 and 3); Master-slave fine coupling (illustrated with reference to Fig. 4); And pulse injection (illustrated with reference to Figure 5) are described above. In some embodiments, two or more oscillators 100A and 100B are synchronized using magnetic coupling and a master-slave micro-adjustment mechanism. In some embodiments, two or more oscillators 100A and 100B are synchronized using a magnetic coupling and a pulse injection mechanism. In some embodiments, synchronization is achieved using magnetic coupling, master-slave fine tuning and pulse injection mechanisms.
FIG. 6 is a flow diagram of a method 600 for synchronizing an oscillator, such as the oscillators 100A and 100B described in FIG. 1, in accordance with one or more embodiments. It is understood that additional operations may be performed before, during, and / or after the method 600 shown in FIG. 6, and it is understood that only some other processes may be summarized herein.
In operation 610, the oscillator is operated to output an oscillation signal. For example, in some embodiments, the oscillator 100A is operated to output a first oscillating signal at node 152A, and the oscillator 100B is operated to output a second oscillating signal at node 152B.
In operation 620, the inductive devices of the oscillator are magnetically coupled. For example, in some embodiments, the inductive device 110A of the oscillator 100A and the inductive device 110B of the oscillator 100B are connected in series between the output oscillation signals of the oscillators 100A and 100B, And is magnetically coupled to reduce the difference or phase difference.
At operation 630, a pulse implant process is performed on various oscillators. For example, in some embodiments, a pulse implantation process is performed on the oscillator 100A and the oscillator 100B. In some embodiments, operation 630 includes generating a pulse signal (act 632), transmitting the pulse signal through a first conductive path to switch device 140A of oscillator 100A, To the switch device 130B of the oscillator 100B through the second conductive path. In some embodiments, the first conductive path and the second conductive path are configured to impose substantially the same delay on the pulse signal.
In some embodiments, operation 630 includes setting (operating 634) the first oscillating signal of oscillator 100A at a first predetermined voltage level by switch device 140A in response to the pulse signal, (Act 636) the second oscillating signal of the oscillator 100B at a first predetermined voltage level by the switch device 140B in response to the second oscillating signal.
The method proceeds to operation 640 where a master-slave fine tuning process is performed on two or more oscillators. For example, in some embodiments, a master-slave fine tuning process is performed on oscillator 100A and oscillator 100B. As shown in Figures 6 and 4, operation 640 includes generating a reference signal CLK_MR (act 642) by frequency dividing the oscillating signal from oscillator 402 or 100B at a predetermined rate, (Operation 643) by frequency dividing the oscillation signal from the oscillator 404 or 100A at a predetermined ratio.
The first phase error signal 442 is generated based on the reference signal CLK_MR and the delayed version CLK_SR 'of the reference signal CLK_SR transmitted via the conductive path 422. In operation 645, The first phase error signal 444 is generated based on the reference signal CLK_SR and the delayed version CLK_MR 'of the reference signal CLK_MR transmitted via the conductive path 424. At operation 648, a tuning signal (V TUNE ) is generated based on the first phase error signal (422) and the second phase error signal (424).
As shown in FIG. 6 and FIG. 1, at operation 649, the frequency or phase of the oscillating signal generated by the oscillator 404 or 100A is adjusted based on the tuning signal V TUNE .
In some embodiments when synchronizing the oscillators 100A and 100B of FIG. 1, either operation 630 or operation 640, or both, are omitted.
In addition, the pulse distribution network 500 and pulse injection process (operation 630) in FIG. 5 may be applied to other types of oscillators, which are not limited to LC tank oscillators. In some embodiments, the pulse injection process or pulse injection mechanism described above may also be applied to a particular type of oscillator known as ring oscillators.
For example, FIG. 7 is a schematic diagram of a ring oscillator 700 in accordance with one or more embodiments. The oscillator 700 has an output node 702 and P inverters 710-1 through 710-P, where P is an odd number. Inverters 710-1 through 710-P are connected in series. In addition, the output terminal of the final stage inverter 710-P is coupled to the output node 702, and the input terminal of the first stage inverter 710-1 is coupled to the output terminal of the inverter 710-P. The inverters 710-1 through 710-P are configured to be active feedback devices and are configured to generate an oscillating signal at the output node 702. [ The other inverter 720 has an input terminal configured to receive the pulse signal and an output terminal coupled with the first node 702. [ Inverter 720 functions as a reset device configured to set the output oscillation signal at node 704 at a predetermined voltage level in response to the pulse signal. In some embodiments, in some embodiments, two or more ring oscillators (e.g., oscillators 532 and 534 in FIG. 5), similar to oscillator 700, may be coupled to two or more ring oscillators, Are connected to various ends of a pulse distribution network similar to the pulse distribution network 500 to synchronize signals.
8 is a schematic diagram of another ring oscillator 800 in accordance with one or more embodiments. Oscillator 800 has a pair of output nodes 802 and 804 and Q differential amplifiers 801-1 through 810-Q, where Q is odd. Amplifiers 810-1 through 810-Q are connected in series. The output terminals of the final stage amplifier 810-Q are coupled to the output nodes 802 and 804 and the input terminals of the first stage amplifier 818-1 are coupled to the output terminals of the amplifier 810-Q. Amplifiers 810-1 through 810-Q are configured as active feedback devices and are configured to generate a pair of differential oscillation signals at output nodes 802 and 804. [ One of the amplifiers, such as amplifier 810-1, further includes a switch device or reset device configured to set the output terminals of the amplifier 810-1 at a predetermined voltage level in response to the pulse signal. In some embodiments, any differential amplifier between amplifiers 810-1 through 810-Q may be used for pulse signal injection. In some embodiments, two or more ring oscillators (e.g., oscillators 532 and 534 of FIG. 5) similar to oscillator 800 may be coupled to a pulse distribution network (not shown) to synchronize the output oscillation signals of two or more ring oscillators. RTI ID = 0.0 > 500, < / RTI >
9 is a plan view of a portion of a circuit 900 that includes a coupling structure 910 and corresponding first and second inductive devices 922 and 924 in accordance with one or more embodiments. In some embodiments, inductive devices 922 and 924 correspond to inductive devices 110A and 110B in FIG. 1 or inductive devices 310A through 310F in FIG. In some embodiments, the coupling structure 910 is configured to facilitate the magnetic coupling 180 of FIG. 1 or the magnetic couplings 308A-380G of FIG. In some embodiments, the coupling structure 910 is configured to facilitate the magnetic coupling 180 of FIG. 1 or the magnetic couplings 308A-380G of FIG.
The coupling structure 910 includes a first conductive loop 912, a second conductive loop 914 and a conductive path 916 electrically connecting the first conductive loop 912 and the second conductive loop 914 ≪ / RTI > The first conductive loop 912 and the second conductive loop 914 have the shape of an octagonal loop. In some embodiments, the first conductive loop 912 and the second conductive loop 914 have the shape of a polygonal or circular loop. In some embodiments, the first conductive loop 912 and the second conductive loop 914 have the shape of a polygonal loop or a circular loop. A set of first conductive loop 912, second conductive loop 914, and conductive paths 916 are formed in various interconnect layers of one or more chips. The first conductive loop 912 surrounds the first inductive device 922 as viewed from a plan view. The second conductive loop 914 surrounds the second conductive device 924 as viewed from a plan view.
The first inductive device 922 has a signal port 922a corresponding to the opening of the coil of the inductive device 922, a center of the coil 922b, and a port direction 922c. The second inductive device 924 has a signal port 924a corresponding to the opening of the coil of the inductive device 924, a center of the coil 924b, and a port direction 924c. 10, the port directions 922c and 924c indicate the same direction. In some embodiments, port directions 922c and 924c indicate different directions.
The first conductive loop 912 includes a first end 912a and a second end 912b. The second conductive loop 914 includes a first end 914a and a second end 914b. The set of conductive paths 916 includes a first conductive path 916a and a second conductive path 916b. The first conductive path 916a electrically connects the first end 912a of the first conductive loop 912 and the first end 914b of the second conductive loop 914. The second conductive path 916b electrically connects the second end 912b of the first conductive loop 912 and the second end 914b of the second conductive loop 914. The length L is defined as the length of the space between the first conductive loop 912 and the second conductive loop 914. In some embodiments, the length L is greater than 100 microns.
In some embodiments, an induced current is generated in the first conductive loop 912 in response to the first magnetic field generated by the first inductive device 922. [ The induced current is transmitted to the second conductive loop 914 through the set of conductive paths 916 and creates a second magnetic field in the second conductive loop 914. Accordingly, the mutual inductance between the first inductive device 922 and the second inductive device 924 is less dependent on the field distribution of the first magnetic field and more dependent on the second magnetic field reproduced by the induced current . As a result, the mutual inductance between the first inductive device 922 and the second inductive device 924 is greater than the inductance of the inductive device 922 and the inductive device 924, for example, when the length L is greater than or equal to 100 占 퐉, And the distance between them.
FIG. 10 is a block diagram of an apparatus according to one or more embodiments. Is a diagram of coupling factor K versus frequency between two inductive devices, such as inductive devices 922 and 924, with or without a coupling structure. Curve 1010 indicates that when no coupling structure 910 is present and the distance between inductive device 922 and inductive device 924 is set to be 1000 占 퐉, inductive device 922 and inductive device 922 924). ≪ / RTI > Curve 1020a shows the coupling coefficient K between inductive device 922 and inductive device 924 with coupling structure 910 and with length L set to 500 占 퐉 and curve 1020b Represents the coupling coefficient K when the length L is 1000 占 퐉 and the curve 1020c represents the coupling coefficient K when the length L is 2000 占 퐉 and the curve 1020d represents the coupling coefficient when the length L is 3000 占 퐉 K and the curve 1020e represents the coupling coefficient K when the length L is 5000 占 퐉. The reference line 1030 represents a K value of 0.001 ( 10-3 ).
The coupling coefficient, K,
.
M is the transconductance between the inductive devices 922 and 924, L 1 is the magnetic inductance of the first inductive device 922 and L 2 is the magnetic inductance of the first inductive device 924. If the K value is greater than 0.001 (reference line 1030), the oscillators corresponding to inductive devices 922 and 924 have significant magnetic coupling sufficient to maintain a stable phase difference therebetween. If the K value is greater than 0.001 (reference line 1030), then the oscillator corresponding to inductive devices 922 and 924 will be of sufficient importance to maintain a stable phase difference between these inductive devices 922 and 924 Magnetic coupling.
At a distance of 1000 microns, as shown by curve 1010 in FIG. 10, the configuration without coupling structure 910 can no longer guarantee sufficient magnetic coupling between inductive devices 922 and 924 none. Conversely, the curves 1020a-1020e illustrate that embodiments of the coupling structure 910 may be self-coupled between the inductive devices 922 and 924, regardless of the distance between the inductive devices 922 and 924, Lt; / RTI > 10, curves 1020a-1020e are all above the reference line 1030 for a length L set to 500, 1000, 2000, 3000, or 5000 μm, after 500 MHz.
Some possible variations in accordance with the embodiment of Fig. 9 are further illustrated with Figs. 11A-15. In some embodiments, the variation as illustrated in FIGS. 11A-15 may be combined to form another variation where the ideas match, as evidenced by FIGS. 11A-15.
11A is a top view of coupling structure 910 and corresponding inductive devices 922 and 924 in accordance with one or more embodiments. Elements which are the same as or similar to those of Fig. 9 are given the same reference numerals, and a detailed description thereof will be omitted.
In comparison to the coupling structure 910, the coupling structure 910A includes a set of conductive paths 916A instead of a set of conductive paths 916. [ The set of conductive paths 916A includes a first conductive path 916Aa and a second conductive path 916Ab. The first conductive path 916Aa and the second conductive path 916Ab are routed such that the first conductive path 916Aa intersects the second conductive path 916Ab at location 1110 as seen from a plan view perspective.
11B is a plan view of coupling structure 910B and corresponding inductive devices 922 and 924 in accordance with one or more embodiments. Elements which are the same as or similar to those of Fig. 9 are given the same reference numerals, and a detailed description thereof is omitted.
In comparison to the coupling structure 910, the coupling structure 910B includes a set of conductive paths 916B instead of a set of conductive paths 916. [ The set of conductive paths 916B includes a first conductive path 916Ba and a second conductive path 916Bb. The first conductive path 916Ba and the second conductive path 916Bb are angled in position 1120 when one of each of the first conductive path 916Ba and the second conductive path 916Bb is viewed in plan view 0.0 > angled < / RTI > corner.
11C is a top view of coupling structure 910C and corresponding inductive devices 922 and 924 in accordance with one or more embodiments. Elements that are the same as or similar to those of Fig. 9 are given the same reference numerals, and a detailed description thereof will be omitted.
In comparison to the coupling structure 910, the coupling structure 910C includes a set of conductive paths 916C instead of a set of conductive paths 916. [ The set of conductive paths 916C includes a first conductive path 916Ca and a second conductive path 916Cb. The first conductive path 916Ca and the second conductive path 916Cb are arranged such that when one of each of the first conductive path 916Ca and the second conductive path 916Cb is viewed from a plan view perspective, Lt; / RTI > Also, the first conductive path 916Ca intersects the second conductive path 916Cb at location 1130 when viewed from a plan view perspective.
12A is a plan view of a coupling structure 1210A and corresponding inductive devices 1222 and 1224 in accordance with one or more embodiments. The coupling structure 1210A includes a first set of conductive paths 1216A that electrically connect the first conductive loop 1212A, the second conductive loop 1214A, the conductive loops 1212A and 1214A, Loop 1212B, a fourth conductive loop 1214B, and a second set of conductive paths 1216B that electrically connect the conductive loops 1212B and 1214B. The first inductive device 1222 is magnetically coupled to the first conductive loop 1212A. The second inductive device 1224 is magnetically coupled to the conductive loop 1212B. The second conductive loop 1214A is magnetically coupled to the fourth conductive loop 1214B. The second conductive loop 1214A encircles the fourth conductive loop 1214B as viewed from a plan view perspective.
In some embodiments, a first inductive current is generated in the first conductive loop 1212A in response to the first magnetic field generated by the first inductive device 1222. [ The first inductive current is transmitted to the second conductive loop 1214A through the first set of inductive paths 1216A and creates a second magnetic field in the second conductive loop 1214A. The second induced current is generated in the fourth conductive loop 1214B in response to the second magnetic field. The second inductive current is transmitted to the third conductive loop 1214B through the second set of conductive paths 1216B to create a third magnetic field in the third conductive loop 1214B. Accordingly, the second inductive device 1224 is magnetically coupled to the first inductive device 1222 through the third magnetic field regenerated by the second inductive current in the third conductive loop 1214B.
12B is a top view of coupling structure 1210B and corresponding inductive devices 1222 and 1224 in accordance with one or more embodiments. The same or similar components as those of FIG. 12A are denoted by the same reference numerals, and a detailed description thereof will be omitted. Compared to the coupling structure 1210A, the second conductive loop 1214A and the fourth conductive loop 1214B are overlapped as viewed from a plan view. In other words, the second conductive loop 1214A and the fourth conductive loop 1214B have the same size and shape but are formed on different interconnect layers.
12C is a top view of coupling structure 1210C and corresponding inductive devices 1222, 1224, and 1226 in accordance with one or more embodiments. The same or similar components as those of FIG. 12A are denoted by the same reference numerals, and a detailed description thereof will be omitted. In comparison to the coupling structure 1210A, the second conductive loop 1214A and the fourth conductive loop 1214B are arranged to be magnetically coupled to the additional inductive device 1226. [ The fourth conductive loop 1214B also surrounds the second conductive loop 1214A as viewed from a plan view perspective.
12D is a top view of coupling structure 1210D and corresponding inductive devices 1222, 1224, and 1226, in accordance with one or more embodiments. The same or similar components as those of FIG. 12B are denoted by the same reference numerals, and a detailed description thereof will be omitted. In comparison to the coupling structure 1210B, the second conductive loop 1214A and the fourth conductive loop 1214B are arranged to be magnetically coupled to the additional inductive device 1226. [
12E is a top view of coupling structure 1210E and corresponding inductive devices 1222, 1224, and 1226, in accordance with one or more embodiments. The same or similar components as those of Fig. 12D are given the same reference numerals, and a detailed description thereof will be omitted. In contrast to the coupling structure 1210D, the set of conductive paths 1216B 'is used in place of the second set of conductive paths 1216B, wherein one conductive path in the set of conductive paths 1216B' Intersects the other conductive path of the set of conductive paths 1216B 'in the conductive path 1230. [
13A is a top view of coupling structure 1310A and corresponding inductive devices 1322, 1324, and 1326, in accordance with one or more embodiments. Coupling structure 1310A includes three conductive loops 1312, 1314, and 1316 electrically coupled together through a set of conductive paths 1318. [ Each conductive loop of conductive loops 1312, 1314, and 1316 is magnetically coupled to a corresponding one of inductive devices 1322, 1324, and 1326.
13B is a top view of coupling structure 1310B and corresponding inductive devices 1322, 1324, 1326, and 1327 in accordance with one or more embodiments. The same or similar components as those of FIG. 13A are given the same reference numerals, and a detailed description thereof will be omitted. Coupling structure 1310B includes four conductive loops 1312, 1314, 1316, and 1317 that are electrically coupled together through a set of conductive paths 1318. [ Each conductive loop of conductive loops 1312, 1314, 1316, and 1317 is magnetically coupled to a corresponding one of inductive devices 1322, 1324, 1326, and 1327.
14 is a plan view of coupling structure 1410 and corresponding inductive devices 922 and 924 in accordance with one or more embodiments. Elements that are the same as or similar to those of FIG. 9 are given the same reference numerals, and a detailed description thereof is omitted. Coupling structure 1410 includes two conductive loops 1412 and 1414 that are electrically coupled together through a set of conductive paths 1416. Each conductive loop of conductive loops 1412 and 1416 is magnetically coupled to a corresponding one of inductive devices 922 and 924. The inductive device 922 also surrounds the conductive loop 1412 as viewed from a plan view perspective and the inductive device 924 encloses the conductive loop 1414 as viewed from a plan view perspective.
15 is a plan view of a coupling structure 910 having shielding structures 1512 and 1514 and corresponding inductive devices 922 and 924 in accordance with one or more embodiments. Elements that are the same as or similar to those of FIG. 9 are given the same reference numerals, and a detailed description thereof is omitted. Compared with the circuit 900 of Fig. 9, the circuit shown in Fig. 15 further includes a first shielding structure 1512 and a second shielding structure 1514. [ At least a portion of the set of conductive paths 916 is between the first shielding structure 1512 and the second shielding structure 1514 as viewed from a plan view.
16 is a flow diagram of a method 1600 of magnetically coupling inductive devices in accordance with one or more embodiments. In some embodiments, the method 1600 may be used with the circuit of FIG. 9 or 12A. In some embodiments, the method 1600 may also be used in conjunction with the circuit of Figures 11A-11C, 12B-12E, or 13A-15. Additional operations may be performed prior to, during, and / or after method 1600 shown in FIG. 16, and some other processes may be described only briefly herein I have to understand.
The process begins with operation 1610 where an inductive current is generated in the first conductive loop 912 or 1212A in response to the first magnetic field of the first oscillator generated by the first inductive device 922 or 1222. [
The process proceeds to operation 1620 where the induced current is transmitted to the second conductive loop 914 or 1214A through the set of conductive paths 916 or 1216A that electrically connect the first and second conductive loops.
The process proceeds to operation 1630 where the second magnetic field is generated in response to an induced current through the second conductive loop 914 or 1214A.
12A or 12B-e, the process proceeds to operation 1640, where another induced current is generated in the third conductive loop 1214B in response to the second magnetic field .
The process proceeds to operation 1650 where the other induced current is transmitted to the fourth conductive loop 1212B through another set of conductive paths 1216B that electrically connect the third conductive loop and the fourth conductive loop.
As a result, the second inductive device 924 or 1224 of the second oscillator is magnetically coupled to the first inductive device 922 or 1222 of the first oscillator through the coupling structure 910 or 1210.
17 is a schematic diagram of an exemplary circuit 1700 in accordance with one or more embodiments. The circuit 1700 includes a pair of oscillators 1710 and 1720 and a coupling structure 1750.
Each of the oscillators 1710 and 1720 includes a plurality of differential amplifiers 1730 and a pair of differential output nodes 1760 and 1770. Each of the differential amplifiers 1730 has differential input terminals Ip and In and differential output terminals Op and On. Differential amplifiers 1730 are connected in series to form a loop. The input terminal Ip of the first differential amplifier 1730 in series and the output terminal Op of the final differential amplifier 1730 in series are connected to each other and to the output node 1760. [ The input terminal In of the first differential amplifier 1730 in series and the output terminal On of the last differential amplifier 1730 in series are connected to each other and to the output node 1770.
Each of the oscillators 1710 and 1720 includes a series of connected differential amplifiers 1730 to form a loop and each of the oscillators 1710 and 1720 may be referred to as a differential ring oscillator.
An oscillator 1710 is configured to generate an oscillating signal OS1 at an output node 1760 of the oscillator and a complementary oscillating signal COS1 at an output node 1770 of the oscillator. Similarly, an oscillator 1720 is configured to generate an oscillating signal OS2 at an output node 1760 of the oscillator and a complementary oscillating signal (COS2) at an output node 1770 of the oscillator. The frequency f of the oscillation signals OS1, OS2, COS1 and COS2 is, for example,
f = 1 / 2Nt d
Lt; / RTI >
Where N is the number of differential amplifiers 1730 and t d is the delay of the differential amplifier 1730.
Coupling structure 1750 couples capacitively oscillators 1710 and 1720. The configuration thus reduces the phase difference and the frequency difference between the oscillation signals OS1 and OS2 and reduces the phase difference and the frequency difference between the complementary oscillation signals COS1 and COS2. In this exemplary embodiment, the coupling structure 1750 includes a pair of metal strips 1780a, 1780b, a pair of capacitors 1790a, another pair of capacitors 1790b, and a metal plate 1780c do. Each of the capacitors 1790a includes a first capacitor terminal coupled to a respective one of the output nodes 1770 of the oscillators 1710 and 1720 and a second capacitor terminal coupled to the metal strip 1780a through an interconnect, And a capacitor terminal. Each of the capacitors 1790b has a first capacitor terminal coupled to an output node 1760 of each of the oscillators 1710 and 1720 and a second capacitor terminal coupled to the metal strip 1780b through an interconnect.
In some embodiments, one of the capacitors 1790a is omitted, and the output node 1770 is connected to the metal strip 1780a through an interconnect. In some embodiments, one of the capacitors 1790b is omitted, and the output node 1760 is connected to the metal strip 1780b through an interconnect.
Oscillators 1710 and 1720 are formed in the substrate. The metal strips 1780a, 1780b are disposed on the substrate and are symmetrical. Metal plate 1780c is disposed below metal strips 1780a, 1780b, is connected to ground, and is configured to separate metal strips 1780a, 1780b from the substrate. In some embodiments, the substrate is a bulk substrate. In some embodiments, the substrate is a silicon-on-insulator (SOI) substrate. Examples of materials for the metal strips 1780a and 1780b and the metal plate 1780c are Al, W, Ni, Ti, Mo, Ta, Cu, Pt, Ag, other metal materials, , ≪ / RTI > and combinations thereof.
Circuit 1700 further includes a master-slave fine adjustment unit. 20 is a schematic block diagram of an exemplary master-slave micro reconciliation unit 2000 according to one or more embodiments. The control unit 2010 of the master-slave fine adjustment unit 2000 compares the first phase error signal 442 and the second phase error signal 444 with the master-slave fine adjustment unit 400 of FIG. (V TUNE ) or a pulse signal in accordance with the first phase error signal 442 and the second phase error signal 444 based on the difference between the first phase error signal 442 and the second phase error signal 444. In an exemplary embodiment, the control unit 2010 includes first and second phase error signals 442 and 444 when the difference between the first and second phase error signals 442 and 444 is greater than the threshold value, And generates a tuning signal V TUNE according to the first and second phase error signals 442 and 444 when the difference between the first and second phase error signals 442 and 444 is below a threshold value. And generates a pulse signal. The use of the tuning signal V TUNE and the pulse signal is described in more detail below in the context of circuit 1700 of FIG. In this exemplary embodiment, master oscillator 402 and slave oscillator 404 correspond to oscillators 1710 and 1720, respectively.
17, the oscillator 1720 further reduces the frequency difference between the complementary oscillation signals COS1 and COS2 by using the frequency difference between the oscillation signals OS1 and OS2 and the tuning signal V TUNE And a first oscillator tuner (1740) configured to receive the first oscillator signal. In this exemplary embodiment, the first oscillator tuner 1740 includes a plurality of current generators 1740a and a node 1740b. Each of the current generators 1740a has an input terminal and an output terminal. The input terminals of current generator 1740a are connected to each other and to node 1740b. The node 1740b to which the tuning signal V TUNE is applied is connected to the control unit 2010 of the master-slave fine tuning unit 2000 of Fig. Each output terminal of the current generator 1740a is connected to a respective one of the differential amplifiers 1730 of the oscillator 1720.
18 is a schematic diagram of an exemplary differential amplifier, e.g., differential amplifier 1730, in accordance with one or more embodiments and a current generator 1740a of an exemplary current generator, e.g., a first oscillator tuner 1740, of an oscillator tuner.
As shown in FIG. 18, differential amplifier 1730 includes a pair of transistors 1810 and 1820, a pair of resistors 1830 and 1840, and a node 1850. In this exemplary embodiment, each of the transistors 1810 and 1820 is an N-type transistor and has a gate terminal, a drain terminal, and a source terminal. Each gate terminal of the transistors 1810 and 1820 serves as an input terminal of each of the input terminals Ip and In of the differential amplifier 1730. Each drain terminal of the transistors 1810 and 1820 serves as an output terminal of each of the output terminals On and Op of the differential amplifier 1730. The source terminals of transistors 1810 and 1820 are connected to each other and to node 1850. Each of resistors 1830 and 1840 is connected between the supply voltage and the drain terminal of each transistor of transistors 1810 and 1820.
18, current generator 1740a includes a pair of transistors 1860 and 1870 and a node 1880. [ In this exemplary embodiment, each of the transistors 1860 and 1870 is an N-type transistor and has a gate terminal, a drain terminal, and a source terminal. The gate and drain terminals of transistor 1860 are connected to each other and to node 1880. Node 1880 functions as an input terminal for current generator 1740a. The gate terminal of transistor 1870 is connected to the gate terminal of transistor 1860. The drain terminal of transistor 1870 is connected to node 1850 and serves as the output terminal of current generator 1740a. The source terminals of transistors 1860 and 1870 are connected to ground.
In operation, a tuning signal V TUNE is applied to node 1880, transistor 1860 generates a tuning current in accordance with tuning signal V TUNE , and transistor 1870 is generated by transistor 1860 Mirror current and generates a current that flows through node 1850. As the tuning current increases, the parasitic capacitance of each of the transistors 1810 and 1820, e.g., the gate-source parasitic capacitance, decreases. This reduces the charging time of the differential amplifier 1730. This alternately increases the frequencies of the oscillation signals OS2 and COS2. Conversely, when the tuning current decreases, the parasitic capacitance increases. This causes the charging time to increase. This alternately reduces the frequencies of the oscillating signals OS2 and COS2 such that the first oscillator tuner 1740 also uses the frequency difference between the oscillating signals OS1 and OS2 and the tuning signal V TUNE Thereby reducing the frequency difference between the complementary oscillation signals COS1 and COS2.
17, each of the oscillators 1710 and 1720 generates the oscillation signal OS1 and the complementary oscillation signal COS1 substantially 180 degrees out of phase with the oscillation signal OS2 using the pulse signal, And a second oscillator tuner 1745 configured to set the complementary oscillation signal COS2 substantially 180 degrees out of phase. In this exemplary embodiment, each of the second oscillator tuners 1745 includes an input terminal connected to the control unit 2010 of the master-slave fine tuning unit 2000 for receiving a pulse signal, oscillators 1710, A first output terminal connected to an input terminal Ip of each one of the last differential amplifiers 1730 and 1720 and an input terminal In of one of the last differential amplifiers 1730 of the oscillators 1710 and 1720, And a second output terminal connected to the second output terminal. In some embodiments, the first and second output terminals of the second oscillator tuner 1745 are connected to input terminals Ip, In of one of the differential amplifiers 1730 other than the last differential amplifier 1730, respectively .
19 is a schematic diagram of an exemplary second oscillator tuner, e.g., a second oscillator tuner 1745, in accordance with one or more embodiments. The second oscillator tuner 1745 includes a pair of transistors 1910 and 1920, a first node 1930, a second node 1940, and a voltage source 1950. In this exemplary embodiment, each of the transistors 1910 and 1920 is an N-type transistor and includes a drain terminal, a source terminal, and a gate terminal. Each drain terminal of the transistors 1910 and 1920 serves as a respective one of the first and second output terminals of the second oscillator tuner 1745. The source terminals of the transistors 1920 and 1920 are connected to each other and also to the first node 1930. A voltage source 1950 is coupled to the first node 1930 and is configured to generate half the common mode voltage or supply voltage of the differential amplifier 1730 in this exemplary embodiment. The gate terminals of the transistors 1910 and 1920 are connected to each other and also to the second node 1940. The second node 1940 functions as an input terminal of the second amplifier tuner 1745.
In operation, when the second node 1940 receives a pulse signal, the drain terminal of the transistor 1910 generates a first reset voltage in accordance with the pulse signal, and the drain terminal of the transistor 1920 also generates a pulse signal To generate a second reset voltage. This resets the oscillation signals OS1 and OS2 to start rising from the level of the first reset voltage and to cause the complementary oscillation signals COS1 and COS2 to start falling from the level of the second reset voltage, The second oscillator tuner 1745 synchronizes the timing of the rising edges of the signals OS1 and OS2 with the timing of the falling edges of the complementary oscillation signals COS1 and COS2 so that the oscillator signal OS1, And the complementary oscillation signal COS2 are substantially 180 degrees out of phase with each other and the oscillation signal OS2 and the complementary oscillation signal COS2 are substantially 180 degrees out of phase.
In some embodiments, the first oscillator tuner 1740 is omitted. In some embodiments, the second oscillator tuner 17445 is omitted. In some embodiments, the first and second oscillator tuners 1740 and 1745 are omitted.
In some embodiments, at least one of the transistors 1810, 1820, 1860, 1870, 1910, 1920 is a P-type transistor, a CMOS transistor, any transistor, or a combination thereof.
Circuit 1700 includes a pulse distribution network. 21 is a schematic diagram of an exemplary pulse distribution network 2100 in accordance with one or more embodiments. Compared to the pulse distribution network 500 of FIG. 5, the pulse generator 510 is omitted. The driver 520 has an input terminal 2110 connected to the control unit 2010 of the master-slave fine tuning unit 2000 and outputs a pulse signal to the various ends of the fifth level conductive paths 549a through 549b And is configured to provide sufficient current drive capability to transmit the pulse signal. In this exemplary embodiment, oscillators 532 and 534 correspond to oscillators 1710 and 1720, respectively.
22 is a flow diagram of an exemplary method 2200 of synchronizing oscillators 1710 and 1720 of circuit 1700 of FIG. 17, a first oscillator and a second oscillator of a circuit according to one or more embodiments. It is understood that additional operations may be performed prior to, during, and / or after method 2200, and some other processes may be briefly described herein.
In operation 2205, the oscillator 1710 is enabled to generate a first oscillating signal OS1 at its output node 1760 and a first complementary oscillating signal COS1 at its output node 1770, Oscillator 1720 is enabled to generate a second oscillating signal OS2 at its output node 1760 and a second complementary oscillating signal COS2 at its output node 1770. [
At operation 2210, the coupling structure 1750 capacitively couples the oscillators 1710 and 1720. Thereby, the phase difference and the frequency difference between the first oscillation signal OS1 and the second oscillation signal OS2 and the phase difference and the frequency difference between the first and second complementary oscillation signals COS1 and COS2 are reduced .
In operation 2215, the first frequency divider 432 generates the first signal CLK_MR by dividing the frequency of the reference signal CLK_M by a predetermined ratio, and the second frequency divider 434 generates the reference signal CLK_S, By dividing the frequency of the second signal (CLK_SR) by a predetermined ratio. In some embodiments, the reference signal CLK_M is the first oscillation signal OS1 and the reference signal CLK_S is the second oscillation signal OS2. In some embodiments, the reference signal CLK_M is the first complementary oscillation signal COS1 and the reference signal CLK_S is the second complementary oscillation signal COS2. In some embodiments, the first and second frequency dividers 432 and 434 are omitted and the first and second oscillation signals OS1 and OS2 or the first and second complementary oscillation signals COS1 , COS2 are used as the first and second signals CLK_MR and CLK_SR, respectively.
The first phase comparator 412 generates a first phase error signal 442 in accordance with the first signal CLK_MR and the delayed version CLK_SR 'of the second signal CLK_SR, The comparator 414 generates a second phase error signal 444 in accordance with the second signal CLK_SR and the delayed version CLK_MR 'of the first signal CLK_MR. In this exemplary embodiment, each of the phase comparators 412 and 414 is a time-to-digital converter (TDC).
When determined by the control unit 2010 of the master-slave fine adjustment unit 2000 that the difference between the first phase error signal 442 and the second phase error signal 444 is substantially equal to zero, at operation 2225 , The flow proceeds to operation 2220 again. Otherwise, flow proceeds to act 2230.
When the control unit 2010 of the master-slave fine tuning unit 2000 determines that the difference between the first phase error signal 442 and the second phase error signal 444 is greater than the threshold value at operation 2230, The flow proceeds to operation 2235. [ When the control unit 2010 of the master-slave fine adjustment unit 2000 determines that the difference between the first phase error signal 442 and the second phase error signal 444 is less than the threshold value, The flow proceeds to operation 2245. [
The control unit 2010 of the master-slave fine tuning unit 2000 at operation 2235 generates a tuning signal V TUNE in accordance with the first phase error signal 442 and the second phase error signal 444.
In operation 2240, the first oscillator tuner 1740 of the oscillator 1720 generates a tuning current in accordance with the tuning signal V TUNE and adjusts the frequency of the oscillation signals OS2 and COS2 in accordance with the tuning current. This also reduces the frequency difference between the first and second oscillation signals OS1 and OS2 and the frequency difference between the first and second complementary oscillation signals COS1 and COS2. Thereafter, the flow returns to operation 2220 again.
In operation 2245, the control unit 2010 of the master-slave fine adjustment unit 2000 generates a pulse signal in accordance with the first phase error signal 442 and the second phase error signal 444.
In operation 2250, each second oscillator tuner 1745 of oscillators 1710 and 1720 generates a first reset voltage and a second reset voltage in accordance with the pulse signal, and generates first and second oscillation signals OS1 And OS2 so as to start rising from the level of the first reset voltage and to cause each one of the first and second complementary oscillation signals COS1 and COS2 to fall from the level of the second reset voltage Lt; / RTI > Thus, the oscillation signals OS1 and COS1 are substantially 180 degrees out of phase and the oscillation signals OS2 and COS2 are substantially 180 degrees out of phase. The flow then returns to operation 2220.
In some embodiments, operation 2215 is skipped and the first and second signals CLK_MR and CLK_SR are reference signals CLK_M and CLK_S, respectively. In some embodiments, operations 2235 and 2240 are skipped. In some embodiments, operations 2245 and 2250 are skipped. In some embodiments, operations 2215-2250 are skipped.
It should be appreciated that although the circuit of FIG. 17 is illustrated with only a pair of oscillators 1710 and 1720, the number of oscillators may be increased as needed. For example, FIG. 23 is a schematic diagram of another exemplary circuit 2300 in accordance with one or more embodiments. Circuit 2300 includes two pairs of oscillators 2310, 2320, 2330, 2340 and a coupling structure 2350. Each of the oscillators 2310, 2320, 2330 and 2340 is a differential ring oscillator and includes an output node 2360 and an output node 2370 and is configured to generate an oscillating signal at output nodes 2360 and 2370 .
Coupling structure 2350 capacitively couples oscillators 2310, 2320, 2330, and 2340. In this exemplary embodiment, the coupling structure 2350 includes two pairs of series-connected metal strips 2380a, two pairs of series-connected metal strips 2380b, two pairs of capacitors 2390a, Another two pairs, and a metal plate 2380c. Each of the capacitors 2390a includes a first capacitor terminal coupled to a respective one of the output nodes 2370 of the oscillators 2310, 2320, 2330, and 2340 and a second capacitor terminal coupled to each of the metal strips 2380a through the interconnects. And a second capacitor terminal connected to the second capacitor terminal. Each of the capacitors 2390b includes a first capacitor terminal coupled to a respective one of the output nodes 2360 of the oscillators 2310, 2320, 2330, 2340 and a second capacitor terminal coupled to each of the metal strips 2380a And a second capacitor terminal connected to the second capacitor terminal.
Oscillators 2310, 2320, 2330, and 2340 are formed in the substrate. The metal strips 2380a, 2380b are disposed on the substrate and are symmetrical. Metal plate 2380c is disposed below metal strips 2380 and 2380b and is connected to ground and is configured to separate metal strips 2380a and 2380b from the substrate. In some embodiments, the substrate is a bulk substrate. In some embodiments, the substrate is an SOI substrate. Examples of the material for the metal strips 2380a and 2380b and the metal plate 2380c include Al, W, Ni, Ti, Mo, Ta, Cu, Pt, Ag, other metal materials, And combinations thereof.
From the experimental results, during operation of the oscillator of the circuit of the present disclosure, the oscillator is substantially synchronous, i. E., In phase, producing the same frequency, oscillation signal. For example, Figure 24 illustrates the oscillating signals (OS1, OS2, OS3, OS4) of the oscillators of the circuit according to one or more embodiments, e.g., the oscillating signals of the oscillators 2310, 2320, 2330, 2340 of the circuit 2300 25 is a plot of the oscillation signals OS1, OS2, OS3, OS4 of the oscillators of the circuit according to one or more embodiments, such as the oscillations 2310, 2320, 2330, 2340 of the circuit 2300, ≪ / RTI > signals. As shown in Figure 24, oscillation signals OS1, OS2, OS3, and OS4 generated by the oscillators 2310, 2320, 2330, and 2340 of the circuit 2300, when the circuit 2300 is initially operated, Have different phases. 25, the oscillation signals OS1, OS2, OS3, and OS4 generated by the oscillators 2310, 2320, 2330, and 2340 of the circuit 2300 are supplied to the initial operation of the circuit 2300 After which it is substantially synchronized and eventually stabilized during any time period of, for example, 20 nanoseconds.
The foregoing description outlines features of several embodiments in order to enable those skilled in the art to better understand aspects of the disclosure. It should be understood by those skilled in the art that the present disclosure can readily be used as a basis for designing or modifying other processes and structures to achieve the same purpose and / or to achieve the same advantages as the embodiments disclosed herein. Those skilled in the art will recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure and that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the disclosure.
