KR101768292B1 - Image sensor devices, methods of manufacture thereof, and semiconductor device manufacturing methods - Google Patents

Abstract

An image sensor element, a manufacturing method thereof, and a semiconductor device manufacturing method are disclosed. In some embodiments, a method of fabricating a semiconductor device includes bonding a first semiconductor wafer comprising a substrate and a wiring structure coupled to the substrate to a second semiconductor wafer. The method includes removing a portion of the substrate from the first semiconductor wafer to expose a portion of the interconnect structure.

Description

TECHNICAL FIELD [0001] The present invention relates to an image sensor element, an image sensor element manufacturing method, and a semiconductor device manufacturing method,

Cross reference of related application

This application is related to U.S. Patent Application No. 13 / 839,860, filed March 15, 2013, entitled " Wiring Architecture and Method ", which is incorporated herein by reference in its entirety.

Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic equipment. Semiconductor devices are typically fabricated by sequentially depositing an insulating or dielectric layer, a conductive layer, and a layer of semiconductor material on a semiconductor substrate, patterning or processing the substrate and / or various layers of material using lithography, . ≪ / RTI > Tens or hundreds of integrated circuits are typically fabricated on a single semiconductor wafer. The individual dies are singulated by cutting the integrated circuit along the scribe line. The individual dies may then be packaged separately into multi-chip modules in different types of packaging or used directly, for example, for the intended application.

The integrated circuit die is typically formed on the front side of the semiconductor wafer. The integrated circuit die may include various electronic components such as transistors, diodes, resistors, capacitors, and other components. The integrated circuit die may include various functions such as logic, memory, processor, and / or other functions.

A complementary metal oxide semiconductor (CMOS) image sensor (CIS) device is a semiconductor device used in some cameras, cellular phones, and other imaging devices. A backside illuminated (BSI) image sensor is a CIS device in which light is irradiated from the rear side of the substrate rather than the front side of the substrate. The BSI sensor can capture more image signals than front-illuminated image sensors due to the reduced reflected light in some applications.

According to some embodiments of the present invention, a method of manufacturing a semiconductor device includes bonding a first semiconductor wafer to a second semiconductor wafer, the first semiconductor wafer including a substrate and a wiring structure coupled to the substrate. A part of the substrate is removed from the first semiconductor wafer to expose a part of the wiring structure.

According to another embodiment, a method of manufacturing an image sensor element includes bonding a first semiconductor wafer including a substrate and a wiring structure coupled to the substrate to a second semiconductor wafer. A part of the substrate is removed to expose a part of the wiring structure. The first semiconductor wafer and the second semiconductor wafer are individualized to form a plurality of image sensor elements.

According to another embodiment, the image sensor element includes a first semiconductor chip, and the first semiconductor chip includes a substrate and a wiring structure disposed on the substrate. The image sensor element includes a second semiconductor chip bonded to the first semiconductor chip. A part of the wiring structure of the first semiconductor chip is exposed.

In some embodiments, the exposed portion of the interconnect structure of the first semiconductor chip is adjacent to a scribe line region, a contact pad of the interconnect structure, a plurality of contact pads of the interconnect structure, a contact pad region of the interconnect structure, And an area of the image sensor element.

BRIEF DESCRIPTION OF THE DRAWINGS For a more complete understanding of embodiments of the present invention and the advantages thereof, reference is made to the following description, taken in conjunction with the accompanying drawings, in which: Fig. In the drawings,
1 is a cross-sectional view of two semiconductor wafers joined together in accordance with some embodiments of the present invention;
2 is a cross-sectional view of a semiconductor device comprising two semiconductor wafers after a bonding process according to some embodiments;
3 is a cross-sectional view of a semiconductor device in which a portion of a substrate of one of the semiconductor wafers is removed, according to some embodiments;
Figure 4 is a top view of the semiconductor device shown in Figure 3 according to some embodiments;
5 is a cross-sectional view of a semiconductor device according to some embodiments in which one of the semiconductor wafers includes through vias therein;
FIG. 6 is a top view of a semiconductor device according to some embodiments, and FIGS. 7 and 8 are cross-sectional views of the semiconductor device;
9 and 10 are a top view and a cross-sectional view of a semiconductor device according to some embodiments;
11 and 12 are a top view and a cross-sectional view of a semiconductor device according to some embodiments;
13 and 14 are a top view and a cross-sectional view of a semiconductor device according to some embodiments;
15 is a flowchart of a method of manufacturing a semiconductor device according to some embodiments of the present invention.
Corresponding reference numerals and symbols in the different figures refer to corresponding parts as a whole, unless otherwise indicated. The drawings are drawn to clearly show the various embodiments of the related aspects and are not necessarily drawn to scale.

The construction and use of some embodiments of the invention are described in detail below. However, it should be understood that the present invention provides many applicable creative concepts that can be implemented in a wide variety of specific contexts. The particular embodiments discussed are merely illustrative of specific ways of constructing and using the invention and are not intended to limit the scope of the invention.

Some embodiments of the present invention relate to a semiconductor device and a method of manufacturing an image sensor element. New image sensor elements, semiconductor devices and their fabrication methods are described herein.

Referring first to Figure 1, a cross-sectional view of two semiconductor wafers 120a, 120b bonded together in accordance with some embodiments of the present invention is illustrated. The first semiconductor wafer 120a is bonded to the second semiconductor wafer 120b using a wafer bonding technique to produce the semiconductor device 100 (see FIG. 2). The first semiconductor wafer 120a and the second semiconductor wafer 120b are bonded and processed using the method described herein. A plurality of semiconductor devices 100 are formed from the first and second semiconductor wafers 120a and 120b and then the first and second semiconductor wafers 120a and 120b are scribed to separate the semiconductor devices 100 from the wafers. And are individualized along a scribe line region. However, in some drawings of the present invention, only some of the semiconductor wafers 120a and 120b including part of the semiconductor wafers 120a and 120b including a part of the semiconductor wafers 120a and 120b Only one semiconductor element 100 is exemplified. Thus, reference numeral 120a denotes a first semiconductor wafer or a first semiconductor chip, and reference numeral 120b denotes a second semiconductor wafer or a second semiconductor chip.

Referring again to Figure 1, first a first semiconductor wafer 120a is provided. The first semiconductor wafer 120a includes a substrate 102a and a wiring structure 104a disposed on the substrate 102a. Substrate 102a may comprise a semiconductor substrate comprising silicon or other semiconductor material and may be coated, for example, with an insulating layer. The substrate 102a may include active capabilities or circuits not shown. The substrate 102a may comprise, for example, silicon oxide over monocrystalline silicon. The substrate 102a may comprise a conductive layer or a semiconductor element, such as a transistor, a diode, a capacitor, a resistor, an inductor, or the like. For example, compound semiconductors such as GaAs, InP, Si / Ge or SiC may be used instead of silicon. The substrate 102a may comprise, for example, a silicon-on-insulator (SOI) germanium-on-insulator (GOI) substrate. The substrate 102a may also be referred to herein as a first substrate 102a.

The wiring structure 104a includes an interlayer insulating film (IMD) 106a including a plurality of insulating material layers. The interconnect structure 104a and the IMD 106a are also referred to herein as the first interconnect structure 104a and the first IMD 106a. The IMD 106a includes a plurality of conductive lines 108a and a plurality of conductive vias 110a formed therein. IMD 106a, conductive lines 108a and conductive vias 110a provide electrical connections, for example, either horizontally or vertically, to first semiconductor wafer 120a. The insulating material layer of the IMD 106a may be made of, for example, silicon dioxide, silicon nitride, a low dielectric constant (k) insulating material having a dielectric constant or k value less than or equal to a k value k (ELK) dielectric material or other kinds of materials having a k value.

Conducting line 108a and conductive via 110b may comprise, for example, a material such as Cu, Al, alloys thereof, other conductive materials, a seed layer, a barrier layer, or a combination or multilayer thereof. A plurality of conductive features 112a may also be formed in the IMD 106a, including trapezoidal or otherwise shaped conductive lines 108a and materials similar to those described above for the conductive vias 110a. In some embodiments, a contact pad 114 is formed adjacent to the surface of the IMD 106a proximate to or adjacent to the first substrate 102a. The contact pad 114 may comprise, for example, Cu, a Cu alloy, Al, or other conductive material. Conductive lines 108a, conductive vias 110a, conductive features 112a and contact pads 114 may be formed in the IMD 106a using, for example, a damascene process and / or an etch removal technique. Alternatively, the IMD 106a, the conductive line 108a, the conductive via 110a, the conductive feature 112a, and the contact pad 114 may comprise other materials and may be formed using other methods, have.

A second semiconductor wafer 120b is provided. The second semiconductor wafer 120b also includes a substrate 102b and a wiring structure 104b coupled to the substrate 102b. The substrate 102b and the wiring structure 104b are also referred to herein as a second substrate 102b and a second wiring structure 104b. The interconnect structure 104b includes an IMD 106b, referred to herein as a second IMD 106b. IMD 106b includes, in some embodiments, a plurality of conductive lines 108b, conductive vias 110b, and / or conductive features 112b formed therein. The substrate 102b, the IMD 106b, the conductive lines 108b, the conductive vias 110b and the conductive features 112b are electrically connected to the substrate 102a of the first semiconductor wafer 120a, the IMD 106a, May include materials and forming methods similar to those described for line 108a, conductive via 110a, and conductive feature 112a.

In some embodiments, the second semiconductor wafer 120b is adapted to perform a different function than, for example, the first semiconductor wafer 120a. In some embodiments, the first semiconductor wafer 120a includes a sensor element and the second semiconductor wafer 120b includes an application specific integrated circuit (ASIC) device, for example. The first semiconductor wafer 120a includes an array region 116 that includes a plurality of pixels formed in the substrate 102 as shown in phantom in Figure 1 in some embodiments (e.g., dotted lines). In some embodiments, a color filter material / lens material 118 is formed over the array region 116. For example, a color filter material is formed on a plurality of pixels of the array region 116, and a lens material is formed on the color filter material. The pixels in the array area 116 are adapted to sense the received image. The color filter material is a color filter material in which light is emitted in red-green-blue (R, G, or B) when the semiconductor element 100 (not shown in FIG. 1 and not shown in FIG. 2) is utilized as a backside illuminated And are adapted to separate into basic elements. The color filter material includes, as another example, a photosensitive material in some embodiments. The lens material includes, by way of example, a micro-lens material in some embodiments. Alternatively, the lens material may include other materials such as the color filter material and the lens material. In some embodiments, the color filter material or lens material or color filter and lens material 118 are not included, and the array region 116 may include pixels and other types of elements. The array region 116 is also referred to herein as the pixel array region 116, for example in part of the patent claims.

The first semiconductor wafer 120a is bonded to the second semiconductor wafer 120b in an inverted state in some embodiments as shown in Figs. The first wiring structure 104a of the first semiconductor wafer 120a is bonded to the second wiring structure 104b of the second semiconductor wafer 120b in some embodiments, for example. In some embodiments, the first IMD 106a of the first semiconductor wafer 120a is bonded to the second IMD 106b of the second semiconductor wafer 120b, for example.

The first semiconductor wafer 120a may be bonded to the second semiconductor wafer 120b using a suitable wafer bonding technique. The first semiconductor wafer 120a may be bonded to the second semiconductor wafer 120b using, for example, dielectric-dielectric bonding, metal-metal bonding, metal-dielectric bonding, or a combination thereof. Some examples of wafer bonding techniques that are typically used include direct bonding, chemical activated bonding, plasma activated bonding, anodic bonding, eutectic bonding, glass frit bonding, adhesive bonding, thermal bonding, And / or other junctions. After the first semiconductor wafer 120a and the second semiconductor wafer 120b are joined together, the interface between the first semiconductor wafer 120a and the second semiconductor wafer 120b is separated from the interface between the first semiconductor wafer 120a and the second semiconductor wafer 120b, Thereby providing an electrically conductive path between the semiconductor wafers 120b. According to some embodiments, in the direct bonding process, the connection between the first semiconductor wafer 120a and the second semiconductor wafer 120b may be a metal-metal junction (e.g., copper-copper junction), a dielectric- Oxide-oxide bonding), metal-dielectric bonding (e.g., oxide-copper bonding), any combination thereof, and / or other bonding. In some embodiments, the first semiconductor wafer 120a and the second semiconductor wafer 120b are bonded using a suitable metal-dielectric bonding technique such as a copper-silicon oxide nitride (Cu-SiON) bonding process as another example.

2 is a cross-sectional view of a semiconductor device 100 including two semiconductor wafers 120a and 120b after the bonding process according to some embodiments. The semiconductor device 100 includes an image sensor element in some embodiments. The image sensor element may comprise a stacked complementary metal oxide semiconductor (CMOS) image sensor (CIS) element and / or a BSI image sensor element according to some embodiments. Alternatively, the semiconductor device 100 may include other types of devices.

The first semiconductor wafer 120a is inverted prior to the bonding process in some embodiments so that the conductive features 112a, conductive lines 108a, conductive vias 110a and / or shallow trenches < RTI ID = The device isolation (STI) region (which may be formed in the substrate 102a, not shown, for example) may be formed on the conductive feature 112b, the conductive line 108b, the conductive via 110b ) And / or a shallow trench isolation (STI) region (which may be formed in the substrate 102b, for example, not shown). By way of example, the polygonal conductive feature 112a has an inverted symmetrical shape from the polygonal conductive feature 112b, and the via 110a has an inverted form from the via 110b. The first semiconductor wafer 120a may not be reversed prior to the bonding process and the conductive feature 112a, conductive line 108a, conductive vias 110a and / Or STI regions may be formed in a similar fashion for the shape of at least some of the conductive features 112b, conductive lines 108b, conductive vias 110b, and / or STI regions in a second interconnect structure 104b not shown, And orientation.

The contact pad 114 may be substantially coplanar with the IMD 106a as shown in FIG. In another embodiment, the contact pad 114 may include a portion, such as an edge portion, disposed on the top surface of the IMD 106a, for example, as shown in FIG. In some embodiments, the contact pad 114 may include a contact of an under-ball wiring (UBM) structure or a post-passivation wiring (PPI) structure. Conductive materials such as solder balls, micro bumps, controlled collapse chip connection (C4) bumps, or combinations thereof may be attached to contact pads 114 for later electrical connection to the first semiconductor wafer 120a in some embodiments, . In another embodiment, the contact pad 114 may include a wire bonding pad, and the wire bonding portion may be attached to the contact pad 114 later for electrical connection to the first semiconductor wafer 120a as another example. Alternatively, the contact pad 114 may include other types of pad, and electrical connections to the contact pad 114 may be made using other types of structures and techniques.

3 is a cross-sectional view of a semiconductor device 100 after a portion of the substrate 102a of one of the semiconductor wafers (e.g., the first semiconductor wafer 120a) has been removed in accordance with some embodiments. According to some embodiments of the present invention, a portion of the substrate 102a is removed from the first semiconductor wafer 120a to expose a portion of the interconnect structure 104a. A portion of the removed substrate 102a is disposed on the contact pads 114 of the interconnect structure 104a and a portion of the interconnect structure 104a that is adjacent to the scribe line region 122, (A), b), c) and / or d)) of the interconnection structure 104a of the interconnection structure 104a, disposed on the plurality of contact pads 114 of the interconnection structure 104a, And a part of the substrate 102a.

A portion of the first substrate 102a may be removed using a lithographic process in some embodiments. For example, a photoresist layer (not shown) may be deposited or formed on the first substrate 102a, and the photoresist layer is then patterned using a lithographic process. The lithographic process may include exposing the photoresist layer to light transmitted through the lithographic mask having a desired pattern thereon or energy reflected therefrom. The photoresist layer is developed and the exposed or unexposed portions of the photoresist layer are removed or etched away depending on whether the photoresist layer is a positive or negative photoresist. The photoresist layer is then used as an etch mask while a portion of the substrate 102a is etched away by an etch process. A hard mask material (not shown) may also be included between the substrate 102a and the pot resist layer. The pattern of the photoresist layer may be transferred to the hard mask material, and as another example, both the hard mask or photoresist layer and the hard mask may be used as an etch mask while a portion of the substrate 102a is etched away by the etch process Can be used. Alternatively, a portion of the substrate 102a may be removed using other methods.

In some embodiments, a portion of the substrate 102a may be removed, for example, using a backside scribe line (BSSL) etch process or other etch process. A portion of the substrate 102a is removed after the bonding process in some embodiments. In another embodiment, a portion of the substrate 102b may be removed from the first semiconductor wafer 120a prior to the bonding process (not shown).

3-5, a portion of the substrate 102a is removed from above the contact pad region 124 of the interconnection structure 104b and over the scribe line region 122 of the semiconductor device 100. In this embodiment, The contact pad region 124 includes a plurality of contact pads 114 and an area adjacent to the contact pads 114. For example, the contact pad region 124 may be in the form of a frame, shown in top view in FIG. 4, spaced a predetermined distance, such as a distance of several micrometers to 10 micrometers from the side of the contact pad 114, . Alternatively, the contact pad region 124 may be spaced another distance from the side of the contact pad 114. The contact pad region 124 may be disposed adjacent to all of the contact pads 114 in some embodiments. In another embodiment, the contact pad region 124 is disposed adjacent to a portion of the contact pad 114. Substrate 102a is left in the central region of semiconductor device 100 in the illustrated embodiment; Alternatively, the substrate 102a may be left in a region other than the central region, and the contact pad region 124 may have a different shape.

FIG. 3 is a cross-sectional view of the semiconductor device 100 of FIG. 4 taken at 3-3 'of FIG. The contact pads 114 are arranged in rows around the periphery of the substrate 102a in some embodiments. Alternatively, the contact pads 114 may be arranged in other configurations. The scribe line region 122 is disposed at the edge of the semiconductor device 100. The scribe line region 122 is a region in which the plurality of semiconductor elements 100 are separated from one another (e.g., individualized) from the first and second semiconductor wafers 120a and 120b using cutters and / And an area where discrete semiconductor elements 100 including the second semiconductor chips 120a and 120b are to be formed.

In the embodiment shown in Fig. 3, no through vias are disposed in the second semiconductor wafer 120b. Electrical connection to the semiconductor device 100 can be performed using the exposed contact pad 114. For example, one end of a wire bonding portion (not shown) may be connected to the contact pad 114 and the other end of the wire bonding portion may be connected to a contact pad (not shown) on the surface of the first substrate 102a. As another example, one end of the wire bonding portion may be connected to the contact pad 114 and the other end of the wire bonding portion may be connected to another external device (not shown). Alternatively, the electrical connection can be made to the contact pad 114 using other devices and techniques.

5 is a cross-sectional view of a semiconductor device 100 according to some embodiments. A portion of the substrate 102a is removed from the contact pad region 124 of the interconnect structure 104b and from the scribe line region 122 of the semiconductor device 100 as shown in Figures 3 and 4. [ However, in the embodiment as shown in FIG. 5, the second semiconductor wafer 102b includes a plurality of through vias 126 formed therein. One or more through vias 126 may be formed in the semiconductor device 120b that provides a vertical electrical connection to the semiconductor device 100, for example. Through vias 126 may be formed, in some embodiments, by the method described in U.S. Patent Application No. 13 / 839,860, filed March 15, 2013, entitled "Wiring Structure and Method" . ≪ / RTI > Alternately, through vias 126 may be formed using other methods. The through vias 126 may be formed, for example, by piercing and patterning the holes in the second semiconductor wafer 120b, coating the holes with an insulating material, and filling the holes with a contact material. The through vias 126 may be formed before or after bonding to the semiconductor wafers 120a, 120b in some embodiments.

The through vias 126 extend at least partially through the second semiconductor wafer 120b and extend from the top to the bottom of the second semiconductor wafer 120b or between the various material layers of the second semiconductor wafer 120b 2 < / RTI > semiconductor wafer 120b. In some embodiments, the through vias 126 extend through the second semiconductor wafer 120b to the first semiconductor wafer 120a and / or at least partially through the first semiconductor wafer 120a, 120a and the second semiconductor wafer 120b.

The contact pads (not shown) may be coupled to the through vias 126 to provide electrical connection to the bottom of the semiconductor device 100. In another embodiment, direct electrical connection may be made to through vias 126 without including contact pads. In some embodiments, a conductive material 128 may be coupled to each of the plurality of through vias 126 of the second semiconductor wafer 120b or to a contact pad coupled to the via vias 126. In some embodiments, Conductive material 128 may include eutectic materials such as, for example, solder or other materials. Conductive material 128 may include solder balls, micro bumps, C4 bumps, or a combination thereof. Conductive material 128 may alternatively include a non-spherical connector. In some embodiments, the conductive material 128 is not included in the semiconductor device 100.

The semiconductor device 100 may include an insulating material 130 disposed on the bottom surface of the second semiconductor wafer 120b also shown in FIG. The insulating material 130 may include a passivation layer and may include, for example, polyimide or other materials. In some embodiments, the insulating material 130 is not included on the semiconductor device 100.

It should be noted that in Figures 5-14, it does not include or display some of the elements illustrated in Figures 1-4, such as, for example, interconnect structures 104a and 104b and IMDs 106a and 106b. Reference may be made to Figures 1-4 again for a closer look at some of the first and second semiconductor wafers 120a and 120b.

6 and 7-8 are a top view and a cross-sectional view of a semiconductor device 100 according to some embodiments. In these embodiments, the substrate 102a is removed from above the contact pad region 124 of the interconnect structure 104a. The substrate 102a is left over the center region of the semiconductor device 100 and the scribe line region 122, for example. 7 is a cross-sectional view of the semiconductor device 100 taken along line 7-7 'of FIG. Figure 8 shows a schematic view of the embodiment of Figure 5 in which through vias 126 are formed in the second semiconductor wafer 120b and the conductive material 128 and the insulating material 130 may or may not be included in the semiconductor device 100 Some embodiments similar to the example are shown.

9 and 10 are a top view and a cross-sectional view of a semiconductor device 100 according to some embodiments. The substrate 102a is partially removed only from above the scribe line region 122 of the semiconductor device 100. [ Substrate 102a is left on contact pad 114 and contact pad region 124 (see Figures 4 and 6, not shown in Figures 9 and 10). The contact pad 114 and the contact pad region 124 are held against the substrate 102a so that they can not be used for electrical connection in these embodiments so that in some embodiments, 100b of the first semiconductor wafer 120b through the through vias 126 so as to partially penetrate the semiconductor wafer 120b and completely penetrate the second semiconductor wafer 120b or completely penetrate the second semiconductor wafer 120b, (Not shown). The conductive material 128 and the insulating material 130 may or may not be included on the semiconductor device 100 as described for the embodiment illustrated in Figures 5 and 8. [

11 and 12 are a top view and a cross-sectional view of a semiconductor device 100 according to some embodiments. In these embodiments, the substrate 102a is only partly removed from above the contact pad 114. [ The substrate 102a is left over the scribe line region 122 of the semiconductor device 100, for example. In some embodiments, the substrate 102a is removed from directly above at least a portion of the contact pad 114. [

13 and 14 are a top view and a cross-sectional view of a semiconductor device 100 according to some embodiments. The substrate 102a is partially removed from above the contact pads 114 of the interconnect structure 104b and over the scribe line regions 122 of the semiconductor device 100. [

In the embodiment illustrated in Figures 11-14, the substrate 102a may be partially removed from over all the contact pads 114 of the interconnection structure 104a, or may be removed, for example, from one of the contact pads 114 of the interconnection structure 104a Some may be removed from the top of the part. In some embodiments, not shown, a portion of the substrate 102a may be left on the contact pad 114, i.e., the edge region of the contact pad 114. [

The embodiment illustrated in Figures 9-14 may also include through vias 126 formed in the second semiconductor wafer 120b, e.g., in some embodiments, as shown in Figures 5, 8, For example, a conductive material 128 and / or an insulating material 130 on the second semiconductor wafer 120b or a conductive material 128 and / or an insulating material 130 on the second semiconductor wafer 120b May not be included.

After the semiconductor wafers 120 and 120b are joined together and a part of the first substrate 102a is removed from the first semiconductor wafer 120a, the semiconductor elements 100 (e.g., the bonded semiconductor wafers 120a and 120b) Are individualized along the scribe lines in the scribe line area 122 to form a plurality of elements. In some embodiments, the plurality of elements includes a plurality of image sensor elements. In some embodiments, scribe line region 122 is completely removed from the device during the singulation process. In another embodiment, the scribe line region 122 remains partially on the device after the singulation process. After the singulation process, in some of the claims, a portion of the first semiconductor wafer 120a in each element is also referred to herein as the first semiconductor chip 120a, and a portion of the second semiconductor wafer 120b in each element is also referred to herein as And is referred to as a second semiconductor chip 120b.

15 is a flow diagram 150 of a method of manufacturing a semiconductor device 100 (see also Figs. 1-3) in accordance with some embodiments of the present invention. In step 152, a first semiconductor wafer 120a is bonded to a second semiconductor wafer 120b, which includes a substrate 102a and a wiring structure 104a bonded to the substrate. In step 154, a part of the substrate 102a is removed from the first semiconductor wafer 120a to expose a part of the wiring structure 104a.

Some embodiments of the present invention include a method of manufacturing a semiconductor device and an image sensor element. Some embodiments of the present invention also include semiconductor devices and image sensor devices fabricated using the novel method described herein.

An advantage of some embodiments of the present invention is that it provides a new semiconductor device 100 and an image sensor element 100 that include two semiconductor chips 120a and 120b bonded together and can include various wiring configurations and selections . The image sensor element 100 includes a stacked CIS element that in some embodiments integrates semiconductor chips 120a and 120b into other features to form a single semiconductor device 100 or image sensor device 100. [ The first semiconductor chip 120a and the second semiconductor chip 120b may be manufactured separately using an optimal manufacturing process and then the semiconductor chips 120a and 120b may be bonded together. In some embodiments, by removing a portion of the substrate 102a to expose the contact pad 114, the contact pad 114 may be used to perform an electrical connection, which may reduce the metal path and chip area required in some embodiments . The new fabrication method described herein provides a flexible application that lowers power consumption and increases operating speed in some embodiments. Various embodiments of the present invention provide various configurations and devices of the semiconductor device 100. In addition, the structure and design of the new semiconductor device 100 and the image sensor element 100 can be easily implemented in the manufacturing process flow.

According to some embodiments of the present invention, a method of manufacturing a semiconductor device includes bonding a first semiconductor wafer to a second semiconductor wafer, the first semiconductor wafer including a substrate and a wiring structure coupled to the substrate. A part of the substrate is removed from the first semiconductor wafer to expose a part of the wiring structure.

According to another embodiment, a method of manufacturing an image sensor element includes bonding a first semiconductor wafer including a substrate and a wiring structure coupled to the substrate to a second semiconductor wafer. A part of the substrate is removed to expose a part of the wiring structure. The first semiconductor wafer and the second semiconductor wafer are individualized to form a plurality of image sensor elements.

According to another embodiment, the image sensor element includes a first semiconductor chip, and the first semiconductor chip includes a substrate and a wiring structure disposed on the substrate. The image sensor element includes a second semiconductor chip bonded to the first semiconductor chip. A part of the wiring structure of the first semiconductor chip is exposed.

In some embodiments, the exposed portion of the interconnect structure of the first semiconductor chip is adjacent to a scribe line region, a contact pad of the interconnect structure, a plurality of contact pads of the interconnect structure, a contact pad region of the interconnect structure, And an area of the image sensor element.

Although some embodiments of the present invention and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims. For example, those skilled in the art will readily appreciate that many of the features, functions, processes and materials described herein can be modified while remaining within the scope of the invention. Further, the scope of the present invention is not intended to be limited to the process, apparatus, manufacture, composition of matter, means, methods and steps of the specific embodiments described in the specification. As will be readily apparent to those skilled in the art from the disclosure of the present invention, the composition of a process, apparatus, manufacturing, or material that is presently or later developed to perform or achieve substantially the same function or result as the corresponding embodiment described herein , Means, methods, or steps may be utilized in accordance with the present invention. Accordingly, the appended claims are intended to include within their scope such process, apparatus, manufacture, composition of matter, means, method or step.

Claims (10)

A method of manufacturing a semiconductor device,
Bonding a first semiconductor wafer including a substrate and a wiring structure coupled to the substrate to a second semiconductor wafer, wherein the wiring structure includes a plurality of insulating layers and a plurality of conductive layers, Wherein the conductive layer in the portion is a contact pad of the wiring structure, and the contact pad is in contact with the substrate; bonding the first semiconductor wafer to the second semiconductor wafer;
Removing a first portion of the substrate from the first semiconductor wafer to expose contact pads in a first portion of the wiring structure, the first portion of the substrate being located over a first portion of the wiring structure Removing a first portion of the substrate;
Removing a second portion of the substrate from the first semiconductor wafer over a scribe line region to expose a second portion of the interconnection structure, wherein a second portion of the interconnection structure is disposed within the scribe line region, And removing the second portion of the substrate, wherein the second portion of the substrate is located over the second portion of the wiring structure. The method of claim 1, wherein removing the first portion of the substrate comprises: i) removing a portion of the substrate from over the contact pad of the wiring structure, or ii) Removing at least one of the plurality of semiconductor elements. The semiconductor device according to claim 1, wherein the substrate includes a first substrate, the wiring structure includes a first wiring structure, and the second semiconductor wafer includes a second substrate and a second wiring structure disposed on the second substrate Wherein bonding the first semiconductor wafer to the second semiconductor wafer comprises bonding the first wiring structure to the second wiring structure. 2. The method of claim 1, wherein the first semiconductor wafer includes a sensor chip having a pixel array region disposed on the substrate. A method of manufacturing an image sensor element,
Bonding a first semiconductor wafer comprising a substrate and a wiring structure coupled to the substrate to a second semiconductor wafer, the substrate comprising a central region directly surrounded by an outer region, Wherein the wiring structure comprises a stack of wiring layers, the stack extending from the first semiconductor wafer, and the first conducting portion of the wiring structure is connected to the first semiconductor wafer Joining a first semiconductor wafer to a second semiconductor wafer, wherein the first semiconductor wafer is directly adjoin;
Removing an outer region of the substrate to expose at least a first conducting portion of the wiring structure outside the central region;
And singulating said first semiconductor wafer and said second semiconductor wafer to form a plurality of image sensor elements. 6. The method of claim 5, wherein removing the outer region of the substrate further comprises removing a scribe line region from the top of the contact pads of the interconnect structure, the plurality of contact pads of the interconnect structure, scribe line region of the substrate. < RTI ID = 0.0 > 11. < / RTI > 6. The method of claim 5, further comprising inverting the first semiconductor wafer before bonding the first semiconductor wafer to the second semiconductor wafer. 6. The method of claim 5, wherein the second semiconductor wafer includes a plurality of through vias formed therein. 9. The method of claim 8, further comprising coupling a conductive material to each of the plurality of through vias in the second semiconductor wafer. In the image sensor element,
1. A first semiconductor chip comprising a substrate and a wiring structure disposed on the substrate, wherein the wiring structure has a top surface and a bottom surface, the top surface is adjacent to the substrate, 1 semiconductor chip;
And a second semiconductor chip bonded to the first semiconductor chip in a face-to-face configuration,
Wherein the second semiconductor chip includes a second wiring structure and a conductive through via, the conductive through via penetrating the second semiconductor chip from a face surface of the second semiconductor chip, The conductive through vias electrically connecting the wiring structure to an external connector on the back surface of the second semiconductor chip,
Wherein the first layer of the wiring structure of the first semiconductor chip is exposed through the substrate of the first semiconductor chip and the first layer is exposed to the substrate of the first semiconductor chip relative to at least one other layer of the wiring structure Adjacent,
Wherein a first exposed portion of the first layer comprises a conductive portion of the wiring structure and a second exposed portion of the first layer is a scribe line region, and wherein the conductive portion of the first exposed portion of the first layer Has a surface coplanar with the top surface of the wiring structure.

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