KR101763970B1 - High efficiency, remotely reconfigurable remote radio head unit system for wireless communications - Google Patents

Abstract

A remote radio head unit (RRU) is disclosed for achieving high efficiency and high linearity in a broadband communication system. The present invention is based on an adaptive digital pre-distortion method for linearizing a power amplifier within the RRU. Power amplifier characteristics such as changes in linearity of the amplifier output signal and asymmetric distortion are monitored by a broadband feedback path and controlled by an adaptive algorithm of the digital module. Therefore, according to the embodiment of the present invention, the nonlinearity is compensated together with the memory effect of the power amplifier system, and the performance is also improved in the power addition efficiency, the adjacent channel leakage rate, and the peak-to-average power ratio. Disclosed herein is a power amplifier system that is reconfigurable in the field and that supports multiple modulation schemes (irrespective of modulation scheme), multicarrier, multiple frequency bands, and multiple channels. Thus, the remote wireless head system is particularly suitable for wireless transmission systems such as base stations, repeaters and indoor coverage systems.

Description

≪ Desc / Clms Page number 1 > HIGH EFFICIENCY, REMOTELY RECONFIGURABLE REMOTE RADIO HEAD UNIT SYSTEM FOR WIRELESS COMMUNICATIONS < RTI ID = 0.0 >

{RELATED APPLICATION}

This application claims the benefit of the following applications:

U.S. Patent Application No. 12 / 415,676, filed on March 31, 2009, and U.S. Patent Application No. 61 / 041,164, filed on March 31, 2008, It also claims priority to U.S. Provisional Patent Application No. 61 / 172,642, filed Apr. 24, 2009;

U.S. Patent Application No. 12 / 603,419 filed on October 21, 2009, and U.S. Patent Application No. 12 / 108,507 filed on Apr. 23, 2008, and U.S. Patent Application No. 60 / 925,577;

U.S. Patent Application No. 12 / 330,451, filed December 8, 2008, and U.S. Patent Application No. 61 / 012,416, filed on December 7, 2007;

U.S. Patent Application No. 11 / 961,969 filed December 20, 2007, and U.S. Patent Application No. 60 / 877,035 filed December 26, 2006, and U.S. Patent Application No. 60 / 925,603 filed on Apr. 23, 2007 ;

U.S. Provisional Patent Application No. 12 / 108,502 filed on Apr. 23, 2008, and U.S. Patent Application No. 12 / 021,241 filed on Jan. 28, 2008, and U.S. Provisional Patent Application No. 60 / / 897,746;

Wan-Jong Kim, Kyoung-Joon Cho and Shawn Patrick Stapleton have been named as inventors and have developed a multi-band broadband power amplifier digital pre-distortion system and its method (MULTI-BAND WIDEBAND POWER AMPLIFIER DIGITAL PREDISTORTION SYSTEM AND METHOD), filed on December 21, 2009, U.S. Patent Application No. 61 / 288,838.

Chengxun Wang and Shawn Patrick Stapleton, as inventors, have proposed a remote wireless head unit system including a broadband power amplifier and a method therefor (REMOTE RADIO HEAD UNIT SYSTEM WITH WIDEBAND POWER AMPLIFIER AND METHOD) U.S. Patent Application No. 61 / 288,840 filed on December 21, 2009.

Wan-Jong Kim, Kyoung-Joon Cho, Shawn Patrick Stapleton, and Ying Xiao have been appointed as inventors, and a digital hybrid mode power amplifier U.S. Patent Application No. 61 / 288,844, filed on December 21, 2009, entitled MODULATION AGNOSTIC DIGITAL HYBRID MODE POWER AMPLIFIER SYSTEM AND METHOD.

Wan-Jong Kim, Kyoung-Joon Cho, Shawn Patrick Stapleton, and Ying Xiao have been appointed as inventors and are highly efficient remotely configured for wireless communication. U.S. Patent Application No. 61 / 288,847, filed on December 21, 2009, entitled HIGH EFFICIENCY, REMOTELY RECONFIGURABLE REMOTE RADIO HEAD UNIT SYSTEM AND METHOD FOR WIRELESS COMMUNICATIONS.

All of the above applications are incorporated herein by reference for all purposes.

The present invention relates to a wireless communication system using a power amplifier and a remote radio head unit (RRU or RRH). In particular, the present invention relates to an RRU that is part of a distributed base station that is included in a small single unit where all wireless related functions are remotely located from the main unit. Multi-mode wireless communications that operate along the GSM, HSPA, LTE and WiMAX standards and advanced software configurability are the main characteristics of a more flexible and energy efficient wireless network deployment. The present invention can also support multiple frequency bands in a single RRU to economize the cost of wireless network deployment.

Wireless and mobile network operators are facing the constant challenge of building networks that can efficiently manage high data traffic growth rates. The enhanced level of mobility and multimedia content for end users has required an end-to-end network that supports both increased demand for broadband and fixed-rate Internet access with new services . In addition, network operators must consider the most cost-effective evolution of networks for 4G services. Wireless and mobile technology standards are evolving toward higher bandwidth requirements for both maximum speed and increased cell throughput. The latest standards to support them are HSPA +, WiMAX, TD-SCDMA and LTE. The upgrade of the network required to deploy a network based on these standards should balance the limited availability of new spectrum, leverage of existing spectrum, and assurance of the operation of all desired standards. All of this happens all the time in the transition phase, and this transition phase takes years. The concept of a distributed open base station architecture as shown in Figure 6 has evolved with the evolution of standards to provide a flexible, cheaper and more extensible modular environment for managing the evolution of wireless access. For example, the Open Base Station Architecture Initiative (OBSAI), the Common Public Radio Interface (CPRI), and the IR wireless standard may include a remote wireless head portion of a base station server and a base station And introduced a standardized interface that is separated by optical fibers.

The concept of the RRU constitutes a fundamental part of the latest base station architecture. However, the RRU to date has been power inefficient, costly, and inflexible. Their poor DC-RF power conversion characteristics have ensured that they will have a large mechanical housing. The demand for RRU from service providers is about greater flexibility for the RRU platform. As standards evolved, there was a need for software upgradeable RRUs. Today, RRU lacks the flexibility and performance required by service providers. The limited performance of these RRUs is due in part to the poor power efficiency of the RF amplifier. Thus, there is a need for an efficient and flexible RRU structure that can be reconfigured in the field.

SUMMARY OF THE INVENTION Accordingly, the present invention has been made in view of the above problems of the prior art and provides a high performance and cost effective method of a multi-frequency band RRU system enabled by a high linearity and high efficiency power amplifier for application to a broadband communication system For that purpose. The specification of the present invention enables RRUs that are reconfigurable in the field, support multiple modulation schemes (irrespective of modulation scheme), multicarrier, multiple frequency bands, and multiple channels.

In order to achieve the above object, according to the present invention, the technical idea is based on an adaptive digital predistortion method for linearizing an RF power amplifier. Various embodiments of the present invention are disclosed, including single-band, dual-band, multi-band RRUs. Another embodiment is a multi-band multi-channel RRU. In accordance with one embodiment of the present invention, a combination of crest factor reducton, PD, and power efficiency boosting techniques together with a coefficient adaptive algorithm is used in a power amplifier (PA) system. According to another embodiment of the present invention, an analog quadrature modulator compensation structure is also used for improving the performance.

According to some embodiments of the present invention, variations in power amplifier characteristics can be monitored and self-tuning by self-adaptive algorithms. One such self-adaptive algorithm is the digital predistortion algorithm, which is implemented in the digital domain.

The application of the present invention may be applied to any wireless base station, remote radio head, distributed base station, distributed antenna system, access point, mobile device and wireless terminal, portable wireless device, and other And is suitable for use in a wireless communication system. The invention is also field upgradeable via a link, such as an Ethernet connection to a remote computing center.

Further objects and advantages of the present invention will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings.

In summary, the RRU system according to the present invention can implement CFR, DPD, and adaptive algorithms with one digital processor, thereby reducing hardware resources and processing time. Therefore, the RRU system according to the present invention can improve efficiency and linearity Thereby improving performance more efficiently. The high power efficiency of the RF power amplifier within the RRU means that less heat dissipation mechanism such as a heat sink is required and thus significantly reduces the size and volume of the mechanical housing. These smaller RRUs allow service providers to place RRUs in locations where heavy or large RRUs could not be deployed, such as column footprints, streetlight tops, etc., due to lack of parcels or loads, wind problems, or other safety issues. . The RRU system according to the present invention is also reconfigurable and field programmable since the algorithms and power efficiency enhancements embedded in the firmware can be adjusted at any time similar to a software upgrade of a digital processor.

In addition, the RRU system is independent of modulation schemes such as QPSK, QAM, OFDM, etc. of CDMA, TD-SCDMA, GSM, WCDMA, CDMA2000 and wireless LAN systems. This means that the RRU system can support multiple modulation schemes, multi-carrier and multiple channels. The advantage of the multiple frequency bands is that mobile operators can deploy a smaller number of RRUs to cover a wider frequency band for more subscribers, thus significantly reducing CAPEX and OPEX. Another advantage of the RRU system is that it can compensate for PA non-linearity of a repeater or indoor coverage system that does not have the necessary baseband signal available immediately.

1 is a block diagram showing a basic form of a remote wireless head unit system.
2 is a block diagram illustrating a multi-channel remote wireless head unit according to an embodiment of the present invention.
3 is a block diagram illustrating polynomial-based pre-distortion in a remote wireless head of the present invention.
4 is a block diagram of a digital pre-distortion algorithm applied to self-adaptation in the remote wireless head unit system of the present invention.
5 is a diagram showing an analog modulator compensation block.
Figure 6 conceptually illustrates various potential installation techniques for an RRU based system architecture.
7 is a three-sector arrangement of an RRU system structure including an optical link to a base station server.
8 is a block diagram depicting various DSP-based functions including crest factor reduction and digital predistortion.
9 is a diagram illustrating a digital hybrid module having either an RF input signal or a baseband modulated signal or an optical interface according to an embodiment of the present invention.
10 is a block diagram of a dual channel remote wireless head illustrating a digital hybrid module having an optical interface according to another embodiment of the present invention.
11 is a block diagram of another dual channel remote wireless head illustrating a digital hybrid module having an optical interface according to another embodiment of the present invention.
12 shows a digital hybrid module having an optical interface and further comprising a calibration algorithm to ensure that each power amplifier output is time aligned, phase aligned, and amplitude aligned with respect to one another. Band remote radio head.

{GLOSSARY}

Abbreviations used herein have the following meanings. In other words,

ACLR: Adjacent Channel Leakage Ratio

ACPR: Adjacent Channel Power Ratio

ADC: Analog-to-Digital Converter (ADC)

AQDM: Analog Quadrature Demodulator

AQM: Analog Quadrature Modulator

AQDMC: Analog Quadrature Demodulator Corrector

AQMC: Analog Quadrature Modulator Corrector

BPF: Bandpass Filter

CDMA: Code Division Multiple Access (CDMA)

CFR: Crest Factor Reduction

DAC: Digital to Analog Converter

DET: Detector

DHMPA: Digital Hybrid Mode Power Amplifier

DDC: Digital Down Converter

DNC: Down Converter (Down Converter)

DPA: Doherty Power Amplifier

DQDM: Digital Quadrature Demodulator

DQM: Digital Quadrature Modulator

DSP: Digital Signal Processing (Digital Signal Processing)

DUC: Digital Up Converter

EER: Envelope Elimination and Restoration

EF: Envelope Following

ET: Envelope Tracking

EVM: Error Vector Magnitude

FFLPA: Feedforward Linear Power Amplifier

FIR: Finite Impulse Response

FPGA: Field-Programmable Gate Array

GSM: Global System for Mobile communications

l-Q: In-phase / quadrature

IF: Intermediate Frequency

LINC: Linear Amplification using Nonlinear Components

LO: Local Oscillator

LPF: Low Pass Filter

MCPA: Multi-Carrier Power Amplifier

MDS: Multi-Directional Search

OFDM: Orthogonal Frequency Division Multiplexing (OFDM)

PA: Power Amplifier

PAPR: Peak-to-Average Power Ratio

PD: Digital Baseband Predistortion

PLL: Phase Locked Loop

QAM: Quadrature Amplitude Modulation

QPSK: Quadrature Phase Shift Keying (QPSK)

RF: Radio Frequency

RRU: Remote radio head unit (small remote wireless base station equipment)

SAW: Surface Acoustic Wave Filter

SERDES: Serializer / Deserializer (Serializer / Deserializer)

UMTS: Universal Mobile Telecommunications System (UMTS)

UPC: Up Converter

WCDMA: Wideband Code Division Multiple Access (WCDMA)

WLAN: Wireless Local Area Network (WLAN)

The present invention relates to a new RRU system using an adaptive digital predistortion algorithm. The present invention relates to a hybrid system of digital and analog modules. The interaction of the digital and analog modules of the hybrid system maintains or increases the wide bandwidth, while linearizing the regrowth of the spectrum and improving the power efficiency of the PA. Thus, the present invention achieves higher efficiency and higher linearity for a wideband demodulated modulated carrier.

1 is a high-level block diagram illustrating the basic system architecture of what is sometimes referred to as a remote wireless head unit, or RRU, which is considered to include at least digital and analog modules and feedback paths in some embodiments of the present invention. to be. The digital module is a digital predistortion controller 101 that includes a PD algorithm, other auxiliary DSP algorithms, and associated digital circuits. The analog module is a main power amplifier 102, other auxiliary analog circuits such as DPA, and related peripheral analog circuits of the overall system. The present invention receives RF modulated signal 100 as an input and is substantially identical but provides an amplified RF signal 103 as an output and is therefore an RF input / RF output, thus providing a "black box" and a plug- . The baseband input signal may be provided directly to the digital predistortion controller in accordance with one embodiment of the present invention. An optical input signal may be provided directly to the digital predistortion controller in accordance with an embodiment of the present invention. The feedback path basically provides a signal to the predistortion controller 101 indicating the output signal. The present invention is hereinafter sometimes referred to as a remote wireless head unit (RRU).

2 is a block diagram conceptually illustrating one embodiment of an 8-channel (or n-channel) RRU in which an input signal 200 is provided. According to an embodiment, the input signal may take the form of an RF modulated signal, a baseband signal or an optical signal. The input signal 200 is fed into a plurality of channels, where each channel is a digital pre-distortion (DPD) controller designated 201, 211 and 271, respectively. The DPD may be implemented in an FPGA in at least some embodiments. For each channel, the output of the DPD is fed to associated PAs 202, 212 and 272, respectively, and the outputs 203, 213 and 273 of the PA are fed back to the DPD of that channel.

3 is a diagram illustrating a polynomial-based digital pre-distortion function of the RRU system of the present invention. The PD according to the present invention generally uses an adaptive LUT based digital pre-distortion system. Particularly, the PD shown in FIG. 3 and the PD according to the embodiment to be described below with reference to FIGS. 9 to 12 are described in U.S. Patent Application No. 11 / 961,969 (A Method for Baseband Predistortion Linearization in Multi-Channel Wideband Communication Systems ). ≪ / RTI > The PD in the RRU shown in FIG. 3 includes a plurality of finite impulse response (FIR) filters, i.e., FIR1 301, FIR2 303, FIR3 305, and FIR4 307. The PD also includes a 3-squared generating block 302, a 5-squared generating block 304 and a 7-squared generating block 306. The output signal from the FIR filter is combined in a summation block 308. The coefficients in the plurality of FIR filters are updated by the digital predistortion algorithm based on the error between the reference input signal and the amplified power output signal.

Figure 4 shows additional details of an embodiment including a DPD according to the present invention in the form of a block diagram, which will be described in more detail below. Generally, the input 400 is provided to the DPD 401. The output of the DPD is supplied to the DAC 402 and then to the PA 403. The feedback signal from the output of the PA is received by the ADC 406 and its digital form is fed to an alignment logic circuit 405 which then provides the aligned signal to the DPD estimation logic 404, Lt; / RTI > The output of the DPD estimator is then fed back to the DPD 401.

Figure 5 shows an analog modulator compensation block. The input signal is separated into an in-phase component X _I and a quadrature component X _Q. The analog quadrature modulation compensation scheme includes four real filters {g11, g12, g21, g22} and two DC offset compensation parameters c1, c2. The DC offset of the AQM is compensated by the parameters c1, c2. The frequency dependency of the AQM is compensated by the filter {g11, g12, g21, g22}. The order of the real part filters depends on the level of compensation required. The output signals Y _I and Y _Q appear in the inphase and quadrature ports of the AQM and are described below with reference to FIG.

6 illustrates a plurality of possible embodiments of an RRU based system architecture, for example the base station server 600 may be connected to a tower mounted RRU 605, a roof mounted RRU 610 and / or a wall mounted RRU 615 and the like.

Figure 7 illustrates an embodiment of a three sector implementation of an RRU based system architecture in which a base station server 700 is optically connected to multiple RRUs 710 to provide appropriate coverage for a particular site .

Figure 8 is a simplified form of an embodiment of DSP functionality of some implementations of the present invention. An input signal is supplied to interface 800, which may take a variety of forms including OBSAI, CPRI, or IR. The incoming signal is supplied to a digital up-converter (DUC) 805 and then to a CFR / DPD logic circuit 810, such as an FPGA. Next, the output of the CFR / DPD logic circuit 810 is provided to the DAC 815. The DAC provides an output signal to the analog RF portion 820 of the system, which in turn provides a feedback signal to the ADC 825 and is coupled to the CFR / DPD and DDC 830 in the form of an input via the DSP block / RTI > The DDC outputs a signal to the interface 800, and the interface 800 may again provide an output.

9 is a block diagram illustrating a more detailed embodiment of an RRU system, wherein like elements are designated by like reference numerals. The embodiment shown in FIG. 9 reduces the PAPR, EVM, and ACPR by applying a crest factor reduction (CFR) to the adaptive algorithm in one digital processor before the PD, and changes the linearity due to the memory effect and the temperature change of the PA Lt; / RTI > The digital processor can take almost any form, although an FPGA implementation is shown as an example for the sake of convenience, but in many embodiments a general purpose processor is also acceptable. The CFR implemented in the digital module of the above embodiment is disclosed in US patent application Ser. No. 61 / 041,164, filed on March 31, 2008, entitled " Based on scaled iterative pulse cancellation, the contents of which are incorporated herein by reference. Since the CFR is included for performance enhancement, it is therefore optional. The CFR may be removed from the embodiment without affecting the overall functionality.

9 is a block diagram illustrating an RRU system in accordance with an embodiment of the present invention. An RRU system typically includes three main blocks: a power amplifier, baseband processing, and an optical interface. The optical interface includes an opto-electrical interface for the transmit / receive mode. The optical interface 901 shown in FIG. 9 is connected to the FPGA. The FPGA 902 performs functions of SERDES / Framer / De-Framer / Control and Management. The FPGA 902 has an interface with another FPAG 903 that performs digital signal processing tasks such as crest factor reduction / digital upconverting / digital downconversion and digital predistortion. According to another embodiment of the present invention, the FPGAs 902 and 903 can be integrated into one FPGA. The serializer / parallelizer (SERDES) module converts a high-speed serial bitstream from the optical module to an electrical receiver into a parallel bitstream. The de-framer decodes the parallel bit stream, extracts in-phase and quadrature (I / Q) modulation, and transmits it to the digital signal processing module 903. The control and management module extracts a control signal from the parallel bit stream and performs an operation based on the requested information. The I / Q data received from the optical interface is converted to an intermediate frequency by the digital up-converter module (DUC). This composite signal is then subjected to a crest factor reduction (CFR) process to reduce the peak to average power ratio. The resulting signal is then provided to the predistorter to compensate for distortion in the power amplifier module 905. The RRU operates not only in the transmission mode but also in the reception mode. The RRU receives a signal from an output duplexer and forwards it to the Rx path or paths according to the number of channels. The received signal is converted to its intermediate frequency (IF) at the receiver (Rx1 and Rx2 in Fig. 10). The IF signal is further downconverted using a digital downconverter (DDC) module and demodulated into inphase and quadrature components. The recovered I / Q signal is then sent to the Framer module / SERDES and is ready to be transmitted over the optical interface.

The system shown in FIG. 9 has a multi-mode or multi-carrier digital signal of RF where it is an optical signal at the input and an RF signal at the output 910. Multiple modes of signal input maximize flexibility, such as RF input ("RF input mode") or baseband digital input ("baseband input mode") or optical input ("optical input mode"). 9 includes the following four core portions: a reconfigurable digital (hereinafter referred to as "FPGA-based digital") module 915, a power amplifier module 960, a receiver 965, and a feedback path 925.

The FPGA-based digital portion includes either a digital-to-analog converter 935 (DAC), an analog-to-digital converter 940 (ADC), and a phase locked loop (PLL) 945, either of two digital processors 902 and 903 . Since the system shown in Fig. 9 has a multiple input mode, the digital processor has three signal processing paths. For the baseband signal input path, the digital processor implements a digital upconverter (DUC), CFR and PD. For the optical input path, SERDES, Framer / Deframer, Digital Upconverter (DUC), CFR, and PD are implemented. For the RF input path, the analog converters DUC, CFR and PD are implemented.

The baseband input mode shown in FIG. 9 includes an I-Q signal. A digital data stream from multiple channels as an I-Q signal is input to the FPGA-based digital module and digitally upconverted to the digital IF signal by the DUC. This IF signal then passes through the CFR block to reduce the PAPR of the signal. This PAPR suppression signal is digitally pre-distorted to compensate for nonlinear distortion of the power amplifier in advance.

In one input mode, the memory effect due to self-heating, biased network and frequency dependence of the activated device is compensated for by the adaptive algorithm in PD as well. The coefficients of the PD are adjusted by broadband feedback requiring an extremely fast ADC. The pre-distorted signal passes through the DQM to produce a real signal and is then converted to an IF analog signal by the DAC. As noted above, in all embodiments, the DQM need not be implemented in the FPGA or may not be implemented at all. If the DQM is not used in the FPGA, an AQM with two DACs to generate real and imaginary signals 935 may be implemented. The gate bias voltage 950 of the power amplifier is determined by the adaptive algorithm and then adjusted through the DAC 935 to stabilize the change in linearity due to the temperature change of the power amplifier. The PLL 945 sweeps the local oscillator signal for the feedback portion to convert the RF output signal to baseband for processing in the digital module.

The power amplifier portion includes an AQM (as in the embodiment shown in FIG. 9) for receiving real and complex signals from the FPGA-based digital module, a high power amplifier with a multi-stage drive amplifier, and a temperature sensor . Depending on the embodiment, to improve the efficiency performance of the DHMPA system, it may be desirable to use other techniques such as Doherty, Envelope Elimination and Restoration, envelope tracking (ET), envelope tracking (EF), and linear amplification using nonlinear components Efficiency enhancement techniques can be used. These strategic efficiency techniques can be used in combination with the enemy, and are optional characteristics for the underlying RRU system. One such Doherty power amplification technique is disclosed in U.S. Provisional Patent Application No. 60 / 925,577 filed Apr. 23, 2007 (N-Way Doherty Distributed Power Amplifier), which is hereby incorporated by reference do. In order to stabilize the linearity performance of the amplifier, the temperature of the amplifier is monitored by the temperature sensor, and the gate bias of the amplifier is controlled by the FPGA-based digital part.

The feedback portion includes a directional coupler, a low pass filter (LPF), a gain amplifier, and a band pass filter (BPF). Depending on the embodiment, these analog components may be used in combination with other analog components. A portion of the RF output signal of the amplifier is sampled by the directional coupler and then downconverted to an IF analog signal by a local oscillator signal of the mixer. The IF analog signal passes through the LPF, a gain amplifier, and a BPF capable of capturing out-of-band distortion. The output of the BPF is input to the ADC of the FPGA-based digital module to determine the dynamic parameters of the PD according to the output power level and the asymmetric distortion due to the memory effect. The temperature is also detected by the DET 970 to calculate the change in linearity and subsequently adjust the gate bias voltage of the PA. More details of the PD algorithm and the self-adaptive feedback algorithm are shown in FIG. 3, which illustrates a polynomial-based predistortion algorithm, and FIG. 4, which illustrates a main adaptive predistortion block that may be used in some embodiments of the present invention. As shown in FIG.

In the case of a strict EVM (EVM <2.5%) required for broadband wireless access such as WiMAX or other OFMD based approaches, the CFR of the FPGA-based digital part only achieves only a small reduction of the PAPR to meet the stringent EVM specification can do. In a typical environment, this means that the power efficiency enhancement capability of the CFR is limited. According to some embodiments of the present invention, a novel technique to maximize the RRU system power efficiency in such a rigorous EVM environment by compensating for incoming band distortion from the CFR by use of a Clipping Error Restoration Path 907 . As described above, the clipping error recovery path includes an additional DAC in the FPGA-based digital portion and an extra UPC in the power amplifier portion. The clipping error recovery path enables compensation of incoming band distortion resulting from CFR at the output of the power amplifier. In addition, any delay mismatch between the main path and the clipping error recovery path may be arranged using the digital delay of the FPGA.

9 shows an RRU system with AQM according to another embodiment of the present invention, but the system shown in FIG. 9 also includes a digital processor having CFR, PD, and analog quadrature modulator corrector (AQMC) therein can do.

In addition, the system shown in FIG. 9 may be configured differently to provide AQM and AQM based clipping error recovery paths. With this arrangement, the clipping error recovery path can be configured to include two DACs in the FPGA-based digital portion and an AQM in place of the UPC in the power amplifier portion.

10 is a block diagram illustrating a dual channel RRU with two power amplifiers 1000 and 1005 for two different bands provided from AQM1 1010 and AQM2 1015, respectively. A duplexer 1020 is used to combine the outputs of the two power amplifiers, and the combined output is provided to an antenna (not shown). Switches 1025 and 1030 are used to isolate the transmitted signal from the received signal, such as in Time Division Synchronous Code Division Multiple Access (TD-SCDMA) modulation. Feedback signals 1035 and 1040 derived from the outputs of PA 1000 and 1005 are provided to an additional switch 1045 which is toggled at an appropriate time to enable feedback correction of each PA to a single FPGA 1050 . According to the illustrated embodiment, the FPGA 1050 includes a block 1060 comprising two blocks: a SERDES, a framer / combiner and a CMA 1055, and DDC1 / CFR1 / PDC1 / DUC1 and DDC2 / CFR2 / PDC2 / And block 1060 controls the switching timing of the associated switches. The feedback signals 1035 and 1040 are first fed back to the block 1060 via an adder 1065 where the signals are combined with a phase locked loop signal 1070 followed by a band pass filter 1075, a low pass filter 1080 and an ADC 1085 . In addition, temperature sensor signals from PA 1000 and 1005 are fed back to block 1060 via toggle switch 1090 and detector 1095, allowing the pre-distortion coefficients to include temperature compensation. The toggle operation of the switches 1045 and 1090 is synchronized to ensure that the output and temperature signal of each PA is provided to the block 1060 at the appropriate time. According to another embodiment of the RRU, the application range extends to multiple frequency bands. According to another embodiment of the present invention, power amplifiers with additional channels are included in parallel as an implementation of multiple frequency bands (i.e., two or more bands). The output of the additional power amplifier is coupled in a N-to-1 duplexer to a single antenna, although multiple antennas may be used in other embodiments. According to another embodiment of a multi-frequency band RRU, two or more frequency bands are coupled to one or more power amplifiers.

11 is a block diagram illustrating another embodiment of a dual channel RRU. According to this embodiment, receive switches (Rx switches) 1105 and 1110 are disposed in the third ports of the circulators 1115 and 1120 to reduce the insertion loss between the PA output and the duplexer 1020. The remaining part of FIG. 11 is substantially the same as FIG. 10, and therefore its details are omitted.

12 is a block diagram illustrating an embodiment of an 8-channel dual-band RRU. According to the present embodiment, the feedback path for each PA 1000A through 1000H and 1005A through 1000H includes a receiver chain that receives a feedback signal from an associated array of PAs via respective associated circulators 1210A through 1210H and 1215A through 1215H, (Indicated as 1200A to 1200H and 1205A to 1205H, respectively). The receiver chain is used when the RRU is switched to the reception mode, and corresponds to the reception (Rx) path shown in FIG. The wideband capture chain is used to capture the wideband distortion of the power amplifier and corresponds to the feedback correction path shown in FIG. According to one embodiment of the present invention, the channel calibration algorithm is implemented to ensure that each power amplifier output is aligned with respect to time, phase and amplitude.

Digital predistortion algorithm ( Digital Predistorter Algorithm )

Digital predistortion (DPD) is a technique for linearizing a power amplifier (PA). Figure 1 shows a block diagram of a linear digital predistortion PA. In the DPD block, a memory polynomial model is used as a predistortion function (see FIG. 3).

Where _aij is the DPD coefficient.

In the DPD estimator block, at least a least square algorithm is used to find the DPD coefficients a _ij and then sends them to the DPD block. The main DPD block is shown in FIG.

Delay estimation algorithm Delay Estimation Algorithm ):

The DPD estimator compares x (n) with its corresponding feedback signal y (n -? D) to find the DPD coefficient. Here,? D is the delay of the feedback path. Since the feedback path delays are different for each PA, this delay must be identified before the signal reaches the coefficient estimate. According to this design, the amplitude difference correlation function of the transmission x (n) and the feedback data y (n) are applied to find the feedback path delay. The correlation is given by the following equation. In other words,

The delay n maximizing the correlation C (m) is the feedback path delay.

As the feedback path passes through the analog circuits, the delay between the transmission and feedback paths may be a fractional sample delay. Fractional delay estimation is needed to more accurately synchronize the signal. To simplify the design, only half-sample delay is considered in this design, but smaller fractional delays can be used.

An upsampling approach is commonly used to obtain the 1/2 sample delay data, but in this design an interpolation method is used to avoid the very high sampling frequency of the FPGA. Data with integer delays and fractional delays are transmitted in parallel. The interpolation function for fractional delay is as follows. In other words,

Where c _i is a weighting factor.

Whether the fractional delay path or the integer delay path is selected depends on the result of the amplitude difference correlation. If the correlation result is odd, the integer path will be selected, otherwise the fractional delay path will be selected.

Phase Offset Estimation and Calibration Algorithm Phase offset Estimation and  Correction Algorithm ):

There is a phase offset between the transmission signal and the feedback signal in the circuit. For better and faster convergence of the DPD coefficient estimate, this phase offset should be eliminated.

The transmission signal x (n) and the feedback signal y (n) can be expressed by the following equations. In other words,

The phase offset e ^{j (?} X ^{-? Y )} can be calculated by the following equation.

Therefore, the phase offset between the transmission and feedback paths is as follows.

The feedback signal from which the phase offset is removed can be calculated by the following equation. In other words

Size correction ( Magnitude correction ):

Since the gain of PA changes slightly, the feedback gain must be corrected to avoid errors due to gain mismatch. The feedback signal is corrected by the following function.

The choice of N depends on the desired accuracy.

QR _ RLS Adaptive  algorithm( QR _ RLS Adaptive Algorithm ):

The least squares solution for DPD coefficient estimation is expressed by the following equation. In other words,

h _k = x (n - i) | x (n - i) | ^j , w _k = a _ij , where k = (i - 1) N + j. The least squares expression is expressed as:

In this design, the QR-RLS algorithm (Haykin, 1996) was implemented to solve this problem. The formula of the QR_RLS algorithm is as follows. In other words,

Here, φ _i is a diagonal matrix, and q _i is a vector.

QR_RLS the algorithm to obtain a unitary transformation (unitary transformation) through the following: the i-th moment φ _i and q _i, such as from his (i-1) th moment. In other words,

Here,? _I is a unitary matrix of unitary transform.

To more efficiently apply the QR_RLS algorithm to the FPGA, a Givens rotation without square root is applied to the unitary transformation process (see E. N. Frantzeskakis, 1994).

In the RLS algorithm, the i-th moment is developed as follows. In other words,

w _i can be obtained by _solving the following equation. In other words,

In the iterative process, a data block (in this design, there are 4096 data in one block) is stored in memory, which uses all the data in the memory to estimate the DPD coefficients. To make the DPD performance more stable, the DPD coefficients are only updated after one block of data has been processed. The matrix A will be used in the next iteration and will therefore converge faster.

In order to ensure that the performance of the DPD is stable, the following weighting factor f is used when updating the DPD coefficient. In other words,

The DPD coefficient estimator computes the coefficient w _i using the QR_RLS algorithm. This w _i is copied to the DPD block to linearize the PA.

Channel Calibration Algorithm ( Channel Calibration Algorithm )

The 8-channel RRU shown in FIG. 12 includes sixteen different power amplifiers, shown as PA 1000A through 1000H and 1005A through 1005H. Half of the power amplifier is designed for one band and the remainder is designed for the second band. Hereinafter, these bands are referred to as band A and band B, and they point to two different frequencies. The 8-channel RRU includes eight antennas 1220A through 1220H, both of which are on each antenna. In order to maximize performance, the output signals of each power amplifier need to be aligned with respect to time, phase and amplitude. The antenna calibration algorithm includes the following three different approaches. 1) a Pilot Tone is injected into each PA; 2) a reference modulated signal is transmitted through each PA; Or 3) real-time I / Q data is used as a reference signal. The pilot tone approach injects the tracked single carrier IF tones into a receiver of a feedback correction path or an individual PA. Each transmission path of band A is aligned with respect to time, phase and amplitude, and so is band B as well. The reference modulation approach uses the stored complex modulated signal transmitted over each of the PAs in band A, and so on for band B as well. The transmitters are then aligned with respect to time, phase and amplitude. Either the feedback calibration path or the individual receiver may be used to obtain the PA output signal. The real-time approach operates on signals transmitted in real time. This approach uses DPD time alignment, phase and magnitude offset information to synchronize each PA output with one another.

In summary, the RRU system according to the present invention can implement CFR, DPD, and adaptive algorithms with one digital processor, thereby reducing hardware resources and processing time. Therefore, the RRU system according to the present invention can improve efficiency and linearity Thereby improving performance more efficiently. The high power efficiency of the RF power amplifier within the RRU means that less heat dissipation mechanism such as a heat sink is required and thus significantly reduces the size and volume of the mechanical housing. These smaller RRUs allow service providers to place RRUs in locations where heavy or large RRUs could not be deployed, such as column footprints, streetlight tops, etc., due to lack of parcels or loads, wind problems, or other safety issues. . The RRU system according to the present invention is also reconfigurable and field programmable since the algorithms and power efficiency enhancements embedded in the firmware can be adjusted at any time similar to a software upgrade of a digital processor.

In addition, the RRU system is independent of modulation schemes such as QPSK, QAM, OFDM, etc. of CDMA, TD-SCDMA, GSM, WCDMA, CDMA2000 and wireless LAN systems. This means that the RRU system can support multiple modulation schemes, multi-carrier and multiple channels. The advantage of the multiple frequency bands is that mobile operators can deploy a smaller number of RRUs to cover a wider frequency band for more subscribers, thus significantly reducing CAPEX and OPEX. Another advantage of the RRU system is that it can compensate for PA non-linearity in a repeater or indoor coverage system that does not have the necessary baseband signal available immediately.

While the present invention has been particularly shown and described with reference to preferred embodiments thereof, it is to be understood that the invention is not limited to the details thereof. Various alternatives and modifications have been suggested in the foregoing description, and other alternatives and modifications may occur to those skilled in the art. It is therefore to be understood that such alternatives and modifications are within the scope of the invention as defined in the following claims.

Claims (10)

A multi-channel remote wireless head unit for wireless communication,
A radio frequency (RF) input path;
A baseband input path;
Optical input path;
A digital processor for receiving an input signal from the radio frequency input path, the baseband input path, or the optical input path;
A plurality of power amplifiers each receiving an input signal and each providing an amplified representation of the received input signal as an output, the input signal being received from the digital processor;
A plurality of feedback paths connected to respective outputs of the plurality of power amplifiers, each of the plurality of feedback paths providing a feedback signal; And
One of said feedback signals associated with a power amplifier of one of said plurality of power amplifiers for connection to said digital processor to generate a predistortion compensation signal suitable for each of said power amplifiers based at least in part on said feedback signal Feedback switch to select
The remote radio head unit comprising:
The method according to claim 1,
At least one of the plurality of temperature sensors being associated with each power amplifier and providing a temperature signal representative of the temperature of the associated power amplifier; And
Selecting one of the temperature signals for connection to the digital processor to cause the digital processor to generate a pre-distortion compensation signal that is suitable for each of the power amplifiers based at least in part on the temperature signal; Processor controlled temperature switch
The remote wireless head unit further comprising:
The method according to claim 1,
Wherein the digital processor is configured to implement an algorithm to ensure that each power amplifier output is aligned with another power amplifier output in terms of time, phase, and amplitude.
The method according to claim 1,
Wherein the digital processor determines a value of a power related variable associated with the power amplifier.
5. The method of claim 4,
Wherein the digital processor further generates a pre-distortion compensation signal for each of the power amplifiers based on the value of the power related variable.
The method according to claim 1,
Wherein the digital processor applies a crest factor reducton to the input signal.
3. The method of claim 2,
An analog-to-digital converter for converting the temperature signal to a digital signal for the digital processor
The remote wireless head unit further comprising:
The method according to claim 1,
Wherein the input signal is received from the optical input path,
The multi-channel remote radio head unit comprises:
An optical-electrical interface coupled to the digital processor and providing the input signal to the digital processor,
The remote wireless head unit further comprising:
The method according to claim 1,
A plurality of circulators each connected to an output of one of the plurality of power amplifiers;
A duplexer connected to the plurality of circulators; And
Each of the plurality of power amplifiers being coupled to one of the plurality of circulators and a plurality of receiver switches, each of which selectively connects an individual circulator to the digital processor to reduce insertion loss between the plurality of power amplifiers and the duplexer
The remote wireless head unit further comprising:
The method according to claim 1,
Wherein the digital processor is a field programmable gate array (FPGA)
Multi-channel remote wireless head unit.

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