KR101760193B1 - Substrate for manufacturing semiconductor package and method for manufacturing the same - Google Patents

Substrate for manufacturing semiconductor package and method for manufacturing the same Download PDF

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Publication number
KR101760193B1
KR101760193B1 KR1020150189884A KR20150189884A KR101760193B1 KR 101760193 B1 KR101760193 B1 KR 101760193B1 KR 1020150189884 A KR1020150189884 A KR 1020150189884A KR 20150189884 A KR20150189884 A KR 20150189884A KR 101760193 B1 KR101760193 B1 KR 101760193B1
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South Korea
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layer
insulating layer
substrate
vias
shape
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KR1020150189884A
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Korean (ko)
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KR20170079388A (en
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이창민
구희연
김병진
임호정
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앰코 테크놀로지 코리아 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/147—Semiconductor insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

The present invention relates to a substrate for fabricating a semiconductor package and a method of manufacturing the same, and more particularly, to a substrate for fabricating a semiconductor package having a new structure, in which more vias can be formed within a limited area by using a PID which is a photosensitive insulating material, .
That is, according to the present invention, an insulating layer stacked on and under the core layer is used as an insulating material of PID (Photo-Imageable Dielectric) material capable of photoresist processing, and a photoresist process including a masking and an exposure process The present invention provides a substrate for fabricating a semiconductor package and a method of manufacturing the same, in which more vias can be formed within a limited area of the substrate.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a substrate for manufacturing a semiconductor package,

The present invention relates to a substrate for manufacturing a semiconductor package and a method of manufacturing the same. More particularly, the present invention relates to a semiconductor package having a new structure, in which more vias can be formed within a limited area by using a photo-imageable dielectric (PID) And a method of manufacturing the same.

Semiconductor devices mounted on a mother board of various electronic apparatuses, that is, semiconductor packages, are manufactured in various types of structures according to their use, and basically have a substrate on which semiconductor chips are mounted, A conductive connecting means, and an input / output terminal for inputting and outputting a signal from the substrate to the outside.

The substrate may be a lead frame, a printed circuit board, a circuit film, a lead frame, or a lead frame substrate mixed with a resin layer, depending on the use and specification of the semiconductor package.

Generally, the printed circuit board, the circuit film, etc. of the substrate are made of a structure in which at least one insulating layer and a conductive layer are laminated around the core layer. In the core layer and the insulating layer, Conductive vias are formed.

Hereinafter, a conventional semiconductor package fabrication substrate and a fabrication process thereof will be described with reference to FIG.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a cross-sectional view showing a manufacturing process of a conventional semiconductor package fabricating substrate.

First, a first via 12, which is a core via, is formed in a core layer 10 of an insulating resin material forming a central skeleton of a substrate.

The first via 12 is a core via formed in the core layer 10 and includes a through hole 14 formed in the core layer 10 by laser drilling or the like and a through hole 14 formed in the through hole 14 by plating or the like And a conductive filler 16 that is coated and filled.

At this time, a first upper conductive layer 20 and a first lower conductive layer (not shown) are formed in the upper and lower portions of the first via 12 on the upper and lower surfaces of the core layer 10, 22 are extended to form a circuit arrangement of a predetermined pattern previously designed.

An upper insulating layer 24 and a lower insulating layer 26 covering the first upper conductive layer 20 and the first lower conductive layer 22 are formed on the upper and lower surfaces of the core layer 10, (Prepreg) lamination.

Next, as the electrically connecting vias that are electrically connected to the first upper conductive layer 20 and the first lower conductive layer 22 in the upper insulating layer 24 and the lower insulating layer 26, respectively, 28 are formed.

That is, the second vias 28 may be formed by a process of forming the through holes 27 using a laser drilling process in the same manner as the method of forming the first vias 12, which are core vias, And the like.

At this time, since the upper insulating layer 24 and the lower insulating layer 26 are laminated in the form of a prepreg using a general thermosetting resin material, It is not possible to form the holes 27 and the through holes 27 for the second vias 28 can be processed only by mechanical means such as laser drilling or the like.

A second upper conductive layer 30 and a second lower conductive layer 32 are formed on the surfaces of the upper insulating layer 24 and the lower insulating layer 26 so as to be conductively connected to the second vias 28, And extended to form a circuit arrangement of the designed specific pattern.

For reference, the substrate manufacturing process as described above is an example of manufacturing a substrate having a four-layer structure. Repeating processes such as laminating insulating layers to form vias and layering the conductive layers again can form four or more substrates have.

Hereinafter, the arranging positions and the relationship of the vias within the limited area of the conventional semiconductor package fabrication substrate manufactured as described above will be described with reference to FIGS. 2 and 3.

2 and 3 show a plan view of a part of the substrate. Reference numeral 12 denotes a first via, which is a core via formed in the core layer. Reference numeral 24 denotes an upper insulating layer. Indicating a second via formed in the insulating layer.

As shown in FIG. 2, a plurality of vias including the first via 12 and the second via 28 are arranged at a fine pitch in a limited area of the substrate.

In particular, a plurality of second vias 28 are intensively and conductively connected to a first top conductive layer 20 (e.g., a ground layer) having a defined area.

3, the first via 12 and the second via 28 are conductively coupled (via a one of the first upper conductive layers 20, for example, signal transmission layers) within a narrow area .

However, the conventional semiconductor package fabrication substrate has the following problems.

First, since the first upper conductive layer 20 has a limited area, there is a limit in connecting the first upper conductive layer 20 to the first upper conductive layer 20 by increasing the number of the second vias 28.

That is, although it is necessary to form more vias, which are electrical transmission paths, in the substrate in accordance with the demand for high integration of the semiconductor package, there is a limit to forming more vias in a limited area of the substrate.

In other words, since the first via 12 and the second via 28 in the limited area of the substrate form a fine parachute with each other as shown in FIGS. 2 and 3, there is a limit in forming a further via in a limited area of the substrate .

Secondly, since the insulating layer stacked above and below the core layer is laminated in the form of a prepreg using a general thermosetting resin material, the through hole for the second via should be processed only by laser drilling at a high price There are disadvantages.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and it is an object of the present invention to provide a photo-imageable dielectric (PID) material which is a photo- And a photoresist process including a development process, so that more vias can be formed within a limited area of the substrate, and a manufacturing method thereof.

According to an aspect of the present invention, there is provided a semiconductor device comprising: a core layer having a first via formed therein; A first upper conductive layer and a first lower conductive layer that are stacked and connected to the first via on the upper and lower surfaces of the core layer; An upper insulating layer and a lower insulating layer which are laminated on the upper and lower surfaces of the core layer while covering the first upper conductive layer and the first lower conductive layer in an insulating manner; A second via formed in the upper and lower insulating layers by a photoresist process; And a second upper conductive layer and a second lower conductive layer that are conductively connected to a second via on a surface of the upper insulating layer and the lower insulating layer; And a semiconductor substrate.

Particularly, the upper and lower insulating layers are used as a photo-imageable dielectric (PID) material which can serve as an insulating layer and a photoresist process.

The second via may include a through hole formed by exposing a non-masked area of the entire insulating layer, and a conductive filler filled in the through hole.

Preferably, the second vias are formed in a shape selected from a semicircular shape, an elliptical shape, and a crescent shape when viewed from above.

The second vias are formed as ground vias for the ground of the electrical signal in the upper insulating layer or the lower insulating layer, and the ground vias are electrically connected to the ground pattern formed on the surfaces of the upper insulating layer and the lower insulating layer. .

Preferably, the ground vias are formed in a shape selected from an ellipse, a rectangle, and a long strip.

According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: i) forming a first via in a core layer; Ii) forming a first upper conductive layer and a first lower conductive layer on the upper and lower surfaces of the core layer, the first upper conductive layer being conductively connected to the first via; Iii) laminating an upper insulating layer and a lower insulating layer on the upper and lower surfaces of the core layer, the upper insulating layer and the lower insulating layer being capable of insulating the first upper conductive layer and the first lower conductive layer, respectively; Iv) forming a second via in the upper and lower insulating layers using a photoresist process; And v) forming a second upper conductive layer and a second lower conductive layer on the surface of the upper insulating layer and the lower insulating layer, the second upper conductive layer being conductively connected to the second via; The present invention also provides a method of manufacturing a substrate for semiconductor package fabrication.

In particular, the step of forming the second via may include the steps of: applying a mask except for a region where the second via is to be formed in the entire area of the upper and lower insulating layers; Exposing an uncoated region of the upper and lower insulating layers to form a through hole; Filling a conductive filler in the through hole; .

Preferably, the second vias are formed in a shape selected from a semicircular shape, an elliptical shape, and a crescent shape when seen from above, and the region where the mask is not applied is a semicircular shape, an elliptical shape, And a second electrode formed on the second electrode.

According to another aspect of the present invention, there is provided a method of manufacturing a substrate, the method comprising: forming a ground via for a ground of an electrical signal in the upper insulating layer or the lower insulating layer; And a ground pattern forming step.

Preferably, the ground vias are formed in a shape selected from an ellipse, a rectangle, and a long band by the same photoresist process as the step of forming the second vias.

Further, in order to manufacture a substrate having four or more layers of the substrate of the present invention, a step of applying an insulating layer again on the second upper conductive layer and the second lower conductive layer, forming a via again in the applied insulating layer, And the step of forming the conductive layer is further repeated.

According to another aspect of the present invention, there is provided a method of manufacturing a substrate for manufacturing a semiconductor package, the method comprising: forming first and second vias in an insulating layer having a limited area among the respective layers of the substrate, A plurality of second via formation steps in which a plurality of first through holes are formed in an insulating layer having a predetermined area, and then conductive fillers are filled in the through holes; Forming a second through hole around the surface of the insulating layer at a position that is the same distance away from each of the second vias, and removing a portion of the second via to form a second through hole; Filling the second through hole with the same material as the insulating layer; Forming a third through hole in a portion filled with the same material and maintaining a predetermined distance from the second via; Filling the third through hole with a conductive filler to form a first via; Wherein the first vias are formed in a circular shape when viewed from above, and the plurality of second vias are formed in a shape selected from a semicircular shape, an elliptical shape, and a crescent shape And are disposed at the same distance from the first vias.

Through the above-mentioned means for solving the problems, the present invention provides the following effects.

First, the insulating layer laminated on and under the core layer forming the substrate skeleton is adopted as a PID (Photo-Imageable Dielectric) insulating material capable of photoresist processing, and the masking and exposure process for the PID insulating material By proceeding with the photoresist process, more vias can be formed within a limited area of the substrate.

Secondly, it is possible to exclude the use of expensive laser drilling when forming the second via for the insulating layer laminated in the form of a prepreg in the core layer by using the thermosetting resin material, thereby reducing the manufacturing cost can do.

Third, more vias can be formed in a limited same layer area of the substrate by forming a plurality of vias in the same layer having a limited area among the respective layers of the substrate so as to be densely arranged in a semicircle, an ellipse, and a crescent shape.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a cross-sectional view showing a main portion showing a manufacturing process of a conventional semiconductor package-
FIGS. 2 and 3 are a plan sectional view showing a state in which vias are arranged in a limited area of a conventional substrate for manufacturing a semiconductor package,
4 is a cross-sectional view illustrating a manufacturing process of a substrate for manufacturing a semiconductor package according to an embodiment of the present invention.
5 and 6 are a plan sectional view showing a substrate for manufacturing a semiconductor package according to an embodiment of the present invention,
7 is a plan sectional view showing a ground via portion of a substrate for manufacturing a semiconductor package according to an embodiment of the present invention,
8 is a plan view showing a manufacturing process of a substrate for manufacturing a semiconductor package according to another embodiment of the present invention.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

First Embodiment

The first embodiment of the present invention is based on the point that a larger number of vias can be formed within a limited area of the substrate by using a PID (Photo-Imageable Dielectric) material capable of photoresist processing.

4 is a cross-sectional view illustrating a manufacturing process of a substrate for fabricating a semiconductor package according to the first embodiment of the present invention.

First, a step of forming a first via 110, which is a core via, in a core layer 100 of an insulating resin material forming a central skeleton of the substrate is preceded (see Fig. 4A).

That is, a process of forming a through hole 112 by laser drilling or the like at a desired position of the core layer 100 and a process of coating a conductive filler 114 on the inner wall of the through hole 112 using a general plating process or the like A first via 110 is formed in the core layer 100 as a core via.

Subsequently, a first upper conductive layer 120 and a first lower conductive layer (not shown) are formed in the upper and lower portions of the first via 110 on the upper and lower surfaces of the core layer 100, 122 are elongated to form a circuit arrangement of a specific pattern designed in advance by a conventional plating process (see the drawing of FIG. 4 (a)).

Next, an upper insulating layer 130 and a lower insulating layer 130 are formed on the upper and lower surfaces of the core layer 100 to cover the first upper conductive layer 120 and the first lower conductive layer 122, respectively, The step of laminating the insulating layer 132 proceeds (see the drawing of FIG. 4B).

At this time, the upper and lower insulating layers 130 and 132 are used as a photo-imageable dielectric (PID) material which can serve as an insulating layer of a substrate and a photoresist process.

Unlike conventional photoresist materials that are removed after the photoresist process, the PID material can also serve as an insulating layer after the photoresist process.

Subsequently, a step of forming a second via 140 in the upper and lower insulating layers 130 and 132 using a photoresist process is performed.

More specifically, the step of forming the second vias 140 may include a step of applying the mask 146 except the region where the second via is to be formed in the entire area of the upper and lower insulating layers 130 and 132 (See the drawing (c) of FIG. 4), the process of exposing the upper and lower insulating layers 130 and 132 to an area to which the mask 146 is not yet applied (See FIG. 4 (e)) in which the through holes 142 are formed in the upper and lower insulating layers 130 and 132 by a plating process and a normal plating process or the like is applied to the inner walls of the through holes 142 (See FIG. 4 (f)) filling the conductive filler 144, and the like.

At this time, the through hole 142 is formed in a planar shape selected from a semicircular shape, an elliptical shape, and a crescent shape by the exposure process for the PID material as described above, and the conductive filler 144 is formed in the through hole 142 The filled second vias 140 are also formed in a shape selected from a semicircular shape, an elliptical shape, and a crescent shape when viewed from above.

5, a second via 140 having a planar shape selected from a semicircular shape, an elliptical shape, and a crescent shape is attached to the periphery of the first via 110, As shown in FIG.

More specifically, a plurality of vias including the first vias 110 and the second vias 140 are arranged at a fine pitch within a limited area of the substrate, but a plurality of second vias 28 are arranged in a PID An elliptical shape, and a crescent shape by using a masking and exposure process for the material, a larger number of second vias 28 can be formed within a limited area.

For example, even though the second vias 28 are intensively and conductively connected to the first top conductive layer 120 (e.g., ground layer) having a limited area as shown in FIG. 5, the second via 28 Since the shape has a shape selected from a semicircular shape, an elliptic shape, and a crescent shape compared to a conventional circular shape, more vias can be formed in a limited area of the substrate.

6, the first and second vias 110 and 140 may be electrically conductive through one of the first top conductive layers 120 (e.g., signal transmission layers) within a narrow area of the substrate At this time, since the second vias 140 have a shape selected from a semicircular shape, an elliptic shape, and a crescent shape, more vias can be formed in a limited area of the substrate.

As shown in FIGS. 2 and 3, conventionally, circularly-shaped second vias 28 are concentrically arranged around the first via 12 in a limited area of the substrate, 5 and 6, the second via 140 of the present invention has a semi-circular, elliptical, and convex shape having a smaller area than the conventional second via 28. However, as shown in FIGS. 5 and 6, It has a crescent shape and can be formed more in a limited area of the substrate.

Next, a second upper conductive layer 150 and a second lower conductive layer 152, which are conductively connected to the second vias 140, are formed on the surfaces of the upper insulating layer 130 and the lower insulating layer 132, Is formed by a conventional plating process or the like.

That is, the second upper conductive layer 150 and the second lower conductive layer 152, which are conductively connected to the second vias 140, are formed on the surfaces of the upper insulating layer 130 and the lower insulating layer 132 in advance And extended to form a circuit arrangement of the designed specific pattern.

Meanwhile, the second vias 140 are formed of ground vias and can be formed in different shapes according to the design of the substrate, as shown in FIG. 7

7, a second via or ground via 160 is formed in the upper insulating layer 130 or the lower insulating layer 132 for the ground of an electrical signal, and the upper insulating layer 130, And a ground pattern 162 that is conductively connected to the ground vias 160 is formed on the surface of the lower insulating layer 132.

At this time, the ground vias 160 may be formed in the same manner as the step of forming the second vias in the insulating layers 130 and 132 made of the PID material using the photoresist process as described above, and the semi- And may have a shape selected from an ellipse, a rectangle, and a long band shape having a narrow width.

Therefore, it is difficult to form ground vias at desired positions in a limited area. However, as shown in FIG. 7, in the present invention, an elliptical shape having a narrow width , A rectangle, a long band, etc., it is possible to secure a peripheral space and utilize the secured peripheral space as a space for forming the conductive pattern 170 (= conductive trace).

The substrate manufacturing process of the present invention as described above is an example of manufacturing a substrate having a four-layer structure, and includes the steps of applying another insulating layer on the second upper conductive layer and the second lower conductive layer, Forming a conductive layer on the surface of another insulating layer, and the like are further repeated to form a substrate having four or more layers.

Second Embodiment

The second embodiment of the present invention is characterized in that an insulating layer is formed of a general prepreg or ABF material or a PID material as in the first embodiment so that more vias can be formed within a limited same layer area of the substrate There is a point in.

That is, the second embodiment of the present invention is characterized in that a plurality of vias can be formed in the same layer on which vias are formed, that is, on the same layer having a limited area.

8 is a plan view showing a process of manufacturing a substrate for fabricating a semiconductor package according to another embodiment of the present invention.

First, a plurality of first through holes 212 are formed in one insulating layer 200 having a limited area among the respective layers of the substrate, and then the conductive fillers 214 are filled in the through holes 212 , And a plurality of second vias 210 are formed at regular intervals (see FIG. 8 (a)).

Next, a second through hole 216 is formed on the surface of the same insulating layer 200 at the same distance from each of the second vias 210 by using a laser drilling process or the like, The step of forming the second through hole 216 proceeds while removing a portion thereof (see the drawing of FIG. 8B).

At this time, the second vias 210 have a semicircular, elliptical or crescent shape with a part thereof being removed.

Preferably, the inner portion of the second via 210 is removed by a laser drilling process to form the second through hole 216. The conductive filler 214 is plated on the removed portion, 2 vias 210 form a semicircular, oval or crescent-shaped planar shape.

The second via 210 is then filled with the same insulating material as the insulating layer 200 (e.g., prepreg material, ABF material, PID material, etc.) in the second through hole 216, Semi-circular, elliptical or crescent-shaped planar shapes and arranged so as to be insulated from each other (refer to the drawing (c) of FIG. 8).

A second via 210 is formed in a portion of the insulating layer 200 filled with the same material as the insulating layer 200 in the second through hole 216 for forming the first via 220, A third through hole 218 maintained at a constant distance is formed by a laser drilling process or the like (see the drawing of FIG. 8 (d)).

At this time, the third through holes 218 are formed to have a smaller diameter than the second through holes 216, so that they are maintained at a certain distance from the second via holes 210.

Subsequently, the conductive filler 214 is filled in the third through-hole 218 to complete the first via 220.

Accordingly, a plurality of second vias 210, that is, semicircular, elliptic, and the like, which maintain a certain distance about the first via 220, are formed in the insulating layer 200 having a limited area and forming the same layer among the respective layers of the substrate. Or a plurality of second vias 210 having a crescent-shaped planar shape are arranged adjacently (see the drawing of FIG. 8 (e)).

As described above, the second vias according to the second embodiment of the present invention are formed in a semicircular, elliptic or crescent-shaped planar shape unlike the conventional circular planar shapes, so that the second vias in the same layer More vias can be formed.

100: core layer
110: 1st Via
112: Through hole
114: conductive filler
120: first upper conductive layer
122: first lower conductive layer
130: upper insulating layer
132: Lower insulating layer
140: Second Via
142: Through hole
144: conductive filler
146: Mask
150: second upper conductive layer
152: second lower conductive layer
160: Ground Via
162: Ground pattern
170: conductive pattern
200: insulating layer
210: Second Via
212: first through hole
214: conductive filler
216: second through hole
218: Third through hole
220: 1st Via

Claims (17)

A core layer having a first via formed therein;
A first upper conductive layer and a first lower conductive layer that are stacked and connected to the first via on the upper and lower surfaces of the core layer;
An upper insulating layer and a lower insulating layer which are laminated on the upper and lower surfaces of the core layer while covering the first upper conductive layer and the first lower conductive layer in an insulating manner;
A second via formed in the upper and lower insulating layers by a photoresist process; And
A second upper conductive layer and a second lower conductive layer that are conductively connected to the second via on the surfaces of the upper insulating layer and the lower insulating layer;
/ RTI >
The second vias are formed as ground vias for the ground of the electrical signal in the upper or lower insulating layer, and the ground vias are conductively connected to the ground pattern formed on the surfaces of the upper insulating layer and the lower insulating layer Wherein the substrate is a semiconductor substrate.
The method according to claim 1,
Wherein the upper and lower insulating layers are formed of a PID (Photo-Imageable Dielectric) material which can serve as an insulating layer and a photoresist process.
The method according to claim 1,
Wherein the second via comprises a through hole formed by exposing an uncovered region of the entire insulating layer and a conductive filler filled in the through hole.
The method of claim 3,
Wherein the second vias are formed in a shape selected from a semicircular shape, an elliptic shape, and a crescent shape when viewed from above.
delete The method according to claim 1,
Wherein the ground vias are formed in a shape selected from an elliptical shape, a rectangular shape, and a long band shape.
I) forming a first via in the core layer;
Ii) forming a first upper conductive layer and a first lower conductive layer on the upper and lower surfaces of the core layer, the first upper conductive layer being conductively connected to the first via;
Iii) laminating an upper insulating layer and a lower insulating layer on the upper and lower surfaces of the core layer, the upper insulating layer and the lower insulating layer being capable of insulating the first upper conductive layer and the first lower conductive layer, respectively;
Iv) forming a second via in the upper and lower insulating layers using a photoresist process;
V) forming a second upper conductive layer and a second lower conductive layer on the surface of the upper insulating layer and the lower insulating layer, the second upper conductive layer being conductively connected to the second via;
/ RTI >
Forming a ground via for an electrical signal ground on the upper insulating layer or the lower insulating layer and forming a ground pattern on the surface of the upper insulating layer and the lower insulating layer so as to be conductive with the ground vias Wherein the substrate is a semiconductor substrate.
The method of claim 7,
Wherein the upper and lower insulating layers are made of a PID (Photo-Imageable Dielectric) material that can serve as an insulating layer and a photoresist process.
The method of claim 7,
Wherein forming the second via comprises:
Applying a mask except for a region of the entire upper and lower insulating layers where a second via is to be formed;
Exposing an uncoated region of the upper and lower insulating layers to form a through hole;
Filling a conductive filler in the through hole;
Wherein the substrate is made of a metal.
The method of claim 9,
Wherein the second vias are formed in a shape selected from a semicircular shape, an elliptical shape, and a crescent shape when viewed from above, and the region where the mask is not applied is formed into a shape selected from a semicircular shape, an elliptical shape, Wherein the substrate is a semiconductor substrate.
delete The method of claim 7,
Wherein the ground vias are formed in a shape selected from an elliptical shape, a rectangular shape, and a long strip shape by the same photoresist process as the step of forming the second vias.
The method of claim 7,
Applying the insulating layer again over the second upper conductive layer and the second lower conductive layer to produce a substrate having four or more layers, forming a via again in the applied insulating layer, and forming a conductive layer Wherein the step of forming the semiconductor substrate is repeatedly performed.
A plurality of second via formation steps in which a plurality of first through holes are formed in an insulating layer constituting the same layer of each layer of a substrate and then filled with conductive fillers in the through holes;
Forming a second through-hole around a surface of the same insulating layer at a same distance from each of the second vias, removing a portion of the second via to form a second through-hole;
Filling the second through hole with the same material as the insulating layer;
Forming a third through hole in a portion filled with the same material and maintaining a predetermined distance from the second via;
Filling the third through hole with a conductive filler to form a first via;
Wherein the substrate is a silicon wafer.
15. The method of claim 14,
Wherein the insulating layer is one selected from the group consisting of a prepreg-type insulating material, an ABF insulating material, and a PID (Photo-Imageable Dielectric) material capable of performing a photoresist process while serving as an insulating material.
15. The method of claim 14,
Wherein the first through holes, the second through holes, and the third through holes are formed by a laser drilling process.
A substrate for manufacturing a semiconductor package manufactured by the method for manufacturing a semiconductor package according to any one of claims 14 to 16,
A first via and a second via are formed in the same layer area of each layer of the substrate. The first via is formed in a circular shape as viewed from above, and the plurality of second vias are formed in a selected one of semicircular shape, elliptical shape, And the second via is formed at a position spaced the same distance from the first via.
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