KR101757943B1 - Faulty chip marking method - Google Patents
Faulty chip marking method Download PDFInfo
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- KR101757943B1 KR101757943B1 KR1020120021296A KR20120021296A KR101757943B1 KR 101757943 B1 KR101757943 B1 KR 101757943B1 KR 1020120021296 A KR1020120021296 A KR 1020120021296A KR 20120021296 A KR20120021296 A KR 20120021296A KR 101757943 B1 KR101757943 B1 KR 101757943B1
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- protective film
- chip
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- Computer Hardware Design (AREA)
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Abstract
The present invention relates to a defective chip marking method capable of marking defective chips at a high speed while preventing contamination of surrounding chips. A defect chip marking method according to the present invention includes: a step of placing a wafer including a plurality of chips, on which alignment marks are formed and having a protective film on one surface, on a stage; A step of aligning the wafer by driving a stage; and a marking step of irradiating the wafer with a laser to perform marking of a defective chip among a plurality of chips included in the wafer, wherein in the marking step, Is irradiated with the defective chip after passing through the protective film, and marking is performed on the surface to which the protective film is attached.
Description
The present invention relates to a wafer marking method, and more particularly, to a method of marking a defective chip using a laser.
The general integrated circuit manufacturing process is divided into a wafer fabrication step, a chip inspection step and a chip packaging step sequentially. Recently, packaging technology has been developed as advanced packaging technology in order to reduce packaging volume and improve the efficiency of integrated circuits in response to demands for thinning and compacting of electronic products. Since the advanced packaging method is high in cost, it is desirable to conduct a defect inspection on the chip before proceeding to the packaging, thereby eliminating the defective chips described above before the subsequent packaging process, thereby saving unnecessary cost in the packaging process .
In the conventional case, a process of marking a defective chip with ink has been used. However, in the case of such an ink marking method, the size (size) of the ink mark is limited due to the inner diameter of the ink tube that ejects the ink and the adhesiveness of the ink itself or other causes. In addition, if the size of the chip is less than a certain size, the ink may easily penetrate into another chip and easily cause contamination. Therefore, the user must manually inspect the ink-marked wafer. This method not only increases manpower but also increases the ink marking time and also requires a baking process to dry the ink, thus greatly affecting productivity. Furthermore, the ink marked on the wafer may easily deteriorate or peel off after a certain period of time, and the inspection data can not be stored for a long period of time as reference evidence for post-processing.
In order to solve such a problem, Japanese Patent Laid-Open No. 10-2009-0012977 (hereinafter referred to as prior art) has proposed a device and a method for marking a chip using a laser.
According to the prior art, the wafer is fixed on the stage, and marking is performed by directly irradiating the defective chip with the laser while moving the stage.
However, in this case, there is a problem that the chips generated in the process of marking by the laser (that is, the particles generated as the wafer flares) contaminate other peripheral chips.
Further, the laser beam is moved in a fixed state. In order to precisely move the entire stage, the moving speed of the stage must be very slow, and the marking speed itself is deteriorated.
It is an object of the present invention to provide a bad chip marking method capable of performing marking on a bad chip at a high speed while preventing the surrounding chip from being contaminated.
A defect chip marking method according to the present invention includes: a step of placing a wafer including a plurality of chips, on which alignment marks are formed and having a protective film on one surface, on a stage; A step of aligning the wafer by driving a stage; and a marking step of irradiating the wafer with a laser to perform marking of a defective chip among a plurality of chips included in the wafer, wherein in the marking step, Is irradiated with the defective chip after passing through the protective film, and marking is performed on the surface to which the protective film is attached.
According to the present invention, particles generated during the marking are prevented from being contaminated by the chips, and the marking speed is improved.
1 is a schematic flowchart of a bad chip marking method according to an embodiment of the present invention.
2 is a schematic block diagram of a marking apparatus for implementing a defective chip marking method according to an embodiment of the present invention.
Fig. 3 is a view for comparing the case where marking is performed with the protective film attached and the case where marking is performed by directly irradiating the wafer with a laser.
Hereinafter, a defective chip marking method according to a preferred embodiment of the present invention will be described with reference to the accompanying drawings.
FIG. 1 is a schematic flowchart of a bad chip marking method according to an embodiment of the present invention, FIG. 2 is a schematic configuration diagram of a marking apparatus for implementing a bad chip marking method according to an embodiment of the present invention, 3 is a view for comparing the case where the marking is performed with the protective film attached and the case where the wafer is marked by laser irradiation.
Referring to FIGS. 1 to 3, the defect chip marking method M100 according to the present embodiment includes a seating step S10, an alignment step S20, and a marking step S30. Hereinafter, the configuration of the
2, the marking
The
The supplied wafer is provided with a plurality of chips, and the plurality of chips include defective chips. Alignment marks for alignment are formed on the wafer.
On the other hand, the
The
The alignment
The
Hereinafter, a process of marking a defective chip using the marking
In the seating step S10, the wafer on which the pre-processing is completed is placed on the stage. At this time, as mentioned above, the protective film is attached to the front surface of the wafer.
In the aligning step S20, the alignment mark formed on the wafer is recognized, and the wafer is aligned by driving the stage. At this time, it is possible to accurately recognize the alignment marks by irradiating the wafer with appropriate light with RGB illumination.
In the marking step S30, a laser is irradiated with a defective chip among a plurality of chips included in the wafer to perform marking. Here, the information on the defective chip (coordinates of the defective chip) is obtained in a pre-inspection step (chip inspection step), and the defective chip is irradiated with the laser using the information to perform marking. At this time, the laser irradiated from the laser irradiation part is irradiated from the front surface of the defective chip after passing through the protective film, thereby marking the entire surface of the defective chip.
Hereinafter, advantages of the present invention will be described.
3 (A), when the laser beam is irradiated onto the wafer W in the state that the protective film f is attached, the particles generated during the marking, i.e., the particles generated as the surface of the wafer is flared, are immediately protected Is adhered to the film (f), so that these particles are prevented from contaminating the peripheral chips. However, as shown in FIG. 3 (B), when the laser is directly irradiated onto the wafer, there is a problem that the particles contaminate the peripheral chips.
3 (A), a diffused reflection occurs between the surface of the wafer W and the interface of the protective film f when the laser is irradiated with the protective film attached thereto, The roughness of the surface is improved. That is, a plurality of grooves h are formed in a concavo-convex shape at the point where the laser beam is irradiated, whereby the depth of each groove is not deep but the recognition rate of marking is improved. However, when the laser is directly irradiated onto the wafer as shown in FIG. 3 (B), only one groove h is formed at the irradiation point. Therefore, the marking recognition rate is lowered compared with FIG. 3A. When the depth of the groove is increased to increase the marking recognition rate, there is a risk that cracks may be generated in the chip itself.
Further, in the prior art, since the stage itself moves and the defective chip is moved to the laser irradiation position and then the laser is irradiated, it takes a long time to move the stage, which lowers the marking speed. However, according to this embodiment, since the stage is fixed and the laser irradiation unit of the galvano scanner type is driven and the bad chip is irradiated with the laser by the marking, the marking speed is improved to about five times or more.
While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is clearly understood that the same is by way of illustration and example only and is not to be taken by way of limitation in the embodiment in which said invention is directed. It will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the scope of the appended claims.
100 ... Marking
20
40 ... RGB lights
Claims (1)
An alignment step of irradiating RGB light to recognize the alignment mark and driving the stage to align the wafer; And
And a marking step of fixing the stage and irradiating a laser beam onto the wafer by driving a galvano scanner type laser irradiation unit to perform marking of a defective chip among a plurality of chips included in the wafer,
Wherein in the marking step, the laser is irradiated with the defective chip after passing through the protective film, so that marking is performed on the surface to which the protective film is attached.
Priority Applications (1)
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KR1020120021296A KR101757943B1 (en) | 2012-02-29 | 2012-02-29 | Faulty chip marking method |
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KR1020120021296A KR101757943B1 (en) | 2012-02-29 | 2012-02-29 | Faulty chip marking method |
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KR20130099636A KR20130099636A (en) | 2013-09-06 |
KR101757943B1 true KR101757943B1 (en) | 2017-07-13 |
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KR1020120021296A KR101757943B1 (en) | 2012-02-29 | 2012-02-29 | Faulty chip marking method |
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KR (1) | KR101757943B1 (en) |
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2012
- 2012-02-29 KR KR1020120021296A patent/KR101757943B1/en active IP Right Grant
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