KR101756359B1 - Circuit for preventing reading error of fuse data - Google Patents

Abstract

The present invention relates to a fuse data reading circuit and, more particularly, to a fuse data lead error prevention circuit for preventing a read error that may occur during a fuse data read, A fuse dummy cell in which two conductive type transistors are connected in series to form one fuse dummy cell and a fuse dummy cell in which fuse data in the fuse cell group is read when the gate bias voltage applied to the fuse dummy cell is stabilized, And a fuse cell lead active signal generator for generating and outputting a signal.

Description

FIELD OF THE INVENTION [0001] The present invention relates to a fuse data read error prevention circuit,

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a fuse data reading circuit, and more particularly, to a fuse data lead error prevention circuit for preventing a read error that may occur in a fuse data read.

As a large amount of memory cells are integrated in the semiconductor memory device, the amount of information previously stored for setting the operating environment of the semiconductor memory device also increases. A technique employing a fuse circuit is generally used to store various information for setting the operating environment of the semiconductor memory device.

Redundancy information for the defective memory cell, DC level trimming information of the semiconductor memory device, Mode Register Set (MRS) information, and the like are stored in the fuse circuit.

The fuse circuit includes a laser fuse whose connection is controlled by laser irradiation, an electrical fuse whose connection is controlled by an electrical signal, or an anti-fuse circuit which converts from a high resistance state to a low resistance state Etc. may be used.

The reading operation of the fuse circuit may be performed in the power-up phase. When an external voltage is applied to the semiconductor memory device, a power-up signal for driving the semiconductor memory device in response to an external voltage is generated, and a leading operation of the fuse circuit is activated simultaneously with the generation of the clock signal synchronized with the power-up signal.

At this time, the output voltage of the DC circuits of the semiconductor memory device after the leading operation is activated may be in an unstable state, and a certain time is required for stabilizing the output voltage of the DC circuits. When the reading operation of the fuse circuit is performed under the same sensing condition (sensing voltage, clock frequency, etc.) in the reading interval having different operating environments as described above, sufficient sensing sensitivity can be provided in the stable interval. However, in the unstable interval, It may lead to a leading error of the fuse data, which may cause operation errors of the semiconductor memory device. Referring to the accompanying drawings,

FIG. 1 illustrates a circuit diagram for explaining a reading operation of a general fuse circuit.

Referring to FIG. 1, a current bias circuit 10 is connected to the left side of the fuse cell group 20 corresponding to the fuse circuit. Assuming that the VDD power is supplied by power-up, the NMOS transistor MN1 is turned on by the diode connection of the NMOS transistor N1 constituting the current bias circuit 10, and accordingly, the PMOS transistor MP1 is also turned on. When the gate bias voltages VPB and VNP are applied to the fuse cell group 20, the logic level "1" is output at the point A in the state where the fuse F1 is connected. When the fuse F1 is open, The logic level "0" is output. That is, the state of the fuse F1 is latched and output in a period in which the power is applied, whereby the reading operation of the fuse circuit is performed.

However, when VDD is increased immediately after power-up, the fuse data should be read in the section where the gate bias voltages VPB and VNP are stabilized, but the reading of the fuse data may be performed in an interval in which the gate bias voltages VPB and VNP are unstable. Can lead to the result of reading of the data.

Also, since there is a miss matching between the bias transistors, the process variation also increases as the number of fuse cells increases. In a period in which the gate bias voltages VPB and VNP are stabilized due to process variations of the bias transistors, Which may result in the reading of the wrong fuse data.

Korean Patent Publication No. 10-0147194 Korean Patent Publication No. 10-2013-0111781

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a read active signal capable of reading fuse data after a gate bias voltage is stabilized, The present invention provides a fuse data lead error prevention circuit which can prevent an error,

It is still another object of the present invention to provide a fuse data reading error prevention circuit capable of stably reading the fuse data regardless of a process deviation between the bias transistors.

According to an aspect of the present invention, there is provided a fuse data reading error prevention circuit,

A fuse dummy cell in which a fuse and at least two conductive transistors are connected in series between a power supply terminal and a ground to constitute one fuse dummy cell,

And a fuse cell lead active signal generating unit for generating and outputting a read active signal capable of reading the fuse data in the fuse cell group when the gate bias voltage applied to the fuse dummy cell is stabilized,

Wherein the fuse cell lead active signal generator comprises:

A comparison signal generator having a resistor and two conductive transistors serially connected between the power supply terminal and the ground so as to be connected in parallel with the fuse dummy cell and to which the gate bias voltage is applied;

A voltage level output from a first output node to which two conductivity-type transistors constituting the fuse dummy cell are connected in common and a voltage level output from a second output node which is a common connection node of two conductivity type transistors constituting the comparison signal generation unit And a logic operation circuit for comparing the voltage levels to generate and output the read active signal.

Furthermore,

A first Schmitt trigger element for outputting a logic signal triggered according to a voltage level output from the first output node,

A second Schmitt trigger element for outputting a logic signal triggered according to a voltage level output from the second output node,

An inverting element for inverting an output signal of the first Schmitt trigger element,

And a logical product multiplying the output signal of the second Schmitt trigger element and the inverting element by a logical multiplication and outputting the read active signal.

In the fuse data lead error prevention circuit having the above-described configuration,

The voltage level rising rate of the first output node is lower than the voltage level rising rate of the third output node which is a common connection node of the two conductivity type transistors constituting the fuse cell in the fuse cell group, And a resistance value of each of the conductive type transistors connected between the ground and the ground is relatively set,

The voltage level descending rate of the second output node is lower than the voltage logic level descending rate of the fourth output node which is a common connection node of the two conductivity-type transistors connected in series with the fuse fuse in which the fuse fuse is connected between the power- A resistance value of each conductive type transistor connected between each of the second and fourth output nodes and the ground is relatively set.

And a resistance value of a fuse constituting the fuse dummy cell is set to have a resistance value larger than a fuse resistance of the fuse cell to reduce a current supplied to the first output node,

The resistance value of the resistor constituting the comparison signal generator is set to have a smaller resistance value than the fuse fuse in the fuse cell group to increase the current supplied to the second output node.

The switching device according to claim 1, further comprising: a switching device that switches between one of two conductive transistors constituting a fuse cell in the group of fuse cells and the ground in accordance with application of the read active signal, The circuit may be designed.

According to the above-mentioned problem solving means, the fuse data lead error prevention circuit according to the embodiment of the present invention can prevent the fuse cell from being unstable in a section in which the gate bias voltage applied to the fuse cell group is unstable due to the process variation of the conductivity type transistors, In order to prevent the fuse data from being read, a signal RAS indicating the read of the fuse data is designed to be generated after the gate bias voltage is stabilized. Therefore, even if the supply voltage is in an unstable state, the reading error of the fuse data can be prevented.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a circuit diagram illustrating a reading operation of a general fuse circuit. FIG.
2 is a block diagram illustrating a peripheral block configuration of a fuse data lead error prevention circuit 110 according to an embodiment of the present invention.
3 is a specific circuit example of the fuse data lead error prevention circuit shown in Fig.
4 is a diagram illustrating an example of a fuse data lead error prevention circuit according to another embodiment of the present invention.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a block diagram illustrating a fuse data lead error prevention circuit 110 according to an embodiment of the present invention. FIG. 3 is a circuit diagram of a fuse data lead error prevention circuit 110 shown in FIG. .

Referring first to FIG. 2, a fuse data lead error prevention circuit 110 according to an embodiment of the present invention is located between a current bias circuit 100 and a fuse cell group 130.

2, a current bias circuit 100 generates and outputs a plurality of gate bias voltages VPB and VNB during power-up, and the plurality of gate bias voltages VPB and VNB are used as a fuse data lead error prevention Is applied to the circuit 110 and the fuse cell group 130 in a covalent manner.

The fuse data lead error prevention circuit 110 includes a fuse dummy cell in which a fuse and at least two conductive transistors are connected in series between a power supply terminal VDD and the ground to constitute one fuse dummy cell, A fuse cell lead active signal generator (hereinafter referred to as " Fuse Cell Read ") generating a read active signal (also referred to as RAS) capable of reading fuse data when the gate bias voltages VPB and VNB applied to the fuse dummy cells are stabilized 110).

2, the external device 120 reads the fuse data from the fuse cell group 130 in response to the fuse cell read active signal RAS being input from the fuse data lead error prevention circuit 110. This external device 120 can be implemented as a logic or controller for reading the fuse data.

2, the lead active signal RAS is applied to the external device 120 reading the fuse data. However, as shown in FIG. 4, the fuse cell group 130 is directly connected to the external device 120 without the intervention of the external device 120, And the read active signal RAS may be applied to the memory cells. In this case, a switch element to be switched by the lead active signal RAS must be separately added to the fuse cell group 130. This will be described in more detail with reference to FIG.

2, a fuse cell group 130 includes a plurality of fuse cells as already known, the fuse cell having a fuse and at least two challenges Type transistors are connected in series to form one fuse cell. In the fuse cell group 130, as shown in FIG. 3, a fuse fuse R3 and conductive type transistors MP3 and MN3 are connected in parallel with respective fuse cells.

Hereinafter, the configuration and operation will be described with reference to FIG. 3 illustrating a detailed circuit diagram of the fuse data lead error prevention circuit 110 and its peripheral structures having the above-described configuration.

The current bias circuit 100 for generating and outputting the gate bias voltages VPB and VNB firstly includes an NMOS transistor D1 connected between the power supply terminal VDD and the ground and a PMOS transistor M1 connected in parallel to the NMOS transistor D1, A resistor R connected in series between the supply terminal VDD and the ground, a PMOS transistor MP1, and an NMOS transistor MN1.

When power is supplied according to power-up, the current bias circuit 100 sequentially turns on the NMOS transistor D1, the NMOS transistor MN1, and the PMOS transistor MP1 by the diode connection to generate the gate bias voltages VPB and VNB, To the fuse data lead error prevention circuit 110 and the fuse cell group 130. [

The fuse data lead error prevention circuit 110 shown in Fig.

A fuse F2 having the same resistance value as that of the fuse cell F3 and at least two conductive transistors, that is, a PMOS transistor MP4 and an NMOS transistor MN4 are connected in series between the power supply terminal VDD and the ground to form one fuse dummy cell A resistor R2 (having a resistance value larger than the fuse fuse R3), a PMOS transistor MP5, and an NMOS transistor MN5 are connected between the power supply terminal VDD and the ground to be connected in parallel with the fuse dummy cell And a comparison signal generating unit connected in series.

The gate bias voltages VPB and VNB are applied to the gate terminals of the conductivity type transistors constituting the fuse dummy cell and the comparison signal generation unit after power-up so that the common connection of the two conductivity type transistors MP4 and MN4 constituting the fuse dummy cell A change occurs in the voltage level output from the first output node P1 which is the node and the second output node P2 which is the common connection node of the two conductivity type transistors MP5 and MN5 constituting the comparison signal generation portion.

When the gate bias voltage is confirmed to be stabilized by comparing the voltage level changes, a logic operation circuit is designed and included in the fuse data lead error prevention circuit 110 so that the read active signal RAS can be generated.

That is, the fuse data lead error prevention circuit 110 compares the voltage level output from the first output node P1, which is the common connection node of the two conductivity type transistors MP4 and MN4 constituting the fuse dummy cell, (T1, T2) for generating and outputting a read active signal RAS by comparing the voltage levels outputted from the second output node P2, which is a common connection node of the two conductivity type transistors MP5, MN5 constituting the generation portion, , T3, T4).

The logic operation circuits T1, T2, T3 and T4 include a first Schmitt trigger element T2 for outputting a logic signal triggered according to a voltage level output from the first output node P1,

A second Schmitt trigger element T1 for outputting a logic signal triggered according to a voltage level output from the second output node P2,

An inversion element T3 for inverting an output signal of the first Schmitt trigger element T2,

And a logic multiplication element T4 that outputs the read active signal RAS by logically multiplying the output logic signal of the second Schmitt trigger element T1 and the inverted element T3. It will be apparent to those skilled in the art that such a logic operation circuit can be implemented by combining various logic elements.

In order to generate the read active signal RAS when the gate bias voltage supplied by the current bias circuit 100 is stabilized,

The voltage level rising rate of the first output node P1 is higher than the third output node A (A), which is the common connection node of the two transistors MP2 and MN2 constituting the fuse cell in the fuse cell group 130, The resistance values of the respective conductive transistors MN4 and MN2 connected between the first and third output nodes P1 and A and the ground are relatively set so that MN4 is higher than MN2 It is set to have a relatively small resistance value)

And a voltage level descending rate of the second output node (P2) is lower than a voltage level descending rate of the fourth output node (B), and an angle between the second and fourth output nodes The resistance values of the conductivity type transistors MN5 and MN3 are relatively set (MN5 is set to have a relatively larger resistance value than MN3).

When the resistance value of the NMOS transistor MN4 is set smaller than the resistance value of the NMOS transistor MN2 in the fuse cell group 130, the output current of MN4 is increased relative to the output current of MN2 when the gate bias voltage VNB is applied, When the voltage level rising speed of the output node P1 is decreased and the resistance value of MN5 is set to have a resistance value larger than that of MN3, the output current of MN5 is decreased relative to the output current of MN3 so that the voltage level falling rate of the second output node P2 is decreased do.

When the power is up, the gate bias voltage is applied to the gate terminals of the NMOS transistors MN4 and MN5, and the voltage level of the first output node P1 gradually increases. After a certain time (securing period) is secured, I have. A signal of a high level is applied to the first input terminal of the AND gate T4 through the first Schmitt trigger element T2 and the inverting element T3 and the voltage level of the second output node P2 is also gradually reduced to " Quot; low "level signal is applied to the second input terminal of the AND gate T4 through the second Schmitt trigger element T1.

Thus, the read active signal RAS of the "high" level is generated in the section where the gate bias voltage is sufficiently stabilized, and is transmitted to the external device 120, thereby reading the data loaded in the fuse cell by the external device 120.

That is, in the fuse data lead error prevention circuit 110 according to the embodiment of the present invention, in order to prevent the fuse data from being read inevitably in an interval in which the gate bias voltage is unstable due to the process variation of the conductive type transistors or the instability of the supply voltage , And a signal (RAS) indicating the read of the fuse data is designed to be generated after the gate bias voltage is stabilized. Therefore, even if the supply voltage is in an unstable state, the reading error of the fuse data can be prevented.

In the above embodiment, the lead active signal RAS is generated after the stabilization period of the gate bias voltage by adjusting the resistance values of the conductive type transistors MN2 to MN5. However, the fuse F2 and the fuse cell F3 resistance The generation of the lead active signal RAS can also be controlled through adjustment.

More specifically, first, the resistance value of the fuse F2 constituting the fuse dummy cell is set to have a resistance value larger than that of the fuse F3 in the fuse cell group 130 to reduce the current supplied to the first output node P1,

The resistance value of the resistor R2 constituting the comparison signal generator may be set to have a resistance value smaller than the fuse fuse R3 in the fuse cell group 130 to set the circuit resistance value to increase the current supplied to the second output node .

When the fuse F2 and the resistor R2 are set so as to reduce and increase the current supplied to the first output node P1 and the second output node P2, respectively, the lead active signal of the "high" level in the period in which the gate bias voltage is sufficiently stabilized (RAS) is generated in the logic operation circuit and transferred to the external device 120, so that the external device 120 normally reads the data loaded in the fuse cell.

FIG. 4 illustrates a fuse data lead failure prevention circuit according to another embodiment of the present invention. In contrast to the fuse data lead failure prevention circuit 110 shown in FIG. 3, the lead active A signal RAS is applied directly to the fuse cell group 130 and the fuse cell group 130 is supplied with one of two conductive transistors constituting the fuse cell, that is, between the emmos transistor MN2 and the ground, A switching element SW1 for switching according to application of the read active signal RAS between the fuse fuse R3 and one of two conductive transistors connected in series, that is, the emmos transistor MN3 and the ground, The other parts are the same except that SW2 is further included.

In the embodiment in which the switching elements SW1 and SW2 which are switched according to the read active signal RAS are included in the fuse cell group 130, the switching elements SW1 and SW2 are turned on by the read active signal RAS generated after the gate bias voltage is stabilized, SW2 are switched so that the NMOS transistors MN2 and MN3 in the fuse cell group 130 are turned on so that the fuse data can be output normally through the third output node A and the fourth output node B. [

Therefore, by using the fuse data lead error prevention circuit and the switching elements located in the fuse cell group 130 shown in FIG. 4, it is possible to prevent the reading error of the fuse data from being prevented even if the supply voltage is in an unstable state. .

While the invention has been shown and described with reference to certain embodiments thereof, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined by the appended claims. Accordingly, the true scope of the present invention should be determined only by the appended claims.

Claims (15)

A fuse dummy cell comprising a fuse and at least two conductive transistors connected in series between a power supply terminal and a ground to form a single dummy cell;
And a fuse cell lead active signal generator for generating and outputting a read active signal capable of reading the fuse data in the fuse cell group when the gate bias voltage applied to the fuse dummy cell is stabilized. Error prevention circuit. The fuse cell lead active signal generator according to claim 1,
A comparison signal generator for connecting a gate bias voltage and a resistor connected in series between the power supply terminal and the ground to couple the two fuse dummy cells in parallel;
A voltage level output from a first output node to which two conductivity-type transistors constituting the fuse dummy cell are connected in common and a voltage level output from a second output node which is a common connection node of two conductivity type transistors constituting the comparison signal generation unit And a logic operation circuit for comparing the voltage levels to generate and output the read active signal. The semiconductor memory device according to claim 2,
A first Schmitt trigger element for outputting a logic signal triggered according to a voltage level output from the first output node;
A second Schmitt trigger element for outputting a logic signal triggered according to a voltage level output from the second output node;
An inversion element for inverting the output signal of the first Schmitt trigger element;
And a logic multiplication element for multiplying an output signal of the second Schmitt trigger element and the inverted element by a logical product to output the read active signal. The method according to claim 2, wherein the voltage rising speed of the first output node is lower than the voltage rising speed of the third output node, which is a common connection node of the two conductivity type transistors constituting the fuse cell in the group of fuse cells, And the third output node, and the ground, and sets a resistance value of each of the conductive type transistors relatively to each other. 3. The method of claim 2, wherein the voltage drop rate of the second output node is between a power supply terminal in the group of fuse cells and ground, and a voltage logic of a fourth output node that is a common connection node of two conductive transistors connected in series with a fuse fuse Wherein the resistance value of each of the conductive type transistors connected between the second and fourth output nodes and the ground is relatively set to be lower than the level falling rate. The fuse according to claim 2, wherein a resistance value of a fuse constituting the fuse dummy cell is set to have a resistance value greater than a fuse resistance of the fuse cell, thereby reducing a current supplied to the first output node Prevention circuit. The fuse module according to claim 2, wherein a resistance value of the resistor constituting the comparison signal generator is set to have a smaller resistance value than a fuse fuse in the fuse cell group, thereby increasing a current supplied to the second output node Prevention circuit. [Claim 2] The fuse cell of claim 1, further comprising: a switching device for performing a switching operation according to application of the read active signal between one of the two conductive transistors constituting the fuse cell in the fuse cell group and the ground, Prevention circuit. 9. The fuse cell lead active signal generator of claim 8,
A comparison signal generator for connecting a gate bias voltage and a resistor connected in series between the power supply terminal and the ground to couple the two fuse dummy cells in parallel;
A voltage level output from a first output node which is a common connection node of two conductivity type transistors constituting the fuse dummy cell and a voltage level output from a second output node which is a common connection node of two conductivity type transistors constituting the comparison signal generation section And a logic operation circuit for comparing the voltage levels to generate and output the read active signal. 10. The semiconductor memory device according to claim 9,
A first Schmitt trigger element for comparing a voltage level output from the first output node with a first threshold voltage to output a triggered logic signal;
A second Schmitt trigger element for comparing a voltage level output from the second output node with a second threshold voltage to output a triggered logic signal;
An inversion element for inverting the output logic signal of the first Schmitt trigger element;
And a logic multiplication element for logically multiplying the output logic signal of the second Schmitt trigger element and the inverting element to output the read active signal. 10. The method of claim 9, wherein the voltage rising speed of the first output node is connected in series with the fuse so as to be later than the voltage level rising speed of the third output node which is a common connection node of the two transistors constituting the fuse cell, Wherein the resistance value of each of the conductive type transistors connected between the third output node and the ground is relatively set. 10. The method of claim 9, wherein the voltage drop rate of the second output node is between a power supply terminal in the group of fuse cells and ground, and a voltage logic of a fourth output node that is a common connection node of two conductive transistors connected in series with a fuse fuse Wherein the resistance value of each of the conductive type transistors connected between the second and fourth output nodes and the ground is relatively set to be lower than the level falling rate. The fuse data lead error prevention circuit according to claim 12, further comprising a switching element switching between one of the two conductive transistors connected in series with the fuse fuse and the ground according to application of the lead active signal. The fuse according to claim 9, wherein a resistance value of a fuse constituting the fuse dummy cell is set to have a resistance value larger than a fuse resistance of the fuse cell, thereby reducing a current supplied to the first output node Prevention circuit. [Claim 11] The method as claimed in claim 9, wherein the resistance value of the resistor constituting the comparison signal generating unit is set to have a smaller resistance value than the fuse fuse in the fuse cell group to increase the current supplied to the second output node Prevention circuit.

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