KR101750669B1 - 멀티-코어 이종 시스템 변환 색인 버퍼 일관성 - Google Patents

멀티-코어 이종 시스템 변환 색인 버퍼 일관성 Download PDF

Info

Publication number
KR101750669B1
KR101750669B1 KR1020167009817A KR20167009817A KR101750669B1 KR 101750669 B1 KR101750669 B1 KR 101750669B1 KR 1020167009817 A KR1020167009817 A KR 1020167009817A KR 20167009817 A KR20167009817 A KR 20167009817A KR 101750669 B1 KR101750669 B1 KR 101750669B1
Authority
KR
South Korea
Prior art keywords
value
processor
tlb
mask
physical address
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
KR1020167009817A
Other languages
English (en)
Korean (ko)
Other versions
KR20160065873A (ko
Inventor
지안 선
류 고 추아-에오안
Original Assignee
퀄컴 인코포레이티드
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 퀄컴 인코포레이티드 filed Critical 퀄컴 인코포레이티드
Publication of KR20160065873A publication Critical patent/KR20160065873A/ko
Application granted granted Critical
Publication of KR101750669B1 publication Critical patent/KR101750669B1/ko
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1009—Address translation using page tables, e.g. page table structures
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G06F12/1036—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] for multiple virtual address spaces, e.g. segmentation
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/65—Details of virtual memory and virtual address translation
    • G06F2212/656—Address space sharing
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/68—Details of translation look-aside buffer [TLB]
    • G06F2212/683—Invalidation

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
KR1020167009817A 2013-10-04 2014-09-19 멀티-코어 이종 시스템 변환 색인 버퍼 일관성 Active KR101750669B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US14/046,341 US9411745B2 (en) 2013-10-04 2013-10-04 Multi-core heterogeneous system translation lookaside buffer coherency
US14/046,341 2013-10-04
PCT/US2014/056664 WO2015050726A1 (en) 2013-10-04 2014-09-19 Multi-core heterogeneous system translation lookaside buffer coherency

Publications (2)

Publication Number Publication Date
KR20160065873A KR20160065873A (ko) 2016-06-09
KR101750669B1 true KR101750669B1 (ko) 2017-07-03

Family

ID=51703398

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020167009817A Active KR101750669B1 (ko) 2013-10-04 2014-09-19 멀티-코어 이종 시스템 변환 색인 버퍼 일관성

Country Status (6)

Country Link
US (1) US9411745B2 (enExample)
EP (1) EP3053045A1 (enExample)
JP (1) JP6066250B2 (enExample)
KR (1) KR101750669B1 (enExample)
CN (1) CN105637492B (enExample)
WO (1) WO2015050726A1 (enExample)

Families Citing this family (45)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9921967B2 (en) 2011-07-26 2018-03-20 Intel Corporation Multi-core shared page miss handler
US10534686B2 (en) 2014-01-30 2020-01-14 Micron Technology, Inc. Apparatuses and methods for address detection
US9785554B2 (en) 2014-05-30 2017-10-10 International Business Machines Corporation Synchronizing updates of page table status indicators in a multiprocessing environment
US9384133B2 (en) * 2014-05-30 2016-07-05 International Business Machines Corporation Synchronizing updates of page table status indicators and performing bulk operations
US20160041603A1 (en) * 2014-07-16 2016-02-11 New Concepts Development Corp. Power Management Apparatus, Systems, and Methods for Increased Power Loads
WO2016042519A2 (en) 2014-09-17 2016-03-24 Simless, Inc. Apparatuses, methods and systems for implementing a trusted subscription management platform
US11606685B2 (en) 2014-09-17 2023-03-14 Gigsky, Inc. Apparatuses, methods and systems for implementing a trusted subscription management platform
US10516990B2 (en) 2014-09-17 2019-12-24 Simless, Inc. Apparatuses, methods and systems for implementing a trusted subscription management platform
US11172352B2 (en) 2014-09-17 2021-11-09 Gigsky, Inc. Apparatuses, methods, and systems for configuring a trusted java card virtual machine using biometric information
US9697137B2 (en) * 2014-11-14 2017-07-04 Cavium, Inc. Filtering translation lookaside buffer invalidations
US9665505B2 (en) 2014-11-14 2017-05-30 Cavium, Inc. Managing buffered communication between sockets
US9684606B2 (en) * 2014-11-14 2017-06-20 Cavium, Inc. Translation lookaside buffer invalidation suppression
US9870328B2 (en) * 2014-11-14 2018-01-16 Cavium, Inc. Managing buffered communication between cores
US9916255B2 (en) * 2014-12-11 2018-03-13 Empire Technology Development Llc Data storage based on memory persistency
US9678872B2 (en) * 2015-01-16 2017-06-13 Oracle International Corporation Memory paging for processors using physical addresses
US12108488B2 (en) 2015-05-16 2024-10-01 Gigsky, Inc. Apparatuses, methods and systems for virtualizing a reprogrammable universal integrated circuit chip
WO2016185293A1 (en) * 2015-05-16 2016-11-24 Simless, Inc. Apparatuses, methods and systems for virtualizing a reprogrammable universal integrated circuit chip
US9898418B2 (en) * 2015-05-21 2018-02-20 Via Alliance Semiconductor Co., Ltd. Processor including single invalidate page instruction
US10007619B2 (en) 2015-05-29 2018-06-26 Qualcomm Incorporated Multi-threaded translation and transaction re-ordering for memory management units
KR102026877B1 (ko) * 2015-06-16 2019-09-30 한국전자통신연구원 메모리 관리 유닛 및 그 동작 방법
US20170149166A1 (en) * 2015-11-25 2017-05-25 GM Global Technology Operations LLC Electrical connector assembly
US9772874B2 (en) * 2016-01-29 2017-09-26 International Business Machines Corporation Prioritization of transactions based on execution by transactional core with super core indicator
US10386904B2 (en) * 2016-03-31 2019-08-20 Qualcomm Incorporated Hardware managed power collapse and clock wake-up for memory management units and distributed virtual memory networks
US9779028B1 (en) 2016-04-01 2017-10-03 Cavium, Inc. Managing translation invalidation
US9910799B2 (en) * 2016-04-04 2018-03-06 Qualcomm Incorporated Interconnect distributed virtual memory (DVM) message preemptive responding
US11843597B2 (en) * 2016-05-18 2023-12-12 Vercrio, Inc. Automated scalable identity-proofing and authentication process
EP3502906B1 (en) * 2016-06-08 2021-06-16 Google LLC Tlb shootdown for low overhead
US10540292B2 (en) 2016-06-08 2020-01-21 Google Llc TLB shootdowns for low overhead
US10482031B1 (en) * 2016-08-25 2019-11-19 Cadence Design Systems, Inc. Method and system for reconstructing virtual address from physical memory
US10353767B2 (en) * 2017-09-14 2019-07-16 Bae Systems Controls Inc. Use of multicore processor to mitigate common mode computing faults
US10725932B2 (en) 2017-11-29 2020-07-28 Qualcomm Incorporated Optimizing headless virtual machine memory management with global translation lookaside buffer shootdown
CN108874729B (zh) * 2018-04-19 2022-04-01 北京中科睿芯科技集团有限公司 芯片互联多应用有效映射方法、系统及内容寻址存储器
JP6810098B2 (ja) * 2018-05-24 2021-01-06 日本電信電話株式会社 統計データ処理装置、統計データ処理方法及びコンピュータプログラム
US10552339B2 (en) * 2018-06-12 2020-02-04 Advanced Micro Devices, Inc. Dynamically adapting mechanism for translation lookaside buffer shootdowns
CN110825665B (zh) * 2018-08-10 2021-11-05 昆仑芯(北京)科技有限公司 数据获取单元和应用于控制器的数据获取方法
US10846239B2 (en) * 2018-11-29 2020-11-24 Marvell Asia Pte, Ltd. Managing translation lookaside buffer entries based on associativity and page size
US10725928B1 (en) * 2019-01-09 2020-07-28 Apple Inc. Translation lookaside buffer invalidation by range
US10997019B1 (en) * 2019-10-31 2021-05-04 Alibaba Group Holding Limited System and method for facilitating high-capacity system memory adaptive to high-error-rate and low-endurance media
US11816037B2 (en) * 2019-12-12 2023-11-14 Advanced Micro Devices, Inc. Enhanced page information co-processor
US11422946B2 (en) 2020-08-31 2022-08-23 Apple Inc. Translation lookaside buffer striping for efficient invalidation operations
US11615033B2 (en) 2020-09-09 2023-03-28 Apple Inc. Reducing translation lookaside buffer searches for splintered pages
US11604740B2 (en) * 2020-12-01 2023-03-14 Capital One Services, Llc Obfuscating cryptographic material in memory
CN113612863B (zh) * 2021-07-12 2022-07-26 武汉理工大学 一种gpu中地址转换优化方法、系统、设备及存储介质
WO2024117572A1 (ko) * 2022-11-29 2024-06-06 한국전자통신연구원 대용량 온칩 메모리를 갖는 인공지능 프로세서를 위한 가상주소 기반의 캐시 코헤런시 지원 방법 및 이를 위한 장치
CN117421748A (zh) * 2023-10-24 2024-01-19 上海兆芯集成电路股份有限公司 计算机系统以及系统内存加解密方法

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100228944A1 (en) 2009-03-04 2010-09-09 Qualcomm Incorporated Apparatus and Method to Translate Virtual Addresses to Physical Addresses in a Base Plus Offset Addressing Mode
US20120137079A1 (en) 2010-11-26 2012-05-31 International Business Machines Corporation Cache coherency control method, system, and program

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0336648A (ja) * 1989-07-03 1991-02-18 Hitachi Ltd 電子計算機及びｔｌｂ装置とマイクロプロセッサチップ
JPH0383150A (ja) * 1989-08-28 1991-04-09 Fujitsu Ltd アドレス変換機構付キャッシュ装置の制御方式
JP2833062B2 (ja) * 1989-10-30 1998-12-09 株式会社日立製作所 キャッシュメモリ制御方法とこのキャッシュメモリ制御方法を用いたプロセッサおよび情報処理装置
US6493812B1 (en) 1999-12-17 2002-12-10 Hewlett-Packard Company Apparatus and method for virtual address aliasing and multiple page size support in a computer system having a prevalidated cache
US6684305B1 (en) 2001-04-24 2004-01-27 Advanced Micro Devices, Inc. Multiprocessor system implementing virtual memory using a shared memory, and a page replacement method for maintaining paged memory coherence
US7069389B2 (en) 2003-11-26 2006-06-27 Microsoft Corporation Lazy flushing of translation lookaside buffers
US20070005932A1 (en) 2005-06-29 2007-01-04 Intel Corporation Memory management in a multiprocessor system
US8156309B2 (en) 2007-10-18 2012-04-10 Cisco Technology, Inc. Translation look-aside buffer with variable page sizes
US8261047B2 (en) * 2008-03-17 2012-09-04 Freescale Semiconductor, Inc. Qualification of conditional debug instructions based on address
US8806101B2 (en) * 2008-12-30 2014-08-12 Intel Corporation Metaphysical address space for holding lossy metadata in hardware
US9471532B2 (en) * 2011-02-11 2016-10-18 Microsoft Technology Licensing, Llc Remote core operations in a multi-core computer
US9916257B2 (en) 2011-07-26 2018-03-13 Intel Corporation Method and apparatus for TLB shoot-down in a heterogeneous computing system supporting shared virtual memory

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100228944A1 (en) 2009-03-04 2010-09-09 Qualcomm Incorporated Apparatus and Method to Translate Virtual Addresses to Physical Addresses in a Base Plus Offset Addressing Mode
US20120137079A1 (en) 2010-11-26 2012-05-31 International Business Machines Corporation Cache coherency control method, system, and program

Also Published As

Publication number Publication date
CN105637492A (zh) 2016-06-01
EP3053045A1 (en) 2016-08-10
WO2015050726A1 (en) 2015-04-09
US9411745B2 (en) 2016-08-09
JP6066250B2 (ja) 2017-01-25
JP2016535883A (ja) 2016-11-17
CN105637492B (zh) 2018-04-20
US20150100753A1 (en) 2015-04-09
KR20160065873A (ko) 2016-06-09

Similar Documents

Publication Publication Date Title
KR101750669B1 (ko) 멀티-코어 이종 시스템 변환 색인 버퍼 일관성
US10437733B2 (en) Method and apparatus to allow secure guest access to extended page tables
TWI531912B (zh) 具有用於多上下文計算引擎的轉譯後備緩衝之處理器、用於致能多執行緒以存取於處理器中之資源之系統和方法
US9858140B2 (en) Memory corruption detection
CN102687128B (zh) 运算处理装置
TWI516937B (zh) 用於資料讀取／寫入延伸分頁表違例之處理的決策動作決定技術之方法、裝置及非暫態機器可讀媒體
US9652375B2 (en) Multiple chunk support for memory corruption detection architectures
US10031697B2 (en) Random-access disjoint concurrent sparse writes to heterogeneous buffers
KR101868389B1 (ko) 선택적인 트랜슬레이션 룩어사이드 버퍼 탐색 및 페이지 오류
JP5922317B2 (ja) 変換索引バッファ（ｔｌｂ）のための重複検査
TW201730770A (zh) 用於記憶體損毀偵測的硬體設備和方法
EP3736700B1 (en) Hybrid directory and snoopy-based coherency to reduce directory update overhead in two-level memory
KR20180008507A (ko) 캐시 태그 압축을 위한 방법 및 장치
US10671548B2 (en) Memory initialization detection system
TW201447584A (zh) 用於在執行硬體表搜尋〈ｈｗｔｗ〉時在某些條件下防止對暫存器的內容的未經授權式存取的方法和裝置
US8996833B2 (en) Multi latency configurable cache
TWI437488B (zh) 微處理器及適用於微處理器之操作方法
CN105103139B (zh) 用于改善跨越相干总线的信号量管理序列的性能的方法和设备
US9734069B2 (en) Multicast tree-based data distribution in distributed shared cache
CN103365799A (zh) 检测对掉电设备的访问
CN104793987A (zh) 一种数据处理方法及装置
CN105843360A (zh) 一种降低指令高速缓冲存储器功耗的装置及方法
JP2010204933A (ja) キャッシュシステムおよびこれを用いるコンピュータ

Legal Events

Date Code Title Description
PA0105 International application

Patent event date: 20160414

Patent event code: PA01051R01D

Comment text: International Patent Application

PG1501 Laying open of application
A201 Request for examination
A302 Request for accelerated examination
PA0201 Request for examination

Patent event code: PA02012R01D

Patent event date: 20160923

Comment text: Request for Examination of Application

PA0302 Request for accelerated examination

Patent event date: 20160923

Patent event code: PA03022R01D

Comment text: Request for Accelerated Examination

E902 Notification of reason for refusal
PE0902 Notice of grounds for rejection

Comment text: Notification of reason for refusal

Patent event date: 20161018

Patent event code: PE09021S01D

E701 Decision to grant or registration of patent right
PE0701 Decision of registration

Patent event code: PE07011S01D

Comment text: Decision to Grant Registration

Patent event date: 20170329

GRNT Written decision to grant
PR0701 Registration of establishment

Comment text: Registration of Establishment

Patent event date: 20170619

Patent event code: PR07011E01D

PR1002 Payment of registration fee

Payment date: 20170619

End annual number: 3

Start annual number: 1

PG1601 Publication of registration
PR1001 Payment of annual fee

Payment date: 20200324

Start annual number: 4

End annual number: 4

PR1001 Payment of annual fee

Payment date: 20210329

Start annual number: 5

End annual number: 5

PR1001 Payment of annual fee

Payment date: 20230327

Start annual number: 7

End annual number: 7

PR1001 Payment of annual fee

Payment date: 20240320

Start annual number: 8

End annual number: 8