KR101747969B1 - Liquid crystal display device - Google Patents

Abstract

The present invention provides a liquid crystal display comprising a substrate including a display portion having a plurality of pixels and a circuit portion disposed on one side of the display portion; A plurality of gate lines and data lines arranged to intersect with each other on the display unit to define the pixels; And a plurality of gate drive circuit lines disposed in the circuit portion and each connected to a plurality of gate lines and having a plurality of switching elements,
Some of the switching elements provided in the first gate driving circuit wiring of the plurality of gate driving circuit wirings may have a larger channel length than the switching elements provided in the gate driving circuit wiring of another line.

Description

[0001] Liquid crystal display device [0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a liquid crystal display device, and more particularly,

Recently, as the society has become a full-fledged information age, the display industry, which processes and displays a large amount of information, has rapidly developed. Liquid crystal display (LCD) has been developed to meet various demands of consumers such as thin shape, light weight, and low power consumption. Currently, it is a next generation display device that replaces a conventional cathode ray tube (CRT) Be in the spotlight.

The liquid crystal display device is constituted by integrating a driving circuit into a liquid crystal panel. In particular, a technique (GIP: Gate in Panel) that forms part or all of a gate driver circuit on a panel realizes reduction in size and manufacturing cost of the device .

Further, the liquid crystal display device excludes the line memory in the timing controller for forming the driving signal applied to the driving circuit portion to reduce the manufacturing cost.

However, due to the absence of the line memory in the timing controller, the first gate driving circuit wiring has to be set to have a smaller charging time than other gate driving circuit wiring, so that the low temperature driving of the panel and the characteristics of the thin film transistor may be degraded to some extent. At this time, the gate-on current of the first gate line connected to the first gate driving circuit line may be lowered, and a dim line defect in which the region corresponding to the first gate line in the liquid crystal display device is brighter than the other region may occur have.

Accordingly, the present invention has been made to solve the problems that may be caused in a liquid crystal display device, and more particularly, it is an object of the present invention to provide a liquid crystal display device in which a large area of a switching element is formed in a first gate driver line And an object of the present invention is to provide a liquid crystal display device capable of displaying an image.

A liquid crystal display device of a solution to the problem according to the present invention is provided. The liquid crystal display device includes a substrate including a display portion including a plurality of pixels and a circuit portion disposed on one side of the display portion; A plurality of gate lines and data lines arranged to intersect with each other on the display unit to define the pixels; And a plurality of gate drive circuit lines disposed in the circuit portion and each connected to a plurality of gate lines and having a plurality of switching elements,

Some of the switching elements provided in the first gate driving circuit wiring of the plurality of gate driving circuit wirings may have a larger channel length than the switching elements provided in the gate driving circuit wiring of another line.

The liquid crystal display device according to the embodiment of the present invention can prevent a lateral skyline failure by forming a larger area of the switching device in the first gate driver line than the gate driver lines of other lines.

Also, the liquid crystal display device according to the embodiment of the present invention can prevent the skid line defect and can improve the product reliability and the yield when the low temperature driving or the characteristics of the thin film transistor are below the reference value.

1 is a view schematically showing a liquid crystal display device according to an embodiment of the present invention.
2 is a plan view showing a part of the gate driver of FIG.
3 is an enlarged plan view of the first gate driving circuit wiring of FIG.
4 is a circuit diagram of the first gate drive circuit wiring of FIG.
5 is an enlarged view of a part of the switching element shown in enlarged view to explain another method of increasing the channel length.
6 is a graph showing the pulse state of the load set of the first gate drive circuit wiring.
7 is a graph showing the gate output pulse.

Embodiments of the present invention will be described in detail with reference to the drawings of a liquid crystal display device. The following embodiments are provided by way of example so that those skilled in the art can fully understand the spirit of the present invention.

Therefore, the present invention is not limited to the embodiments described below, but may be embodied in other forms. In the drawings, the size and thickness of an apparatus may be exaggerated for convenience. Like reference numerals designate like elements throughout the specification.

1 is a view schematically showing a liquid crystal display device according to an embodiment of the present invention.

Referring to FIG. 1, the liquid crystal display device may include a liquid crystal panel 100 having a built-in gate driver, and a data driver 130 connected to one side of the liquid crystal panel 100 through an FPC.

The liquid crystal panel 100 may include first and second substrates facing each other with a liquid crystal interposed therebetween. Here, the first substrate may include a display unit 110 including a plurality of pixels and a circuit unit disposed on one side of the display unit 110. [ Here, the display unit 110 may include a plurality of gate lines, a plurality of data lines, a thin film transistor provided in each pixel, and a pixel electrode connected to the thin film transistor of each pixel. On the other hand, the second substrate may include a color filter pattern arranged in correspondence with each pixel and a black matrix pattern arranged around each pixel. Here, the common electrode may be disposed on the inner surface of the first substrate or the second substrate.

The gate driver 120 may be disposed on the circuit portion of the first substrate 110. [ Here, the gate driver 120 performs on / off control of the thin film transistors provided in the display unit 110 so that analog image signals supplied from the data driver 130 are applied to the pixels connected to the thin film transistors do. Here, the gate driver may include a plurality of gate drive circuit wires each corresponding to a plurality of gate lines. Here, the plurality of gate drive circuit wirings may be connected to the gate lines, respectively.

Meanwhile, the data driver selects reference voltages of input data in response to external control signals, and supplies the selected reference voltage to the liquid crystal panel to control the rotation angle of the liquid crystal molecules to display an image.

Hereinafter, the gate driver will be described in detail with reference to FIGS. 2 to 4. FIG.

2 is a plan view showing a part of the gate driver of FIG.

3 is an enlarged plan view of the first gate driving circuit wiring of FIG.

4 is a circuit diagram of the first gate drive circuit wiring of FIG.

Referring to Figs. 2 to 4, the gate driver includes a plurality of gate driving circuit lines (1'st to n GIP lines) connected to the gate wirings of the liquid crystal panel, respectively. Here, n is a natural number.

A control signal input to each of the gate drive circuit lines 1'st to n GIP lines is supplied to the gate drive circuit via the power supply voltage VDD, the ground voltage VSS, the clock signal CLK_IN, the gate start signal VST, And a driving power supply (VDD_0VDD_E). At this time, the first and second driving power sources VDD_0 and VDD_E are alternately applied with the driving power so that the first switching device M1 and the second switching device M2 of the pulldown switching device can be alternately driven, The third switching device M3 and the fourth switching device M4 of the transistor can be alternately driven and the stress of the pull-down switching device can be relaxed. This is because the pull-down switching device is subject to great stress as compared with other switching devices and can easily be deteriorated.

Each of the plurality of gate drive circuit lines 1'st to n GIP lines may include a plurality of switching devices, for example, 17 switching devices M1 to M17. Here, the switching element may be composed of a thin film transistor. Here, the plurality of gate driving circuit wirings include fifth to tenth switching devices M5 to M10, forward switching device M11, and pull-up switching device M15, which are capable of generating a high- First to fourth switching devices M1 to M4 for holding scan pulses of a low voltage outputted to the gate wiring, first pull-down and second pull-down switching devices M16 and M17, Down unit and a converting unit for applying a low-voltage scan pulse at a high voltage.

In addition, the plurality of gate drive circuit wirings may include a node control unit (QC), a scan direction control unit (SDC), and an output unit (OP).

The node control unit (QC) controls the signal states of the set node (Q), the first reset node (QB_O), and the second reset node (QB_E). The node control unit QC includes first to tenth switching elements M1 to M10.

The first switching device M1 is connected between the first voltage line VDD_O and the second reset node QB_O and the second switching device M2 is connected between the first voltage line VDD_O and the first reset load QB_O. QB_O. The third switching device M3 and the fourth switching device M4 may be connected between the second voltage line VDD_E and the second reset node QB_E.

Here, the first to fourth switching devices M1 to M4 can turn on the switching elements of the pull-down section to output gate pulses of a low voltage.

The gate terminal of the fifth switching device M5 is connected to the second voltage line VDD_E and the source and drain terminals thereof are connected to the first reset load QB_O and the ground voltage VSS. The sixth switching device M6 is connected between the first voltage line VDD_O and the ground voltage VSS, and the turn-on and turn-off of the sixth switch M6 are controlled by the set load Q.

The seventh switching device M7 is connected between the first reset load QB_O and the ground voltage VSS, and the turn-on and turn-off of the seventh switching device M7 are controlled by the start signal Vst.

Further, the eighth switch M8 is connected between the second reset load QB_E and the ground voltage (VSS), and is operated by the forward of the second voltage line (VDD_E). The ninth and tenth switching devices M9 and M10 are connected between the drain terminal of the third switching device M3 and the fourth switching device M4 and the ground voltage VSS stage, Q and the start gate signal VST are controlled to be turned on and off.

Here, the fifth to tenth switching elements can serve to keep the switching elements of the pull-down section in an off state when the set load is turned ON.

The scan direction controller SDC includes a forward switching device M11 and a reverse switching device M12. Here, the forward switching device M11 is turned on / off by the start gate signal, and is connected between the power supply voltage VDD stage and the set load Q.

The reverse switching element M12 is supplied with a voltage at the terminal of the front stage power supply voltage VDD by operation and the reverse switching element M12 is connected to the terminal of the set load Q and the ground voltage VSS Respectively.

The scan direction controller SDC may further include thirteenth and fourteenth switching devices M13 and M14 connected between the drain terminal of the forward switching device M11 and the ground line VSS.

Here, the forward switching element M11, the thirteenth and fourteenth switching elements M13 and M14 can discharge the set load Q during the OFF period of the pull-down switching element.

The output part OP includes a pull-up switching element M15, a first pull-down and a second pull-down switching element M16 and N17.

The pull-up switching element M15 is driven by the set load Q and outputs a high voltage of the clock pulses CLK1 to CLK4 supplied from the clock line CLK_IN and outputs the high voltage of the first pulldown and the second pulldown switching element M16 And M17 are driven by the first reset node QB_O and the second reset node QB_E and output the low voltage of the ground line VSS.

As described above, the liquid crystal display device can be provided with the gate driver in the liquid crystal panel, thereby realizing the miniaturization of the affection display device and the manufacturing cost reduction effect. However, recently, in order to further reduce the manufacturing cost, the line memory is excluded from the timing controller for forming the driving signal applied to the driving circuit portion, so that the first gate driving circuit wiring (1'st GIP line) 'rd ~ n GIP line), the charging time can be set to be small. As a result, the gate-on current of the first gate line can be lowered, and a dim line defect in which the region corresponding to the first gate line in the liquid crystal display device is brighter than the other region can occur.

In order to solve this problem, some of the switching elements included in the first gate driving circuit wiring (1'st GIP line) among the plurality of gate driving circuit wirings (1'st to n GIP lines) Can be formed to have a larger channel length than a switching element provided in the circuit wiring (2'rd to n GIP line).

Here, the switching element for adjusting the channel length may be any one of switching elements constituting a pull-up portion for generating a high-voltage scan pulse output to the gate wiring. For example, the switching element for adjusting the channel length may be either the forward switching element M11 or the pull-up switching element M15. For example, the forward switching element M11 of the first gate driving circuit wiring (1'st GIP line) has a larger channel length than the forward switching elements of the gate driving circuit wiring (2'rd to nGIP line) of the other lines Lt; / RTI > Alternatively, the pull-up switching device M15 of the first gate driving circuit wiring (1'st GIP line) can have a larger channel length than the pull-up switching devices of the gate driving circuit wiring (2'rd to nGIP line) have.

As a result, the charging voltage of the set load Q is increased in the first gate driving circuit wiring (1'st GIP line) as compared with the gate driving circuit wiring lines 2'rd to n GIP lines of other lines, The charging time of the circuit wiring (1'st GIP line) can be increased. Accordingly, the output voltage of the gate can be raised in the first gate driving circuit wiring (1'st GIP line), so that the gate-on current of the first gate line can be raised. Thus, it is possible to prevent a dim line defect in the region of the liquid crystal display device corresponding to the first gate line from being brighter than other regions.

Here, the switching element for increasing the channel length may have a large area of 15 to 45% as compared with the switching elements provided in the gate drive circuit wiring lines 2'rd to n GIP lines of other lines. In this case, when the switching element for increasing the channel length has an area of less than 15%, it is not effective in solving the lateral line defect. On the other hand, if the switching element exceeds 45%, the switching element is not charged due to the cap increase, This is because the overhanging of the device can make the lateral dimple defect more brighter.

5 is an enlarged view of a part of the switching element shown in enlarged view to explain another method of increasing the channel length.

As shown in FIG. 5, the switching element may be formed by connecting a plurality of sub-switching elements CT. Here, the sub switching element CT may include a sub-source electrode having a branch portion on the gate electrode and a sub-drain electrode interposed between the branched sub-source electrode. At this time, the sub-source electrode may have a U-shape and the sub-drain electrode may have an I-shape.

At this time, the channel length of the switching device can be increased by adjusting the number of sub-switching devices CT.

6 and 7, the effect of the liquid crystal display according to the embodiment of the present invention will be described in detail. Here, in the comparative example, the sizes of the forward switching elements provided in the plurality of gate driving circuit wirings were 1900 m. Further, in the embodiment, the size of the forward switching element of the first gate driving circuit wiring is formed to 2250 mu m, and the size of the forward switching element of the other gate driving circuit wiring is formed to 1900 mu m.

6 is a graph showing the pulse state of the load set of the first gate drive circuit wiring.

As shown in Fig. 5, when the size of the forward switching element (M11 in Fig. 4) of the first gate driving circuit wiring among the switching elements of the plurality of gate driving circuit wirings is increased from the comparative example, It was ascertained that it rose.

7 is a graph showing the gate output pulse.

As shown in Fig. 7, in the comparative example, the output voltage of the first gate drive circuit wiring was 28.8V, and the output voltages of the second and third gate drive circuit wiring were 31.3V and 30.9V, respectively. On the other hand, in the embodiment, the output voltage of the first gate drive circuit wiring was 30.4 V, and the output voltages of the second and third gate drive circuit wiring were 31.7 V and 31.6 V, respectively. In other words, when the size of the forward switching element (M11 in FIG. 4) of the first gate driving circuit wiring of the switching elements of the plurality of gate driving circuit wiring is increased, the gate output voltage It was confirmed that the difference in gate output voltage between the first gate driving circuit wiring and the other gate driving circuit wiring was remarkably reduced.

100: liquid crystal panel
110:
120: gate driver
130: Data driver

Claims (6)

1. A liquid crystal display comprising: a substrate including a display portion having a plurality of pixels and a circuit portion disposed on one side of the display portion;
A plurality of gate lines and data lines arranged to intersect with each other on the display unit to define the pixels; And
A plurality of gate drive circuit lines disposed in the circuit portion and each connected to a plurality of gate lines and having a plurality of switching elements;
/ RTI >
Wherein some of the switching elements provided in the first gate driving circuit wiring of the plurality of gate driving circuit wirings have a larger channel length than the switching elements provided in the gate driving circuit wiring of another line.
The method according to claim 1,
And a switching element having a large channel length among the switching elements provided in the first gate driving circuit wiring generates a high signal output to the gate wiring.
3. The method of claim 2,
A switching element having a large channel length among the switching elements provided in the first gate driving circuit wiring is driven by a gate start signal and is driven by a forward switching element for providing a signal to a set load or a high- Up switching element for outputting a pull-up signal.
The method according to claim 1,
Wherein a channel length of some switching elements among the switching elements provided in the first gate driving circuit wiring is controlled by an area of the switching elements.
5. The method of claim 4,
The switching element having a large channel length among the switching elements provided in the first gate driving circuit wiring has a large area of 15 to 45% as compared with the switching element provided in the gate driving circuit wiring of the other line.
The method according to claim 1,
Wherein the switching element has a plurality of sub-switching elements connected to each other, and a channel length of the switching element is controlled by the number of the sub-switching elements.

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