KR101746426B1 - 4x4 INTRA PREDICTION HARDWARE LOGIC FOR HIGH EFFICIENCY VIDEO CODING - Google Patents

Abstract

For intra-prediction in units of 4x4 blocks of HEVC (High Efficiency Video Coding), an interpolated value to be used for intra-prediction in 4x4 block units using a reference pixel located in a neighboring block of a current 4x4 block to be predicted Interpolation logic for generating a reference pixel; And an SAD logic (SAD logic) for receiving an original pixel of the current 4x4 block and the interpolated reference pixel output from the interpolation logic and performing a sum of absolute difference (SAD) operation for each intra prediction mode 4x4 intra prediction logic is provided. Here, the SAD logic shares the SAD unit logic so that the same SAD unit logic is assigned to a plurality of angular modes having the same interpolation operation expression among the intra prediction modes.

Description

HEVC 4x4 Intra Prediction Hardware Device < RTI ID = 0.0 > [0002] <

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a High Efficiency Video Coding (HEVC) technology, and more particularly, to a 4x4 intra prediction hardware logic structure for performing HEVC intra prediction.

High-Efficiency Video Coding (HEVC), an image compression standard that is advantageous for high-quality image compression, has been announced compared to H.264, an image compression standard that has been used in the past. There are three main differences between H.264 and HEVC.

First, the existing H.264 macroblock (MB), which is the basic unit of compression, has been replaced by a coding tree unit (CTU). At this time, the size of the MB is 16x16, whereas the size of the CTU is 16x16, 32x32, 64x64. Then, one CTU can be divided into CUs (Coding Units), which are divided into Prediction Unit (PU) and Transform Unit (TU). Here, each CU may have a size of 64x64 to 8x8, a PU may have a size of 64x64 to 4x4, and a TU may have a size of 32x32 to 4x4. Therefore, HEVC supports various sizes of block and frequency conversion compared to H.264. Second, in H.264, HEVC uses 35 prediction directions while intra prediction has 9 prediction directions. Third, even in the case of inter-prediction (inter prediction), the maximum block size is limited to 16x16 in the case of the conventional H.264 inter prediction, while in the HEVC, various block sizes from 4x4 to 64x64 can be handled .

For the above reasons, the HEVC has improved the image compression ratio by about twice as compared with H.264, but the volume of compression increases by the number of kinds of partition sizes compared to H.264. This makes it vulnerable to real-time compression of high-quality images. Therefore, it is necessary to reduce the total operation time by modifying the order of block operation in HEVC hardware design. Particularly, prior art related to intraprediction hardware logic that can reduce the computational complexity of HEVC intra prediction is 'Kalali, E., Adibelli, Y., and Hamzaoglu, I .:' A high performance and low energy intra prediction hardware high efficiency video coding ". IEEE Int. Conf. on Field Programmable Logic and Applications, Oslo, Norway, August 2012, pp. 719-722.

The present invention provides a hardware logic structure in which the order of block operations is modified in order to reduce the total time required for intra prediction in a 4x4 block in intra prediction of HEVC (High Efficiency Video Coding).

According to an aspect of the present invention, there is provided an intra prediction logic for intra prediction in units of 4x4 blocks of HEVC (High Efficiency Video Coding)

Interpolation logic for generating an interpolated reference pixel to be used for intra prediction in 4x4 block units using a reference pixel located in a neighboring block of a current 4x4 block to be predicted; And an SAD logic (SAD logic) for receiving an original pixel of the current 4x4 block and the interpolated reference pixel output from the interpolation logic and performing a sum of absolute difference (SAD) operation for each intra prediction mode Including,

The SAD logic is provided with 4x4 intra prediction logic sharing the SAD unit logic so that the same SAD unit logic is allocated for a plurality of angular modes in which the interpolation equation is the same among the intra prediction modes.

In one embodiment, the SAD logic comprises a total of nine SAD unit logic,

Wherein each of the eight SAD unit logic of the nine SAD unit logic is responsible for SAD operation for a plurality of angular modes in which the interpolation equation is the same,

The remaining one SAD unit logic of the nine SAD unit logic is a mode in which the interpolation operation formula of the intra prediction mode is different from the Planar mode 0 mode, the DC mode 1 mode, the horizontal direction 10 mode, And can take charge of the SAD operation for the 26th mode in the vertical direction.

In one embodiment, the nine SAD-

Sequentially executing SAD operations according to a prediction mode of any one of a plurality of intra prediction modes to be handled by the unit logic, wherein the SAD operation is performed in parallel with each other in relation to the interpolation logic, The SAD calculation according to the prediction mode can be performed simultaneously.

In one embodiment, comparison and determination logic (which determines the intra prediction mode of the best mode through comparison based on SAD computation results for a total of 35 intra prediction modes performed through the SAD logic) ).

According to another aspect of the present invention, a 4x4 intra prediction logic of the above-described structure; Transform logic for performing a transform for 4x4 block-based encoding based on an intra prediction mode determined as an optimal mode by the 4x4 intra prediction logic; And an HEVC encoder comprising an intra-prediction mode-specific operation in the 4x4 intra prediction logic and control logic for controlling the conversion of the transforming logic.

In one embodiment, the control logic can control the order of SAD operations per intra prediction mode, according to Table 1 below.

[Table 1]

Here, SAD0 to SAD8 represent a total of nine SAD unit logic in the 4x4 intra prediction logic, SAD0 to SAD7 of which are SAD unit logic sharing an interpolation equation, T denotes a phase related to the calculation order, The numbers 0 to 34 in Table 1 represent a total of 35 intra prediction modes.

In one embodiment, the control logic controls the block operation order of intra prediction in 4x4 block units,

A 4x4 block that can be directly generated from the 4x4 blocks from among the 4x4 blocks before intra prediction is generated based on the reference pixel information that can be generated from the 4x4 blocks after block conversion according to intraprediction is completed, And control is performed such that a block operation for intraprediction is preferentially performed.

According to the embodiment of the present invention, it is possible to reduce the total time required for intra prediction in the 4x4 block by providing a hardware logic structure in which the operation order of blocks of 4x4 size is modified in intra prediction of HEVC (High Efficiency Video Coding) It is effective.

Figure 1 illustrates 4x4 intra prediction hardware for HEVC intra prediction according to an embodiment of the present invention.
FIG. 2 is a table for explaining an interpolation equation sharing method in each mode of intra prediction. FIG.
3 is a view for explaining an intra prediction mode of HEVC;
4 is a diagram for explaining reference pixels referred to in an interpolation process in intra prediction of HEVC;
FIG. 5 is a table for explaining an intra prediction mode in which a total of nine SADs (sum of absolute differences) provided in accordance with an embodiment of the present invention is handled. FIG.
6 is a diagram for explaining a block operation procedure of 4x4 intra prediction;
FIG. 7 is a timing diagram illustrating a block operation sequence of FIG. 6 assuming a block of 32x32 size; FIG.

BRIEF DESCRIPTION OF THE DRAWINGS The present invention is capable of various modifications and various embodiments, and specific embodiments are illustrated in the drawings and described in detail in the detailed description. It is to be understood, however, that the invention is not to be limited to the specific embodiments, but includes all modifications, equivalents, and alternatives falling within the spirit and scope of the invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail with reference to the accompanying drawings. In addition, numerals (e.g., first, second, etc.) used in the description of the present invention are merely an identifier for distinguishing one component from another.

Also, throughout the specification, when an element is referred to as being "connected" or "connected" with another element, the element may be directly connected or directly connected to the other element, It should be understood that, unless an opposite description is present, it may be connected or connected via another element in the middle. Also, throughout the specification, when an element is referred to as "including" an element, it is understood that the element may include other elements as well, without departing from the other elements unless specifically stated otherwise.

FIG. 1 illustrates 4x4 intra prediction hardware for HEVC intra prediction according to an embodiment of the present invention. Referring to FIG. 3 is a diagram for explaining an intra prediction mode of an HEVC. FIG. 4 is a table for explaining an interpolation operation sharing method in each mode of intraprediction, FIG. 5 is a table for explaining an intra prediction mode in which a total of nine SADs (Sum of Absolute Difference) are provided according to an embodiment of the present invention.

Referring to FIG. 1, a 4x4 intra prediction logic 100 according to an embodiment of the present invention for HEVC intra prediction includes interpolation logic 110, sum of absolute difference logic 130, Comparison and determination logic 150, and transform logic 170. In one embodiment, This 4x4 intra prediction logic 100 may be configured in an HEVC encoder.

The interpolation logic 110 generates an interpolated reference pixel to be used for intra prediction in 4x4 block units using a reference pixel located in a neighboring block of a current 4x4 block to be predicted.

The SAD logic 130 receives the original pixel of the current 4x4 block and the interpolated reference pixel output from the interpolation logic 110 and performs a sum of absolute difference (SAD) calculation for each intra prediction mode . At this time, the SAD logic 130 may include the SAD unit logic of SAD0 to SAD8 as shown in FIG.

The comparison and decision logic 150 compares the SAD operation result values for a total of 35 intra prediction modes performed through each SAD unit logic (see SAD0 through SAD8 in Figures 1 and 5) of the SAD logic 130 The intra prediction mode of the best mode is determined.

The transform logic 170 then performs transformations for 4x4 block-based encoding based on the intra-prediction mode determined to be the best mode. The transform logic 170 may include discrete sine transform logic, quantization logic, inverse quantization logic, inverse DST logic, and the like, which perform frequency domain transforms on 4x4 blocks. . ≪ / RTI >

Hereinafter, embodiments of the present invention will be described in detail with reference to FIG. 2 through FIG. 5, with reference to technical features of a hardware logic according to an embodiment of the present invention according to the components of FIG.

The intra prediction mode in the HEVC standard includes a total of 35 prediction modes as shown in FIG. In this case, the 0th mode is a Planar mode, the 1st mode is a DC mode, the 10th mode is a horizontal direction prediction mode, and the 26th mode is a vertical direction prediction mode. A total of 31 prediction modes except for the above four prediction modes are prediction modes having an angular direction as shown in FIG. 3 (i.e., angular mode). At this time, the angular mode of the HEVC standard shares some interpolation equations in some modes as shown in the table of FIG.

Referring to FIG. 2, the same interpolation equation is applied to modes 2, 18, and 34, and the same interpolation equation is applied to modes 3, 17, 19, and 33 . 2, there are eight groups of prediction modes that can share the interpolation equation.

That is, referring to the table of FIG. 2, the interpolation equation has a form of ax + by. In this case, the modes having the same values of the interpolation coefficients a and b can be grouped together. Here, the x and y values represent horizontal and vertical reference pixels to be used for the interpolation operation with respect to the current 4x4 block. The reference pixel (x, y) includes candidate pixels of the current block in the current 4x4 block (pixel in the left block shifted to the left from the current block, upper block shifted to the upper side of the current block, (See FIG. 3) of each prediction mode among the pixels in the block (see FIG. 4). At this time, the selection of the reference pixel can be made in such a way that the necessary reference pixels are extracted from the memory (not shown) by the control logic (not shown) in the HEVC encoder. Therefore, the value of the reference pixel (x, y) may be varied for each mode and for each current block to be predicted. However, in spite of the fluctuation of the value of the reference pixel, the prediction modes common to the interpolation operation formula itself can be processed through the hardware designed logic with the same structure.

Therefore, in the embodiment of the present invention, the prediction modes in which the interpolation equation can be shared as described above are grouped and allocated to one SAD unit logic. Referring to FIG. 5, SAD0 is responsible for SAD operation for modes 2, 8 and 34, SAD1 is for SAD operation for modes 3, 17, 19 and 33, and SAD0 A total of 31 angular modes are assigned to a total of 8 SAD unit logic from the SAD 7 to the SAD 7.

Referring to FIG. 5, in the case of the 0-th mode, the 1-th mode, the 10-th mode, and the 26-th mode in which the interpolation equation can not be shared, a separate SAD unit logic (see SAD 8 in FIG. 1 and FIG. 5 ) To process the SAD operation related thereto.

As described above, in the embodiment of the present invention, the SAD logic 130 includes a total of nine SAD unit logic, and the nine SAD unit logic SAD0 to SAD8 is a unit of the plurality of intra prediction modes And sequentially performs SAD operations according to one prediction mode. In addition, the nine SAD unit logic SAD0 to SAD8 are connected in parallel with each other in relation to the interpolation logic 110, so that SAD operations according to any one prediction mode in the unit logic can be performed simultaneously . This will be described with reference to FIG.

Referring to FIG. 5, there is shown a sequence of SAD operations for each intra prediction mode. In FIG. 5, T represents a phase related to the calculation order, and the numbers 0 to 34 in the table of FIG. 5 represent a total of 35 intra prediction modes. That is, in performing a SAD operation according to a total of 35 intra-prediction modes with respect to one 4x4 block, in the first phase, a total of 9 SAD0 to SAD8 operations for nine prediction modes in the 2 < SAD unit logic at the same time. In this way, up to the fourth phase, a total of nine SAD unit logic performs the SAD operation on the specific prediction mode assigned to each of them. At this time, the assignment of the order of the SAD operation for each intra prediction mode for each phase and for each SAD unit logic can be performed by the control logic (not shown) of the HEVC encoder.

According to the 4x4 intra prediction logic according to the embodiment of the present invention, since SAD operation can be performed for all 35 prediction modes in total with only 9 SAD unit logic, existing logic (case having separate SAD unit logic for each prediction mode ), There is an advantage that the required hardware size can be reduced to about 1/4.

In addition, according to the embodiment of the present invention, the order of block operation in the intra prediction process of 4x4 block units can be the order as shown in FIG. 6 and FIG. The control of the intra-prediction block operation order can be performed by the control logic (not shown) in the HEVC encoder. This will be described in more detail with reference to FIG. 6 and FIG. 6 is a diagram for explaining a block operation procedure of 4x4 intra prediction, and FIG. 7 is a timing diagram illustrating a block operation procedure of FIG. 6 assuming a block of 32x32 size.

In general, in the intra prediction of 4x4 block units, the result after the conversion of the previous block is necessary to predict the current block. Therefore, when the block operation is performed in the order described in the HEVC standard, the current block may not be predicted until the conversion of the previous block ends. For example, when a block operation is performed according to the order presented in the HEVC standard (refer to the block operation procedure of FIG. 6A), the prediction of the block 5 is performed until the prediction and the conversion of the block 4 are completed I can not. Therefore, intra prediction logic is wasted without any action during that time.

On the other hand, in the embodiment of the present invention, as shown in FIG. 6B, by performing the block operation of the method of performing the conversion on the block 4 after the prediction of the block 4 and the prediction of the block 8 , The prediction logic can also operate while the conversion logic is operating, minimizing logic waste. As described above, the prediction of the block 8 immediately after the prediction of the block 4 is possible because the calculation of the blocks 2 and 3 is completed in accordance with the previous block operation procedure, and the reference pixel value This is a situation that can be secured.

As described above, in the embodiment of the present invention, it is possible to directly generate reference pixels from the 4x4 blocks in which the block operation is completed according to the previous order among the remaining 4x4 blocks before the intraprediction, irrespective of the general block operation procedure defined in the HEVC standard A 4x4 block is determined as a current prediction block, and a block operation for intraprediction is preferentially performed so that the total operation time for intraprediction can be reduced.

7 shows a timing diagram of a block operation procedure according to an embodiment of the present invention with respect to a CTU of 32x32 block size. However, the block operation order control method according to the embodiment of the present invention described above is different from the CTU 16x16, 64x64) can also be applied to the same principle. Therefore, the HEVC encoder employing the logic and block operation procedure according to the embodiment of the present invention is advantageous in that the computation time can be greatly reduced. Therefore, in the surveillance and security field requiring real-time encoding, that is, And can be applied to the same application fields and products.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the following claims And changes may be made without departing from the spirit and scope of the invention.

Claims (7)

An HEVC encoder including intra prediction logic for intra prediction in units of 4x4 blocks of High Efficiency Video Coding (HEVC)
Interpolation logic for generating an interpolated reference pixel to be used for intra prediction in 4x4 block units using a reference pixel located in a neighboring block of a current 4x4 block to be predicted; And an SAD logic (SAD logic) for receiving an original pixel of the current 4x4 block and the interpolated reference pixel output from the interpolation logic and performing a sum of absolute difference (SAD) operation for each intra prediction mode Including,
Wherein the SAD logic shares the SAD unit logic so that the same SAD unit logic is allocated for a plurality of angular modes having the same interpolation equation of the intra prediction mode;
Transform logic for performing a transform for 4x4 block-based encoding based on an intra prediction mode determined as an optimal mode by the 4x4 intra prediction logic; And
An intra prediction mode operation in the 4x4 intra prediction logic, and control logic for controlling the conversion of the conversion logic,
The control logic comprises:
The block operation order of intra prediction in 4x4 block units is controlled,
A 4x4 block that can be directly generated from the 4x4 blocks from the block transformed 4x4 blocks before intra prediction is generated based on the reference pixel information that can be generated from the 4x4 blocks after block conversion according to intraprediction, And controls the block operation for intraprediction to be performed preferentially,
And performs the intra-prediction for any 4X4 block among the 4X4 blocks before the intra-prediction, and at the same time corrects the operation order of the block so that the 4X4 transform is performed in parallel on the other 4X4 block in which intra prediction is completed.
The method according to claim 1,
The SAD logic includes a total of nine SAD unit logic,
Wherein each of the eight SAD unit logic of the nine SAD unit logic is responsible for SAD operation for a plurality of angular modes in which the interpolation equation is the same,
The remaining one SAD unit logic of the nine SAD unit logic is a mode in which the interpolation operation formula of the intra prediction mode is different from the Planar mode 0 mode, the DC mode 1 mode, the horizontal direction 10 mode, HEVC encoder responsible for SAD operation for mode 26 in the vertical direction.
3. The method of claim 2,
The nine SAD-
Sequentially executing SAD operations according to a prediction mode of any one of a plurality of intra prediction modes to be handled by the unit logic, wherein the SAD operation is performed in parallel with each other in relation to the interpolation logic, An HEVC encoder that simultaneously performs SAD operations according to a prediction mode.
The method according to claim 1,
And comparison and determination logic for determining an intra prediction mode of a best mode through a comparison based on a result of SAD operation on a total of 35 intra prediction modes performed through the SAD logic. HEVC encoder.
delete The method according to claim 1,
The control logic comprises:
According to Table 1 below, controls the order of SAD operations per intra prediction mode.
[Table 1]

Here, SAD0 to SAD8 represent a total of nine SAD unit logic in the 4x4 intra prediction logic, SAD0 to SAD7 of which are SAD unit logic sharing an interpolation equation, T denotes a phase related to the calculation order, The numbers 0 to 34 in Table 1 indicate a total of 35 intra prediction modes.
delete

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