KR101742231B1 - High Power Factor And High Efficiency Interleaved Dual-Buck Converter And Method Therefor - Google Patents

High Power Factor And High Efficiency Interleaved Dual-Buck Converter And Method Therefor Download PDF

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KR101742231B1
KR101742231B1 KR1020150168956A KR20150168956A KR101742231B1 KR 101742231 B1 KR101742231 B1 KR 101742231B1 KR 1020150168956 A KR1020150168956 A KR 1020150168956A KR 20150168956 A KR20150168956 A KR 20150168956A KR 101742231 B1 KR101742231 B1 KR 101742231B1
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South Korea
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voltage
switch
inductor
diode
capacitor
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KR1020150168956A
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Korean (ko)
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KR20170064100A (en
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이영일
한정호
김주만
신용재
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서울과학기술대학교 산학협력단
주식회사 재신파워텍
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H02M2003/1586—

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Rectifiers (AREA)
  • Dc-Dc Converters (AREA)

Abstract

Disclosed is a high power factor high efficiency interleaved dual-buck converter and control method that facilitates capacity increase. The interleaved dual-buck converter according to the present embodiment includes PFC control, rectification, boost operation, a first capacitor C 1 , And eliminating the voltage controllable section of the second capacitor (C 2 ) and distributing the inductor current. In addition, by distributing the dual-buck half-bridge circuit and applying the interleaved form, the current capacity of the inductor is divided, thereby improving efficiency and capacity of the entire bridge circuit.

Figure R1020150168956

Description

TECHNICAL FIELD [0001] The present invention relates to a high power factor interleaved dual-buck converter and a control method thereof,

The present embodiment relates to a high power factor high efficiency interleaved dual-buck converter and a control method which are easy to increase the capacity.

The contents described below merely provide background information related to the present embodiment and do not constitute the prior art.

Rectifier is one of the power conversion devices that convert AC to DC, and there are various applications such as UPS, battery charger and so on. The function of the rectifier is largely divided into a rectifying action for converting AC to DC and a boosting action for increasing the magnitude of the rectified DC voltage. Recently, PFC (Power Factor Correction) control is required to increase the efficiency. In order to perform this role, the rectifier basically uses a circuit in which a bridge diode and a boost converter are combined. However, such a rectifier is difficult to increase the capacity of 1 KW or more due to the loss of the bridge diode, and the size of the inductor of the converter increases as the capacity increases. The problem of increasing inductor size can be reduced by designing the boost converter in an interleaved fashion. However, the interleaved rectifier can not avoid the loss problem because the bridge diode still exists at the input.

In order to solve the problem of loss of the bridge diode, a symmetrical bridgeless booster rectifier (SBBR) and an asymmetrical bridgeless boost rectifier (ABBR) without a bridge diode are being studied . SBBR and ABBR can be rectified, boosted, and PFC controlled without a bridge diode. In addition, the SBBR and ABBR have no Arm-Short risk of the Leg, so the loss due to Switching Dead Time can be reduced. However, since SBBR and ABBR can only function as a rectifier, additional inverter circuits must be added in order to be used in applications such as battery charging and discharging, resulting in increase in cost and efficiency of the entire system. For this reason, a form of a half-bridge converter or a full-bridge converter capable of acting as a rectifier and an inverter with only one circuit is being studied. Half-bridge converters or full-bridge converters have a risk of female shorts due to their operating characteristics. To prevent this, the switching dead time must be set.

The dual-buck half-bridge converter has the advantages of each circuit among the various power conversion circuits.

1 is a circuit diagram of a conventional dual-buck half-bridge converter. The dual-buck half-bridge converter comprises two switching elements S 1 and S 2 , diodes D 1 and D 2 , inductors L 1 and L 2 , capacitors C 1 and C 2 , 120). Power is transferred from AC voltage (V ac ) of AC part to DC part of load, and in the steady state, DC part voltage is larger than AC part peak value.

The dual-buck half-bridge converter 100 may serve as a rectifier and an inverter. Legs 112 and 114 are composed of diodes D 1 and D 2 and switching elements S 1 and S 2 , respectively. The control unit 120 generates a signal for controlling the diode and the switching element to be inverted from each other. Thus, the dual-buck half-bridge converter 100 is free of arm-short risk. In addition, the dual-buck half-bridge converter 100 is capable of rectifying, boosting, and power factor correction (PFC) control without a bridge diode when operating as a rectifier. Since the dual-buck half-bridge converter 100 includes the inductors L 1 and L 2 , the capacity of the inductors L 1 and L 2 increases as the capacity increases. The increase of the inductor capacity may cause problems such as increase in volume and cost of the dual-buck half-bridge converter 100, reduction of efficiency, and the like. Also, during the half period of the AC voltage (V ac ) of the AC part (AC-side), the first capacitor (C 1 ) of the DC part (DC- And the voltage of the second capacitor (C 2 ) are always discharged.

The present embodiment has an object to provide an inductor with a dual-buck half-bridge circuit as a rectifier, thereby distributing the current capacity of the inductor to increase the efficiency and increase the capacity. Also, during the half period of the AC negative voltage, the first capacitor (C 1 ) And the second capacitor (C 2 ) voltage is always being discharged.

According to the example an aspect of this embodiment, for generating an alternating voltage (V ac) is applied is derived from the received primary winding, the primary winding first induced voltage (v ac1) and a second induced voltage (v ac2) for each two A transformer including a primary winding and a tertiary winding; An inductor group which receives a current from the secondary winding and the tertiary winding and generates a link voltage according to the current; A leg unit for receiving the link voltage and converting the link voltage into a DC voltage; A capacitor group which receives the DC voltage from the leg portion and performs charge / discharge; And a control unit for generating a control signal for controlling the switching of the leg unit for charging / discharging the capacitor group. The interleaved dual-buck converter of claim 1,

According to another aspect of the present embodiment, is derived from a primary winding receiving applying an alternating voltage (V ac) in the transformer a first induced voltage (v ac1) and a second induced voltage (v ac2 to the third winding to the secondary winding Respectively; Receiving a current from the secondary winding and the tertiary winding in an inductor group and generating a link voltage according to the current; Receiving the link voltage from the leg portion and converting the link voltage into a DC voltage; Charging and discharging the DC voltage by receiving the DC voltage from the capacitor group; And controlling switching of the leg portion for charging / discharging the capacitor group. The method of controlling an interleaved dual-buck converter according to claim 1,

As described above, the interleaved dual-buck converter according to the present embodiment includes PFC control, rectification and boosting operation, a first capacitor C 1 , And eliminating the voltage controllable section of the second capacitor (C 2 ) and distributing the inductor current. In addition, by distributing the dual-buck half-bridge circuit and applying the interleaved form, the current capacity of the inductor is divided, thereby improving efficiency and capacity of the entire bridge circuit.

1 is a circuit diagram of a conventional dual-buck half-bridge converter.
Figure 2 illustrates operational characteristics of a dual-buck half-bridge converter in accordance with an embodiment of the present invention.
3 is a block diagram of a controller of a dual-buck half-bridge converter in accordance with an embodiment of the present invention.
4 is a circuit diagram of an interleaved dual-buck converter in accordance with an embodiment of the present invention.
5 illustrates operational characteristics of an interleaved dual-buck converter in accordance with an embodiment of the present invention.
6 is a block diagram of a controller of an interleaved dual-buck converter in accordance with an embodiment of the present invention.
Figure 7 illustrates simulation parameters in accordance with an embodiment of the present invention.
8 shows the current relationship between the AC negative voltage and current and L 1 and L 2 of a dual-buck half-bridge converter according to an embodiment of the present invention.
Figure 9 illustrates the AC negative and DC negative voltage relationships of a dual-buck half-bridge converter in accordance with an embodiment of the present invention.
10 illustrates the current relationship between the AC negative voltage and current and L 1 and L 2 of an interleaved dual-buck converter according to an embodiment of the present invention.
11 shows the current relationship of the AC negative voltage, current, v ac2 voltage, current, L 3 and L 4 of the interleaved dual-buck converter according to an embodiment of the present invention.
12 illustrates the AC negative voltage and DC negative voltage relationships of an interleaved dual-buck converter according to an embodiment of the present invention.

Hereinafter, the present embodiment will be described in detail with reference to the accompanying drawings.

Figure 2 illustrates operational characteristics of a dual-buck half-bridge converter in accordance with an embodiment of the present invention. The control unit 120 of FIG. 1 divides one cycle of the AC voltage (V ac ) of the AC unit by a half period, so that S 1 and D 1 operate when the voltage value has a positive value, and S 2 and D 2 do not operate do. On the contrary, when the voltage value has a negative value, the controller 120 causes S 2 and D 2 to operate, and S 1 and D 1 do not operate. The controller 120 also generates a signal for controlling the diode D 1 or D 2 of each leg and the corresponding switching element S 1 or S 2 to be inverted from each other. Here, inversion refers to control such that the diode and the switch are not turned on at the same time, that is, the switching element is turned off when the diode is turned on and the switching element is turned on when the diode is turned off.

2 (a) shows a state in which the AC negative voltage is positive and S 1 is on. In this case, D 1 is turned off and i ac flows in a direction output from the AC negative voltage. On the other hand, C 1 And C 2 are both discharged. When D 1 is in an ON state, it can be expressed as shown in FIG. 2 (b). That is, S 1 is in the off state, and i ac decreases in the direction output from the AC negative voltage. On the other hand, C 1 is in a charged state and C 2 is in a discharged state. 2 (a) and 2 (b), when the AC negative voltage has a positive value, the current flows only to L 1 . C 1 is repeatedly charged and discharged by the switching operation, and C 2 is always discharged.

2 (c) shows a state in which the AC negative voltage is negative and S 2 is on. In this case, D2 is turned off and i ac flows in the direction of input to the AC negative voltage. C 1 and C 2 are all discharged. 2 (d) shows a state in which D 2 is on. At this time, S 2 is turned off, i ac flows decreases in the direction in which the input AC voltage part. C 2 changes to a charged state, and C 1 maintains a discharged state. As shown in (c) and (d) of FIG. 2, when the AC negative voltage has a negative value, the current flows only to L 2 . C 2 is repeatedly charged and discharged by the switching operation, and C 1 is always discharged.

As described above, the dual-buck half-bridge converter 100 can control the voltage of one of the capacitors C 1 or C 2 during the AC negative voltage half cycle, and the voltage of the remaining capacitors is always discharging have. For this reason, the dual-buck half-bridge converter 100 lowers the reliability of the overall DC negative voltage control. Since the dual-buck half-bridge converter 100 operates only one leg for half a period, the input current and the inductor current have the same magnitude during that period. Thus, it can be seen that if the dual-buck half-bridge converter 100 needs to increase the capacity of the circuit, the capacity of each device included therein must also increase.

3 is a block diagram of a controller 120 of a dual-buck half-bridge converter in accordance with an embodiment of the present invention. 3, the controller 120 includes a PLL (Phase Locked Loop) 310, a first subtractor 320, a second subtractor 320, a voltage controller 330, a multiplier 340, a current controller 350, a switch 360, a second switch 360, an inverter 370, a first comparator 380, and a second comparator 380.

The PLL 310 causes the phases of the AC AC negative voltage V ac and the phases of the AC internal power source V ac | sin? T to be supplied to the dual-buck half-bridge converter 100 to coincide with each other. That is, the PLL 310 compensates for the phase difference from the AC negative voltage V ac due to the delay occurring in the dual-buck half-bridge converter 100, so that the PLL 310 can perform accurate phase control. Claim is connected to the first switch 360 and second switch 360, when connected to the terminal (V dcT) # 1 when the value of V ac is positive, negative terminal 2 (V dcB).

The first subtractor 320 receives the reference direct-current voltage V dc * as a positive terminal, and the value of the reference direct-current voltage is set to a value corresponding to half of V dc . The negative terminal of the first subtractor 320 is connected to V dcT , which is the first terminal of the first switch 360 when the AC negative voltage is a positive value. When the AC negative voltage is negative, And is connected to the second terminal V dcB of the second switch 360. The first subtractor 320 is connected to a value V dc * and the first switch (360), (V dcT or V dcB ), and transmits the difference to the voltage controller 330.

The voltage controller 330 and the current controller 350 perform one of control of P control (Proportional Control), PI control (Proportional Integral Control), PD control (Proportional Differential Control) and PID control (Proportional Integral Differential Control) can do.

The voltage controller 330 performs PI control (Proportional-Integral Control) and performs a control operation proportional to the magnitude of the error value of the first subtractor 320 and a control operation proportional to the integration of the error value of the first subtractor 320 To reduce the steady-state error. The control proportional to the error value of the first subtractor 320 is Kp and the control proportional to the integral of the error value of the first subtracter 320 is Ki. The output of the voltage controller 330 becomes the peak value I pk * of the current flowing in the inductor.

The multiplier 340 receives the output I pk * of the voltage controller 330 and the AC internal power source sin ωt, multiplies them, and outputs I ac * . I ac * And is transmitted to the second subtracter 320 as a reference AC current of the AC part.

A second subtracter 320 receives the ac i * with the positive terminal, receives the i ac to the negative terminal. i ac * is the reference AC current, and i ac is the current output from the AC negative voltage. The second subtractor 320 calculates the difference between i ac * and i ac and transmits it to the voltage controller 330.

The current controller 350 performs PI control in the same manner as the voltage controller 330 and performs a control operation proportional to the magnitude of the error value of the second subtractor 320 and a control operation proportional to the integral of the error value of the second subtractor 320 (Steady-state) error by performing the operation. The output value of the current controller 350 is a rational number between -1 and 1 and a signal for controlling the duty is transmitted to the first comparator 380 or the second comparator 380 through the second switch 360 .

The current controller 350 performs control to reduce the difference between i ac * and i ac . Where i ac * is a signal generated from sin ω t synchronized with V ac by PLL 310. The current controller 350 synchronizes V ac and i ac * by controlling the difference between i ac * and i ac . Accordingly, the current controller 350 performs the PFC operation to match the phases of the AC negative voltage V ac and the AC attraction current i ac .

When the AC negative voltage is a positive value, the first comparator 380 receives an output voltage between -1 and 1 of the current controller 350, which is the first terminal of the second switch 360, The voltage of the triangular wave having a magnitude between -1 and 1 is inputted to the terminal of The first comparator 380 compares the output voltage value and output voltage value of the triangular waveform in the negative terminals of the current controller 350 of the positive terminal, and supplies an output voltage to S 1 in Fig.

When the AC negative voltage is negative, the second comparator 380 is connected to the positive terminal of the current controller 350, which is the second terminal of the second switch 360, And receives the output of the inverting inverter 370. The second comparator 380 receives the voltage of the triangular wave having a magnitude between -1 and 1 at the negative terminal. The second comparator 380 compares the output voltage value of the inverter 370 of the positive terminal with the output voltage value of the triangular wave of the negative terminal, and supplies the output voltage to S 2 of FIG. 1.

The control unit 120 of FIG. 1 divides one cycle of the AC sub voltage by a half period, so that S 1 and D 1 operate when the voltage has a positive value, and S 2 and D 2 do not operate. Conversely, when the voltage value has a negative value, S 2 and D 2 are operated, and S 1 and D 1 are not operated. In addition, the control unit 120 of FIG. 1 does not cause arm-short because the switching elements and the diodes of the respective legs operate to invert each other. In addition, the controller 120 of FIG. 1 is capable of rectifying, boosting, and PFC control without a bridge diode when operating as a rectifier.

4 is a circuit diagram of an interleaved dual-buck converter in accordance with an embodiment of the present invention. The interleaved dual-buck converter 400 includes four switching elements S 1 , S 2 , S 3 and S 4 , four diodes D 1 , D 2 , D 3 and D 4 , four inductors L 1, L 2, and a L 3, L 4), 2 of the capacitor (C 1, C 2), the transformer 420 and the controller 450. In the interleaved dual-buck converter 400, power is transferred from the AC part to the DC part, and in the steady state, the DC negative voltage is larger than the peak voltage values of v ac1 and v ac2 . The transformer 420 includes a primary winding 426 on the primary side, a secondary winding 426 on the secondary side, and a tertiary winding 428 and a core 424. v ac1 Phase is induced in the secondary winding 426 and has the same phase as the primary side, and v ac2 Phase is induced in the tertiary winding 428 and has an inverted phase with the primary side. v ac1 Phase is connected to L 1, L 2 S 1, D 1, is connected to the DC section via the S 2, D 2 and, v associated with ac2 phase L 3, L 4 S 3, D 3, S 4, D 4 To the DC portion. The intermediate point between C 1 and C 2 is connected to the (-) terminal on the secondary side of the transformer.

The inductor groups L 1 , L 2 , L 3 , and L 4 430 receive a current from the secondary winding 426 and the tertiary winding 428 and generate a link voltage according to the change in current. One end of the secondary winding is connected to the first inductor group including the first inductors L 1 and L 2 and one end of the third winding is connected to the second inductor group including the second inductors L 3 and L 4 Lt; / RTI > The first leg 442 is a first converter that receives an output from L 1 and generates a first converting voltage. The second leg 444 is a second converter that receives an output from L 2 and generates a second converting voltage. The third leg 446 is a third converter that receives an output from L 3 and generates a third converting voltage. The fourth leg 448 is a fourth converter that receives an output from L 4 and generates a fourth converting voltage. The capacitor group (C 1 , C 2 ) receives the DC voltage from the leg portion 440 and performs charge / discharge.

5 illustrates operational characteristics of an interleaved dual-buck converter in accordance with an embodiment of the present invention. The control unit 450 divides one period of the AC negative voltage by a half period to make S 1 , D 1 , S 4 and D 4 operate when the voltage value has a positive value, and S 2 , D 2 , S 3 , and D 3 is Do not operate. In contrast, the controller 450 of FIG. 4 allows S 2 , D 2 , S 3 , and D 3 to operate when the AC negative voltage has a negative value, S 1 , D 1 , S 4 , and D 4 do not operate. The control unit 450 of FIG. 4 includes switching elements S 1 , S 2 , S 3 and S 4 and diodes D 1 , D 2 , D 3 and D 4 of the respective legs 442, 444, 446 and 448, Lt; / RTI > Here, the inversion operation means that the diode and the switching element are not turned on at the same time, that is, the switching element is turned off when the diode is on and the switching element is turned on when the diode is off.

(A) in FIG. 5 - (d) is AC portion (transformer primary side) is that the voltage is positive, v, and the value is a positive value of ac1 v from the value of the state of the value of the negative ac2, S 1, D 1 , S 4 , and D 4 , respectively. 5 (a) shows a state in which S 1 and S 4 are on and D 1 and D 4 are off. At this time, i ac1 increases in a direction output from the voltage v ac1 , and i ac2 decreases in a direction of input to the voltage v ac2 . On the other hand, both of C 1 and C 2 are in the discharge state. FIG. 5B shows a state in which D 1 and D 4 are on and S 1 and S 4 are off. At this time, i ac1 decreases in the direction output from the voltage v ac1 , and i ac2 decreases in the direction input to the voltage v ac2 . On the other hand, C 1 and C 2 are all in a charged state. FIG. 5C shows a state in which S 1 and D 4 are on and D 1 and S 4 are off. At this time, i ac1 increases in a direction output from the voltage v ac1 , and i ac2 decreases in a direction input to the voltage v ac2 . On the other hand, C 1 is in a discharged state and C 2 is in a charged state. 5D shows that D 1 and S 4 are on and S 1 and D 4 are off. At this time, i ac1 decreases in the direction output from the voltage v ac1 , and i ac2 increases in the direction input to the voltage v ac2 . At this time, i ac1 decreases in the direction output from the voltage v ac1 , and i ac2 increases in the direction input to the voltage v ac . On the other hand, C 1 becomes a charged state and C 2 becomes a discharged state.

When the AC negative voltage is a positive value, the operation of the interleaved dual-buck converter is summarized as follows: L 1 current flows in the direction always output from the voltage v ac1 and L 4 current flows in the direction always inputted from the voltage v ac2 Able to know. 5 (a) and 5 (c), when S 1 is in an on state, C 1 is in a discharge state. In (b) and (d) of FIG. 5, when S 1 is off, C 1 is in a charged state. From these results, it can be seen that when the AC negative voltage is a positive value, the voltage of C 1 can be controlled using S 1 , and the voltage of C 2 can be controlled using S 4 . Thus, unlike a dual-buck half-bridge converter, an interleaved dual-buck converter can control both C 1 and C 2 voltages during a positive half-cycle.

The following shows the operating characteristics according to the on / off states of S 2 , D 2 , S 3 , and D 3 with the AC negative voltage being a positive value. FIG. 5E shows a state in which S 2 and S 3 are on, and D 2 and D 3 are off. At this time, i ac1 increases in the direction of input to the voltage of v ac1 , and i ac2 increases in the direction of output from the voltage of v ac2 . On the other hand, both of C 1 and C 2 are in the discharge state. In FIG. 5 (g), S 2 and D 3 are on, and D 2 and S 3 are off. 5 (h) shows a state in which D 2 and S 3 are on and S 2 and D 3 are off. At this time, i ac1 decreases in the direction of input to the voltage v ac1 , and i ac2 increases in the direction output from the voltage v ac . On the other hand, C 1 is in a discharged state and C 2 is in a charged state.

When the AC negative voltage is negative, the operation of the interleaved dual-buck converter is summarized as follows. L 2 current flows in the direction of always entering the voltage of v ac1 , and L 3 current flows in the direction of always output from the voltage of v ac2 . 5 (e) and 5 (g), C 2 is in the discharge state when S 2 is on and C 1 is in the discharge state when S 2 is off in FIGS. 5 (f) do. Similarly, also in the 5 (e), when the S 3 from (h), and the condition C 1 is discharged, when the S 3 is turned off at (f), (g) of Figure 5 is C 1 The battery is in a charged state. From these results, it can be seen that the C 2 voltage can be controlled by S 2 when the AC negative voltage is negative, and the C 1 voltage can be controlled by S 3 . Thus, it is shown that both the C 1 and C 2 voltages can be controlled during the negative half period of the interleaved dual-buck converter 400.

5, it can be seen that the interleaved dual-buck converter 400 can control both the C 1 and C 2 voltages during one cycle of the AC negative voltage. Also, if the turn ratio of the primary, secondary, and tertiary windings of the transformer is 1: 1: 1, the current on the secondary side of the transformer is the same as the primary side current of the transformer. .

6 is a block diagram of a controller of an interleaved dual-buck converter in accordance with an embodiment of the present invention. The controller 450 includes a PLL 610, a first subtractor 620, a second subtractor 620, a third subtractor 620, a fourth subtractor 620, a first voltage controller 630, The second switch 660, the first multiplier 640, the second multiplier 640, the first current controller 650, the second current controller 650, the first switch 660, the second switch 660, A first comparator 680, a second comparator 680, and a third comparator 670. The switch 660, the first inverter 670, the second inverter 670, the third inverter 670, the fourth inverter 670, 680 and a fourth comparator 680.

The PLL 610 causes the phases of the AC negative voltage V ac and the phases of the AC internal power supply V ac | sin? T to be supplied to the interleaved dual-buck converter 400 to match each other. That is, the PLL 610 compensates for the phase difference between the AC negative voltage (V ac ) due to the delay generated in the interleaved dual-buck converter (400) to perform accurate phase control. The first switch 660, the second switch 660, and the third switch 660 are connected to the first terminal when the value of V ac is positive, and to the terminal of 2 when negative.

The first subtractor 620 receives the reference DC voltage V dcT * as a positive terminal, and the reference DC voltage value is set to a value corresponding to half of V dc . The negative terminal of the first subtractor 620 is connected to V dcT . The first subtracter 620 calculates the difference between V dcT * and V dcT and delivers the result to the first voltage controller 630.

The second subtractor 620 receives the reference DC voltage V dcB * as a positive terminal, and the reference DC voltage value is set to a value corresponding to half of V dc . The second subtractor 620 is connected to V dcB as a negative terminal. The second subtractor 620 transfers the difference between V dcB * and V dcB to the second voltage controller 630.

The first voltage controller 630 performs PI control (Proportional-Integral Control) and performs a control operation proportional to the magnitude of the error value of the first voltage controller 630 and an integration of the error value of the first voltage controller 630 And a steady-state error is reduced by performing a control operation proportional to the steady state. The output of the first voltage controller 630 becomes the peak value I pkT * of the current flowing in the inductor.

The second voltage controller 630 performs the PI control and performs a control operation proportional to the magnitude of the error value of the first voltage controller 630 and proportional to the integration of the error value of the first voltage controller 630 It works to reduce the steady-state error. The output of the first voltage controller 630 becomes the peak value I pkB * of the current flowing in the inductor.

The first multiplier 640 receives and multiplies the output I pkT * of the first voltage controller 630 and the AC internal power source sin ωt . That is, the first multiplier 640 and outputs the multiplied I acT * sinωt I in pkT *. I acT * is the reference current of v ac1 derived from the secondary winding, and is transmitted to the third subtracter 620 via the first switch 660.

The second multiplier 640 receives and multiplies the output I pkB * of the second voltage controller 630 and the AC internal power source sin ωt. That is, the second multiplier 640 multiplies I pkB * by sin? T and outputs I acB * . I acB * is the reference current of v ac2 derived from the tertiary winding, and is transmitted to the fourth subtracter 620 via the first switch 660.

When V ac is positive, the third subtracter 620 receives a positive terminal connected to the first terminal of the first switch 660 and receives i acT * . On the other hand, when V ac is negative, it is connected to the second terminal of the first switch 660 and receives i acB * . The third subtracter 620 receives i ac1 as a negative terminal. The third subtractor 620 transfers the difference between i acT * or i acB * and i ac1 to the current controller 650.

A fourth subtractor 620, V if ac is positive, the positive terminal is first connected to a first terminal of the switch (660) i acB * is an inverted signal being input a via a second inverter (670) input do. On the other hand, when V ac is negative, it is connected to the second terminal of the first switch 660 and receives the inverted signal through the first inverter 670 after receiving i acT * . The fourth subtracter 620 receives i ac2 as a negative terminal. The fourth subtractor 620 transfers the difference between i acT * or i acB * and i ac2 to the current controller 650.

The first current controller 650 performs a control operation proportional to the magnitude of the error value of the third subtractor 620 and a control action proportional to the integration of the error value of the third subtractor 620, . The output of the first current controller 650 transfers a signal for controlling the duty to a first comparator 680 or a second comparator 680 via the second switch 660 in a rational number between -1 and 1.

The first current controller 650 may be coupled to the < RTI ID = 0.0 > Controls to reduce the difference between i acB * and i ac1 . Where i acT * or i acB * is a signal generated from sin? t synchronized with V ac by the PLL 610. The first current controller 650 may be coupled to the < RTI ID = 0.0 > Synchronize V ac and i ac1 * through control to reduce the difference between i acB * and i ac1 . Accordingly, the first current controller 650 performs the PFC operation.

The second current controller 650 receives i acT * and outputs the inverted current or i accept acB * Inverted by the second inverter 660 And controls to reduce the difference between current and i ac2 . Where i acT * or i acB * is a signal generated by PLL 610 from sin? t synchronized with V ac . A second current controller 650 is an inverted current i receives the * acT through the first inverter 660, or i accept acB * Inverted by the second inverter 660 V ac and i ac2 * are synchronized by controlling the difference between current and i ac2 . Accordingly, the second current controller 650 performs the PFC operation.

When the AC negative voltage is a positive value, the positive terminal of the first comparator 680 receives the output voltage between -1 and 1 of the first current controller 650, which is the first terminal of the second switch 360 , And the negative terminal receives the voltage of the triangular wave having a magnitude between -1 and 1. The first comparator 680 compares the output voltage value of the output voltage value with the triangular wave of the first current controller 650, and supplies an output voltage to S 1 in Fig.

When the AC negative voltage is negative, the positive terminal of the second comparator 680 is connected to the output of the first current controller 650, which is the second terminal of the second switch 660, and the first current controller 650 The output of the third inverter 670 is inverted. The negative terminal of the second comparator 680 receives the voltage of the triangular wave having a magnitude between -1 and 1. The output voltage value of the third inverter 670 of the second comparator 680 is compared with the output voltage value of the triangular wave, and the output voltage is supplied to S 2 of FIG.

When the AC negative voltage is a negative value, the positive terminal of the third comparator 680 receives the output voltage between -1 and 1 of the second current controller 650, which is the second terminal of the third switch 360 , And the negative terminal receives the voltage of the triangular wave having a magnitude between -1 and 1. The output voltage value of the second current controller 650 of the third comparator 680 is compared with the output voltage value of the triangular wave, and the output voltage is supplied to S 3 of FIG.

When the AC negative voltage is a positive value, the positive terminal of the fourth comparator 680 is connected to the output of the second current controller 650, which is the first terminal of the third switch 660, and the second current controller 650 And the output of the fourth inverter 670 is inverted. The negative terminal of the fourth comparator 680 receives the voltage of the triangular wave having a magnitude between -1 and 1. The fourth comparator 680 compares the output voltage value of the triangular wave with the output voltage value of the fourth inverter 670, and supplies the output voltage to S 4 of FIG.

Simulations were performed to analyze the operating characteristics of the circuits of FIGS. 1 and 4. A PSIM tool is used for the simulation, and the controllers 120 and 450 shown in FIG. 3 and FIG. 6 are used for the circuit control.

Figure 7 illustrates simulation parameters in accordance with an embodiment of the present invention. The interleaved dual-buck converter 400 has a voltage of the AC portion of 220 Vrms and a voltage of the DC portion of 700 V. The capacity is 4.9 kW. L 1 , L 2 , L 3 and L 4 Values of 1 mH each, and C 1 , C 2 The value is 5000 μF. The turn ratio of the primary, secondary, and tertiary windings of the transformer is 1: 1: 1 and the switching frequency is 50 kHz.

8 shows the current relationship between the AC negative voltage and current and L 1 and L 2 of a dual-buck half-bridge converter according to an embodiment of the present invention. Dual-buck half-bridge converter 100 v ac voltage is positive due to the S 1 ON / OFF operation flows, and the current is increased or decreased to L 1 when the value of a, v when the ac voltage is negative value of S 2 on / off Due to the operation, the current flows to L 2 with increasing or decreasing. At this time, i ac is the sum of one period of L 1 and L 2 currents, and the current peak value of L 1 and L 2 is equal to i ac .

Figure 9 illustrates the AC negative and DC negative voltage relationships of a dual-buck half-bridge converter in accordance with an embodiment of the present invention. The dual-buck half-bridge converter 100 controls the C 1 voltage (V dcT ) due to the S 1 on / off operation and the C 2 voltage (V dcB ) continuously discharges when the v ac voltage is a positive value . Conversely, it can be seen that the dual-buck half-bridge converter 100 controls the C 2 voltage due to the S 2 on / off operation and the C 1 voltage continues to discharge when the v ac voltage is negative. At this time, the DC portion (V dc ) is represented by the sum of the C 1 voltage and the C 2 voltage.

8 and 9, the dual-buck half-bridge converter 100 can perform the PFC control and the rectifying and boosting from the AC part to the DC negative voltage, but the AC part current is equal to the L 1 and L 2 current for half a period, It can be seen that only one of the C 1 and C 2 voltages is controllable.

10 illustrates the current relationship between the AC negative voltage and current and L 1 and L 2 of an interleaved dual-buck converter according to an embodiment of the present invention. When the v ac voltage is positive, the interleaved dual-buck converter 400 can see that the voltage v ac1 is also a positive value, and the current flows to and flows through L 1 due to the on / off operation of S 1 . The interleaved dual-buck converter 400 has a negative value of v ac1 when the v ac voltage is a negative value, and the current flows to the L 2 due to the on / off operation of S 2 . At this time, i ac1 is the sum of one period of L 1 and L 2 currents, and the current peak value of L 1 and L 2 is half of i ac . Because i ac flows in half from v ac2 is inverted to AC voltage parts.

11 shows current relationships of AC negative voltage, current, v ac2 voltage, current, L 3 and L 4 of an interleaved dual-buck half-bridge converter according to an embodiment of the present invention. The interleaved dual-buck converter 400 can see that the v ac2 voltage is a negative value when the v ac voltage is a positive value. The on / off operation of S 4 causes a current to flow through L 4 , and when the v ac voltage is negative, the v ac voltage flows to L 3 due to the on / off operation of the positive value S 3 . At this time, i ac2 is L 3, and the sum of the current for a period of 4 L, the current peak value of L 3, L 4 it can be seen that half of the ac i. This is because half of i ac is flowing from v ac1, which is in phase with the AC negative voltage.

12 illustrates the AC negative voltage and DC negative voltage relationships of an interleaved dual-buck half-bridge converter according to an embodiment of the present invention. The interleaved dual-buck converter 400 controls the C 1 voltage and the C 2 voltage, respectively, due to on / off operations S 1 and S 4 when the v ac voltage is a positive value. Conversely, when the ac voltage is negative, S 2 and S 3 control the C 2 voltage and C 1 voltage, respectively, due to on / off operation. The DC negative voltage is the sum of the C 1 voltage and the C 2 voltage. It can be seen that it is controlled in all the sections without the period of always discharging during one period different from the C 1 voltage and the C 2 voltage shown in FIG.

10, 11 and from the Figure 12, an interleaved dual according to the embodiment buck converter 400 is a rectified and boosted to a DC negative voltage from the PFC control and AC negative voltage, of course, L 1, L 2, L 3 and L 4 current flows in half of the AC sub-current, it is easy to increase the capacity. In addition, C 1 And the voltage of C 2 can be controlled.

The foregoing description is merely illustrative of the technical idea of the present embodiment, and various modifications and changes may be made to those skilled in the art without departing from the essential characteristics of the embodiments. Therefore, the present embodiments are to be construed as illustrative rather than restrictive, and the scope of the technical idea of the present embodiment is not limited by these embodiments. The scope of protection of the present embodiment should be construed according to the following claims, and all technical ideas within the scope of equivalents thereof should be construed as being included in the scope of the present invention.

120, 450: control unit 110, 440:
310, 610: PLL 320:
330: Voltage controller 340: Multiplier
350: current controller 360: switch
370: inverter 380: comparator
420: transformer 422: primary winding
424: transformer core 426: secondary winding
428: Third winding

Claims (13)

A primary winding to which an AC voltage V ac is applied, a secondary winding and a tertiary winding derived from the primary winding to generate a first induced voltage v ac1 and a second induced voltage v ac2 , respectively Transformer;
A first inductor L 1 and a second inductor L 2 connected in parallel at one end of the secondary winding to generate a first link voltage and a second link voltage, An inductor group including a third inductor (L 3 ) and a fourth inductor (L 4 ) generating a link voltage and a fourth link voltage;
Wherein the first inductor, the second inductor, the third inductor, and the fourth inductor are connected to each other to output the first link voltage, the second link voltage, the third link voltage, A leg portion including a first converter, a second converter, a third converter, and a fourth converter for receiving and generating different converting voltages;
A capacitor group for receiving the different converting voltages from the leg portion to perform charging and discharging; And
A control unit for generating a control signal for controlling switching of the leg unit for charging / discharging the capacitor group,
, ≪ / RTI &
The first converter, the second converter, the third converter and the fourth converter are respectively connected to a first diode D 1 and a first switch S 1 , a second diode D 2 and a second switch S 2), the third diode (D 3) and the third switch (S 3), the fourth diode (including D 4) and the fourth switch (S 4), and the first diode is the first of the first inductor 1 switch is connected to a positive terminal of the load and the second diode is connected to a negative terminal of the load and a second node to which the second inductor and the second switch are connected, The third diode is connected to a third node to which the third inductor and the third switch are connected and a positive terminal of the load, and the fourth diode is connected to the fourth node to which the fourth inductor and the fourth switch are connected, And the other terminal of the third switch is connected to the negative terminal of the load, Is connected to the negative terminal of the load, the other end of the other end of the fourth switch of the second switch is interleaved dual characterized in that connected to the positive terminal of the load-buck converter. The transformer according to claim 1,
Wherein the AC voltage is applied to the primary winding and the first induced voltage having the same phase as the AC voltage is induced in the secondary winding and a phase opposite to the phase of the first induced voltage is induced in the tertiary winding And wherein the second inductive voltage having the second inductive voltage is induced. 3. The method of claim 2,
Wherein the transformer is configured to generate a current of the same magnitude as the current flowing in the primary winding for one period of the AC voltage, to the secondary winding and the tertiary winding so that the primary winding, the secondary winding, And the winding ratio is 1: 1: 1. The interleaved dual- delete The method according to claim 1,
Wherein the secondary winding and the tertiary winding have a winding direction such that phases of a current flowing in the first inductor or the second inductor and a phase of a current flowing in the third inductor or the fourth inductor are opposite to each other, And the other end of the secondary winding and the other end of the third winding are connected to each other. 6. The method of claim 5,
Wherein the capacitor group includes a first capacitor (C 1 ) and a second capacitor (C 2 ) connected in series between both terminals of the leg portion, wherein a connection end of the first capacitor and the second capacitor is connected to a terminal And the other end of the third winding is connected to the other end of the third winding. delete The method according to claim 1,
Wherein an anode and a cathode of the first diode are respectively connected to the first node and a positive terminal of the load and an anode and a cathode of the second diode are respectively connected to the second node and the negative terminal of the load, An anode and a cathode of the third diode are respectively connected to the third node and a positive terminal of the load and an anode and a cathode of the fourth diode are respectively connected to the fourth node and the negative terminal of the load Features an interleaved dual-buck converter. 9. The apparatus according to claim 8,
When the first diode is turned on, the first switch is turned off. When the first diode is turned off, the first switch is turned on. When the second diode is turned on, the second switch is turned off , The second switch is turned on when the second diode is turned off, the third switch is turned off when the third diode is turned on, the third switch is turned on when the third diode is turned off, The fourth switch is turned off when the first diode is turned on, and the fourth switch is turned on when the fourth diode is turned off. 9. The method of claim 8,
Wherein the capacitor group includes a first capacitor (C 1 ) and a second capacitor (C 2 ) connected in series between both terminals of the leg portion, wherein a connection end of the first capacitor and the second capacitor is connected to a terminal And the control unit controls the first capacitor voltage using the first switch when the AC voltage is a positive value and controls the first capacitor voltage using the second switch when the AC voltage is a positive value, Controlling the second capacitor voltage by using the second switch when the AC voltage is a negative value and controlling the first capacitor voltage by using the third switch to control the first capacitor voltage for one period, 1 < / RTI > capacitor and the second capacitor. 9. The method of claim 8,
The current of the first inductor flows in a direction of outputting from the secondary winding and the current of the fourth inductor flows in a direction of input of the tertiary winding when the AC voltage is a positive value,
The second inductor current flows in a direction to be outputted from the secondary winding and the current of the third inductor flows in a direction to be input to the tertiary winding when the AC voltage is a negative value Interleaved dual-buck converter. 11. The method of claim 10,
Wherein the capacitors of the first inductor to the fourth inductor have the same capacitance. delete
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KR102532877B1 (en) 2021-11-16 2023-05-15 고려대학교 산학협력단 A dual-phase dual-path buck-boost dc-dc converter with continuous input output currents and single-mode operation
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060208711A1 (en) 2004-12-14 2006-09-21 International Rectifier Corp. EMI noise reduction circuit and method for bridgeless PFC circuit
JP2011142726A (en) 2010-01-06 2011-07-21 Logah Technology Corp Interleave bridgeless power factor corrector and method of controlling the same
US20140268952A1 (en) * 2013-03-12 2014-09-18 XP Power Limited Bridgeless interleaved power factor correction circuit using a pfc inductor with quad-winding on a single core

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060208711A1 (en) 2004-12-14 2006-09-21 International Rectifier Corp. EMI noise reduction circuit and method for bridgeless PFC circuit
JP2011142726A (en) 2010-01-06 2011-07-21 Logah Technology Corp Interleave bridgeless power factor corrector and method of controlling the same
US20140268952A1 (en) * 2013-03-12 2014-09-18 XP Power Limited Bridgeless interleaved power factor correction circuit using a pfc inductor with quad-winding on a single core

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