KR101740932B1 - Wireless Communication System for Basement Station Baseband Signal Processing based on Multi-core DSP of DU/RU Separated Type Structure - Google Patents

Abstract

Disclosed is a wireless communication system and its communication method for multi-core DSP-based base station baseband signal processing of a DU / RU separation structure. A wireless communication system for multi-core DSP-based base station baseband signal processing of a DU / RU separation structure according to the present invention comprises: a digital signal processing device concentratedly installed in a digital signal processing center; A wireless signal processing device remote from the digital signal processing device and installed in a service target area; And an interface for connecting the digital signal processing device and the wireless signal processing device, wherein the digital signal processing device and the wireless signal processing device cooperate with each other through an interface.

Description

Technical Field [0001] The present invention relates to a multi-core DSP based base band signal processing based on a DU / RU separation type wireless communication system,

The present invention relates to a wireless communication system and a communication method thereof for multi-core DSP base station baseband signal processing of a DU / RU separation structure, and more particularly, to a wireless communication system and a communication method therefor, RU: Separate structure of DU / RU that can flexibly allocate and add digital signal processing resources according to network load by applying structure that can replace base station with only L2 / L3 and baseband modem by separating RU: Radio Unit And more particularly, to a wireless communication system and a communication method thereof for multicore DSP-based base station baseband signal processing.

In recent years, mobile terminals such as smart phones and tablets have spread rapidly, making it difficult to handle the amount of wireless data traffic that is increasing in the case of existing base station type equipment.

When the capacity of the wireless network is increased by the existing base station method, the rent of the top surface of the base station is greatly increased, and the operation cost is greatly increased because the indoor top surface and the cooling and power peripheral devices are required for each base station. Such an increase in the operating cost is transferred to the mobile communication data fee of the user, which causes a problem that the user can not meet the satisfaction of the user with respect to the data usage charge burden.

The existing base station baseband modem device mainly uses FPGA (Field Programmable Gate Array), but recently it has been developing a baseband modem based on a multicore DSP (Digital Signal Processor) for low cost and ease of development.

However, the development of a coder / decoder, a modulator / demodulator, and a synchronizer implementation of dozens of expensive FPGAs and single-core DSP chips in a base station baseband modem device causes a problem in cost of the FPGA chip In addition, it is difficult to handle the base station baseband signal and protocol which are explosively increasing because it is difficult to cope with the processing speed of the conventional single-core DSP or FPGA.

Disclosure of the Invention The present invention has been made to solve the above-mentioned problems, and it is an object of the present invention to provide a wireless communication system capable of replacing a base station by only L2 / L3 and a baseband modem by separating a digital signal processing unit (DU) and a radio signal processing unit Based DSP base station base band signal processing and its communication method capable of flexibly allocating and expanding digital signal processing unit resources according to the network load by applying the DU / RU separation structure .

Further, the present invention can greatly reduce the investment cost and the operation cost by easily expanding the network even with a small cost, and is capable of efficiently coping with explosively increasing mobile data traffic, And a radio communication system for DSP base station baseband signal processing and a communication method therefor.

The present invention also aims at providing a technology for separating DU and RU, a multi-core DSP-based signal processing platform technology, and hardware design technology for flexible extension of RU according to frequency band.

According to an aspect of the present invention, there is provided a wireless communication system for multi-core DSP-based base station baseband signal processing in a DU / RU separation structure, comprising: a digital signal processing device installed in a digital signal processing center; A wireless signal processing device remote from the digital signal processing device and installed in a service target area; And an interface for connecting the digital signal processing device and the wireless signal processing device, wherein the digital signal processing device and the wireless signal processing device cooperate with each other through an interface.

The digital signal processing apparatus includes a communication controller for controlling communication between a MAC (Media Access Control) layer and a network layer; And a baseband modem unit for relaying signals between the communication control unit and the wireless signal processing device.

The communication control unit includes: an L3 control unit, which is a DSP (Digital Signal Processor) module having a core network and a Gigabit Ethernet interface; And an L2 control unit that executes MAC layer control software for data traffic.

The baseband modem unit transmits and receives signals using a 6.25Gbps SRIO (Serial Rapid IO) interface, which is a serial high-speed input / output switch, and a 6.144Gbps CPRI (Common Public Radio Interface).

The baseband modem unit operates as a master and the radio signal processing unit operates as a slave.

The baseband modem unit includes a DSP 1 and a DSP 2 that process a DSP in software form and perform a baseband modem function in a coprocessor that is a hardware accelerator; FPGA 1 providing DSP1 and DSP2 with Peripheral Component Interconnect-express (PCIe) high-speed communications and DSP GPIO ports; An FPGA 2 for receiving a system clock from a remote radio unit of a wireless signal processing apparatus and distributing a necessary clock in a baseband modem unit; And an SRIO switch connecting DSP 1, DSP 2, FPGA 1, and FPGA 2 to each other.

FPGA 1 can share Flash ROM with FPGA 2.

The SRIO switch can switch packets for board-to-board communication that interconnects L2 / L3 top boards.

The wireless signal processing apparatus includes an optical-electrical converter for converting a signal received from the baseband modem unit into an electrical signal; A digital / analog converter for digital / analog conversion of the signal converted by the optical / electrical converter; An intermediate frequency up converter for up converting the signal converted by the digital / analog converter to an intermediate frequency; And a power amplifier for converting a signal up-converted by the intermediate-frequency up-converter into a high-frequency carrier, amplifying the power, and transmitting the amplified signal through an antenna.

A radio signal processing apparatus includes: a low noise amplifier for filtering and amplifying noise from a signal received from an antenna; An intermediate frequency down converter for down-converting the frequency of the signal amplified by the low noise amplifier to an intermediate frequency; And an analog-to-digital converter for analog-to-digital conversion of the down-converted signal by the intermediate frequency down-converter. In this case, the opto-electric converter converts the signal converted by the analog / digital converter into a baseband signal and transmits it to the baseband baseband modem unit.

According to an aspect of the present invention, there is provided a wireless communication method including: a digital signal processing device; a wireless signal processing device remote from the service target area and a digital signal processing device; The digital signal processing device and the wireless signal processing device are interfaces of the wireless signal processing device. The multi-core DSP based base station of the DU / RU separable structure interworking with each other through the interface. A communication method, comprising: controlling communication between a MAC layer and a network layer; And relaying the signal controlled by the communication control step to the wireless signal processing device.

The communication control step may control the communication using an L3 control unit, which is a DSP module having a core network and a Gigabit Ethernet interface, and an L2 control unit, which executes MAC layer control software for data traffic.

The signal relaying step transmits and receives signals using the communication control step and the 6.25Gbps SRIO interface, which is a serial high-speed input / output switch, and transmits and receives signals through the 6.145Gbps CPRI of the wireless signal processing device and the public wireless interface .

The wireless signal processing apparatus includes: converting a signal received from the baseband modem unit into an electric signal; Digital-to-analog converting the converted electric signal; Converting the converted analog signal to an intermediate frequency; And converting the up-converted signal to an intermediate frequency into a high-frequency carrier, amplifying the power, and transmitting the amplified signal through the antenna.

The wireless signal processing apparatus may further include: filtering and amplifying noise from a signal received by the antenna; Down converting the frequency of the amplified signal to an intermediate frequency; Converting the down-converted signal to an intermediate frequency; And converting the converted digital signal into a baseband signal and transmitting the converted baseband signal to the baseband baseband modem unit of the digital signal processing apparatus.

The wireless communication system for multi-core DSP base station baseband signal processing of the DU / RU separation structure according to the present invention can greatly reduce the investment cost and the operation cost by facilitating the network expansion with a small cost.

In addition, according to the present invention, when a conventional base station baseband modem is implemented by applying a multi-core DSP based signal processing platform technology to a base station baseband modem device, the cost reduction effect can be achieved rather than using dozens of expensive FPGAs Can be obtained.

Also, according to the present invention, it is difficult to cope with the computation processing speed with the conventional single-core DSP or FPGA. However, when the multi-core DSP based technology is applied to the base station baseband modem apparatus, the baseband signal and protocol, Can be processed. Therefore, it can be a best alternative to efficiently cope with the explosion of mobile data traffic, thereby reducing the convenience and cost of efficient operation.

1 is a schematic diagram illustrating a wireless communication system for baseband signal processing of a multi-core DSP based base station according to an embodiment of the present invention.
2 is a diagram schematically showing a configuration of a baseband modem unit of the digital signal processing apparatus shown in FIG.
FIG. 3 is a diagram illustrating a multi-core interworking structure according to an embodiment of the present invention.
4 is a diagram showing a configuration of the radio signal processing apparatus shown in Fig.
5 is a diagram schematically showing the configuration of a multicore DSP block constituting a baseband modem unit.
FIG. 6 is a flowchart illustrating a method of wireless communication for multicore DSP-based base station baseband signal processing according to an exemplary embodiment of the present invention.
FIG. 7 is a flowchart illustrating a wireless communication method for baseband signal processing based on multicore DSP based on an embodiment of the present invention, and shows a method of processing a signal received from a baseband modem unit by a wireless signal processing apparatus.
FIG. 8 is a flowchart illustrating a wireless communication method for baseband signal processing based on multicore DSP based on an embodiment of the present invention, and shows a method of processing a signal received through an antenna by a wireless signal processing apparatus.

Hereinafter, a multicore DSP based base station baseband modem apparatus and a driving method thereof according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

1 is a schematic diagram illustrating a wireless communication system for multi-core DSP based base station baseband signal processing of a DU / RU separation structure according to an embodiment of the present invention.

Referring to FIG. 1, a wireless communication system for multi-core DSP-based base station baseband signal processing according to an embodiment of the present invention includes a digital signal processing device 100 and a wireless signal processing device 400 And the digital signal processing apparatus 100 is concentrated in a separate digital signal processing center, and the wireless signal processing apparatus 400 is remotely installed in the service target area. At this time, the digital signal processing apparatus 100 and the wireless signal processing apparatus 400 are connected to each other via the interface 600 and interlocked with each other through the interface 600 connected thereto.

 The digital signal processing apparatus 100 includes a communication control unit 200 connected to a core network and controlling communication between a MAC (Media Access Control) layer and a network layer, and a communication control unit 200 and a wireless signal processing unit 400, And a baseband modem unit 300 for relaying signals between the baseband modem unit 300 and the baseband modem unit 300.

The wireless signal processing apparatus 400 may include a remote wireless unit 500 that processes signals between the baseband modem unit 300 of the digital signal processing apparatus 100 and another wireless signal processing apparatus.

The communication control unit 200 includes an L3 control unit, which is a DSP (Digital Signal Processor) module having a core network and a Gigabit Ethernet interface; And an L2 control unit that executes MAC layer control software for data traffic.

The baseband modem unit 300 transmits and receives signals using the SRIO (Serial Rapid IO) interface of 6.25 Gbps, which is a serial high-speed input / output switch, to the communication control unit 200, And a common public radio interface (CPRI) of a public wireless access point of 6.144 Gbps. At this time, the CPRI of the baseband modem unit 300 operates as a master and the CPRI of the remote radio unit 500 of the radio signal processing device 400 operates as a slave. Here, up to three CPRI interfaces of the baseband modem unit can be connected, thus up to three remote radio units 500 can be connected. In addition, when the remote radio unit 500 transmits / receives signals to / from another remote radio unit, the remote radio unit 500 operates as a master and the other remote radio unit operates as a slave to transmit / receive signals.

2 is a diagram schematically showing a configuration of a baseband modem unit of the digital signal processing apparatus shown in FIG.

The baseband modem unit 300 includes a DSP 1 302 and a DSP 2 304, an FPGA 1 306 and an FPGA 2 308 as shown in FIG. 2, and an SRIO switch 310 ).

DSP 1 302 and DSP 2 304 process the DSP in software form and perform a baseband modem function in a hardware accelerator coprocessor. Each DSP 1 302 and DSP 2 304 included in the baseband modem unit 300 is composed of four independent DSP core devices each having a clock speed of 1.2 GHz at maximum, And performs functions of a transmitter and a receiver of the baseband modem. That is, one of the eight DSP cores uses all cores as master cores with function and time control, and the other uses cores as antenna cores for L2 / L3 upper layer and remote radio parts. The remaining six cores are composed of an operating core that performs detailed functions of the baseband modem of the transmitter and the receiver (see FIG. 3).

DDR3 SDRAM 312 may be used as a local memory dependent on each DSP core and as a shared memory for sharing between DSP cores. The DSP 1 302 and the DSP 2 304, the FPGA 1 306, and the FPGA 2 308 are connected to each other through the SRIO switch 310. The baseband modem unit transmits / receives data and control information to the L2 / L3 unit through the SRIO I / F unit 314 connected to the SRIO switch 310 to perform SRIO communication at a transmission rate of 6.25 Gbps. The DSP 2 304 performs CPRI high-speed interface communication with the remote radio unit at a transmission rate of 6.144 Gbps through the CPRI I / F unit 316, which is a CPRI interface. The CPRI provides a standard interface for connecting the remote radio unit to the baseband modem unit 300, so that operators can combine these devices supplied by different vendors.

The FPGA 1 306 provides a Peripheral Component Interconnect-express (PCIe) high speed communication function and a DSP GPIO port to the DSP 1 302 and the DSP 2 304 via a Mezzanine connector in the baseband modem unit 300. In addition, it shares the flash ROM 320 with the FPGA 2 308, interfaces with the DDR3 SDRAM 312, and the SRIO switch 310, and performs LED control and FPGA 1 temperature sensor functions.

The FPGA 2 308 receives the system clock from the remote radio unit 500 through the system clock unit 318 and distributes the required clock in the baseband modem unit 300. The FPGA 2 308 also converts the system clock into L2 / L3. The FPGA 2 308 provides the DSP 1 302 and the DSP 2 304 DSP functions via the Mezzanine connector in the baseband modem unit 300 as the FPGA 1 306 and provides a DSP reset signal , SPI (Serial Peripheral Interface) communication function. The FPGA 2 308 is interfaced with the flash ROM 320 and the SRIO switch 310 and is connected to the module management controller to control the module. It also provides an RS232C serial communication interface.

The SRIO switch 310 is connected to the SRIO I / F unit 314 as well as to the chip-to-chip interconnecting the DSP 1 302, the DSP 2 304, the FPGA 1 306 and the FPGA 2 308 It provides reliable, high-performance, packet-switched technology with increased bandwidth for board-to-board communication that interconnects L2 / L3 top boards through the backplane.

4 is a diagram showing a configuration of the radio signal processing apparatus shown in Fig.

The wireless signal processing apparatus 400 includes an optical / electrical and electrical / optical converter 402, a digital to analog converter 404, an intermediate frequency upconverter 406, a power amplifier 408, an antenna 410, a low noise amplifier 412, an intermediate frequency down-converter 414 and an analog-to-digital converter 416.

The optical / electrical and electrical / optical converter 402 converts a CPRI high speed optical signal transmitted from the baseband modem unit 300 of the base station digital signal processing apparatus 100 into an electrical signal.

The base-band baseband modem signal converted by the optical-electrical converter 402 is converted into an analog signal by the digital-to-analog converter 404.

The intermediate frequency up converter 406 upconverts the converted analog signal to the digital / analog converter 404 to an intermediate frequency, the signal passed through the intermediate frequency up converter 406 is converted into a high frequency carrier, Amplified by the power amplifier 408 so as to be output. The signal amplified and processed by the power amplifier 408 at a high power is transmitted through the antenna 410.

The low noise amplifier 412 filters the noise received by the antenna 410 and amplifies the signal while suppressing amplification to noise to the maximum. A signal amplified by the low noise amplifier 412 is transmitted to an intermediate frequency down converter 414 and down-converted to an intermediate frequency, and the analog-to-digital converter 416 converts the analog signal down- Converts the signal into a baseband signal, and transmits the CPRI high-speed optical signal to the baseband baseband modem unit 300 through the electrical / optical converter 402.

5 is a diagram schematically showing the configuration of a multicore DSP block constituting a baseband modem unit.

The DSP constituting the baseband modem unit 300 includes a core pack 330 composed of a plurality of cores, a multicore shared memory control unit 340 allowing a multicore to efficiently access the shared memory as in a local memory, A coprocessor 350 composed of a bit rate coprocessor (BCP) and a fast Fourier transform coprocessor (FFTC), which are peripherals that are required to implement a module necessary for implementing a band modem, and a communication function with an L2 / L3 upper layer A peripheral device 360 supporting a remote radio unit and a CPRI interface performing a transmission function, and a multi-core navigator 370 performing a queue manager and a packet DMA function to operate peripheral devices in the core, . Between the core pack 330 in the DSP block, the multicore shared memory controller 340, the coprocessor 350, the peripheral device 360 and the multicore navigator 370 is a non-blocking data transfer port at a rate of one terabit per second Data is transferred to the provided terranet (teraNet).

The core pack 330 of the DSP includes two multicore DSP chips having four cores. Accordingly, in order to use peripheral devices (CPRI, SRIO) 360 and a coprocessor (BCP, FFTC) 350, which are the same resources, the core performs scheduling through the multicore navigator 370 in the core. Scheduling is a process by which a base station determines how much each mobile user or device will receive the wireless bandwidth per frame.

The multicore navigator 370 handles packet transmission, memory allocation, accelerator triggering, multiple destinations, and so on, all of which are handled by the DSP core so that it does not consume a single cycle. Through multicore navigator 370, direct communication and memory access between the cores is possible.

The multi-core shared memory control unit 340 can operate efficiently from the data stored in the shared memory, in order to connect to the data of the external memory, or to reduce the performance loss when data is moved between the local memories of the respective cores have. By combining the multi-core (core pack) 330, the multicore shared memory control unit 340, the coprocessor 350, the peripheral device 360, and the terranet developed using the multi-core navigator 370, The baseband baseband modem unit 300 of FIG.

 In the DSP block configuration, the mobile data packets are queued in the multicore navigator at the antenna interface CPRI and then routed to the FFTC coprocessor. This packet waits in the queue and is routed to the DSP core for further processing. All of these actions are properly routed automatically without CPU intervention. Thus, data can be transferred between components without competition between different cores.

FIG. 6 is a flowchart illustrating a method of wireless communication for multicore DSP-based base station baseband signal processing according to an exemplary embodiment of the present invention.

1 to 6, the digital signal processing apparatus 100 controls communication between the MAC layer and the network layer (S110). In this case, the communication control step (S110) controls communication using an L3 control unit, which is a DSP module having a core network and a Gigabit Ethernet interface, and an L2 control unit, which executes MAC layer control software for data traffic.

Further, the digital signal processing apparatus 300 relays the signal controlled by the communication control step (S110) to the radio signal processing apparatus (400). Here, the signal relaying step S120 transmits and receives signals using the SRIO interface of 6.25 Gbps, which is a serial high-speed input / output switch, in the communication control step (S110), and transmits and receives signals using a 6.144 Gbps CPRI Lt; / RTI >

FIG. 7 is a flowchart illustrating a wireless communication method for baseband signal processing based on multicore DSP based on an embodiment of the present invention, and shows a method of processing a signal received from a baseband modem unit by a wireless signal processing apparatus.

1 to 7, the radio signal processing apparatus 400 converts a signal transmitted from the baseband modem unit 300 into an electrical signal (S210), and digital / analog converts the converted electrical signal S220).

The radio signal processor 400 converts the converted analog signal to an intermediate frequency (S230), converts the up-converted signal to an intermediate frequency into a high frequency carrier, amplifies the power, and transmits the amplified signal through the antenna S240).

FIG. 8 is a flowchart illustrating a wireless communication method for baseband signal processing based on multicore DSP based on an embodiment of the present invention, and shows a method of processing a signal received through an antenna by a wireless signal processing apparatus.

1 to 8, the wireless signal processing apparatus 400 filters and amplifies noise received from an antenna (S310), and down-converts the frequency of the amplified signal to an intermediate frequency (S320) .

In addition, the radio signal processor 400 converts the down-converted signal to an intermediate frequency (S330), converts the converted digital signal into a baseband signal, and transmits the converted baseband signal to the baseband baseband modem unit of the digital signal processor (S340).

The foregoing description is merely illustrative of the technical idea of the present invention and various changes and modifications may be made by those skilled in the art without departing from the essential characteristics of the present invention. Therefore, the embodiments disclosed in the present invention are intended to illustrate rather than limit the scope of the present invention, and the scope of the technical idea of the present invention is not limited by these embodiments. Further, the scope of protection of the present invention should be construed according to the claims, and all technical ideas within the scope of the same should be interpreted as being included in the scope of the present invention.

Claims (5)

A digital signal processing device installed in a centralized manner in a digital signal processing center;
A wireless signal processing device remote from the digital signal processing device and installed in a service target area; And
An interface for connecting the digital signal processing device and the wireless signal processing device;
/ RTI >
The digital signal processing device and the wireless signal processing device are interlocked with each other through the interface,
The digital signal processing apparatus comprising:
A communication controller for controlling communication between a MAC (Media Access Control) layer and a network layer; And
And a baseband modem unit for relaying signals between the communication control unit and the radio signal processing device,
The baseband modem unit,
A core pack having a plurality of cores;
Peripheral devices supporting the Common Public Radio Interface (CPRI);
A multicore shared memory control unit for supporting a shared memory access of the plurality of cores;
A coprocessor that is a hardware accelerator; And
And a multicore navigator for performing scheduling for each of the plurality of cores connected to the coprocessor or the peripheral device. The multi-core DSP based base station baseband signal processing system according to claim 1, delete The method according to claim 1,
The communication control unit,
An L3 control unit, which is a DSP (Digital Signal Processor) module having a core network and a Gigabit Ethernet interface; And
Core system baseband signal processing in a DU / RU discrete structure comprising an L2 control unit that executes MAC layer control software for data traffic. The method according to claim 1,
The baseband modem unit,
The communication control unit transmits and receives signals using a SRIO (Serial Rapid IO) interface of 6.25 Gbps class, which is a serial high-speed input / output switch, and transmits and receives signals through the CPRI of 6.144 Gbps class A Wireless Communication System for Baseband Signal Processing in a Multi - core DSP Base Station with a DU / RU Separated Structure. The method according to claim 1,
The baseband modem unit,
A multi-core DSP based base station baseband signal processing system operating as a master and a wireless signal processing device operating as a slave (DU / RU).

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