KR101736884B1 - Dram for providing successive row and column data - Google Patents

Dram for providing successive row and column data Download PDF

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Publication number
KR101736884B1
KR101736884B1 KR1020160023407A KR20160023407A KR101736884B1 KR 101736884 B1 KR101736884 B1 KR 101736884B1 KR 1020160023407 A KR1020160023407 A KR 1020160023407A KR 20160023407 A KR20160023407 A KR 20160023407A KR 101736884 B1 KR101736884 B1 KR 101736884B1
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South Korea
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data
column
access
signal
word line
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KR1020160023407A
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Korean (ko)
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장우영
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단국대학교 산학협력단
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G11C11/4087—Address decoders, e.g. bit - or word line decoders; Multiple line decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4097—Bit-line organisation, e.g. bit-line layout, folded bit lines

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)

Abstract

A dynamic memory is provided that provides data in a horizontal row and a vertical column, which are sequential in order to construct memory cells with one capacitor and two transistors to access rows and columns based on RAS and CAS signals. The dynamic memory for providing the presented continuous row and column data includes a capacitor for storing data having a column address or data having a column address and a capacitor for storing a column address stored in the capacitor when a control signal is applied through the first word line And a second transistor for detecting data having a column address stored in a capacitor when a control signal is applied through the second word line and outputting the detected data to a second bit line, As shown in Fig.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a dynamic random access memory (DRAM)

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a dynamic memory for providing continuous data of a horizontal row and a vertical column, and more particularly, to a dynamic memory for providing data of a horizontal row and a vertical column by accessing data having a column address, Memory.

Since conventional dynamic memory stores data based on a row address, efficient access is possible to data having the same column address, but data having the same column address causes serious performance loss and power consumption .

Since most applications access data with the same street address, conventional dynamic memory alone has provided sufficient performance. Therefore, problems due to the access based on the column address are not recognized as a serious problem.

However, as the spread of portable terminals increases, there is an increasing demand for data access based on a column address, in addition to existing data access based on a column address. That is, on the screen of the mobile terminal, access to data having a column address and a column address such as a portrait mode (portrait mode) and a landscape mode (landscape mode) is required.

For example, as shown in FIG. 1, an image normally displayed in the portrait mode of the portable terminal is stored in the memory of the portable terminal based on the row address. At this time, as shown in FIG. 2, when the memory is accessed in the same direction as the portrait mode in the landscape mode of the portable terminal, the portable terminal is displayed as an image rotated by 90 degrees. As shown in FIG. 3, in order to output a non-rotated image, images stored in a dynamic memory must be accessed based on a column address. However, in the conventional dynamic memory, data access performance based on a column address is very low, It was not used due to problems such as power consumption.

In order to solve the problem of the conventional dynamic memory, a method of storing the same image once on the basis of the row address, storing once on the basis of the column address, and storing the image twice has been used. That is, conventionally, an image which is stored as it is and rotated by 90 degrees is stored separately. At this time, conventionally, one image suitable for the image mode (i.e., the horizontal mode and the vertical mode) is selected and accessed based on the row address.

However, the method of storing the image twice has a problem of causing a waste of the memory bandwidth and additional power consumption because the same image is stored twice.

In addition, it provides efficient vertical addressing based on image processing, memory mapping, and memory controller, but does not solve the problem of performance degradation and power consumption.

Korean Registered Utility Model No. 20-0124131 (Name: Dynamic Memory Access Control Circuit)

SUMMARY OF THE INVENTION The present invention has been proposed in order to solve the above-mentioned problems of the prior art, and it is an object of the present invention to provide a memory cell comprising a single capacitor and two transistors, It is an object of the present invention to provide a dynamic memory that provides column data.

According to an aspect of the present invention, there is provided a dynamic memory for providing continuous row and column data, including a memory array in which a plurality of layers in which a plurality of memory cells are arranged in a matrix are stacked, A first word line decoder for activating a memory cell corresponding to an access address output from the first access circuit among a plurality of memory cells included in the memory array, A first sense amplifier for receiving and outputting the row data from the memory cell activated by the first word line decoder, a second access circuit for activating when the column access control signal is input and outputting the access address, A plurality of memory cells connected in parallel to the access address output from the second access circuit among the plurality of memory cells, A second sense amplifier for receiving and outputting the column data from the memory cell activated by the second word line decoder, and a second sense amplifier for outputting from the first sense amplifier or the second sense amplifier And a buffer for storing the row data or the column data and outputting the data to the outside.

The memory cell includes a capacitor for storing data having a column address or data having a column address, data having a column address stored in the capacitor when a control signal is applied through the first word line, And a second transistor for detecting data having a column address stored in the capacitor when the control signal is applied through the first transistor and the second word line, and outputting the detected data to the second bit line.

The first transistor has a gate terminal connected to the first word line, a source terminal connected to the capacitor, a drain terminal connected to the first bit line, and a control signal applied through the gate terminal, And detects the data having the column address and outputs it to the first bit line through the drain terminal.

The second transistor has a gate terminal connected to the second word line, a source terminal connected to the capacitor, a drain terminal connected to the second bit line, and a control signal applied through the gate terminal, And outputs data having a column address to the second bit line through the drain terminal.

The first access circuit includes a CAS signal value, a WE signal value, and an Idle signal value and a NOT product value of the RAS signal. The CAS signal value, the WE signal value, the Idle Signal value and the RAS signal value to apply the access address to the first word line decoder.

The second access circuit includes a logical product circuit of a RAS signal value, a WE signal value, and an Idle signal value and a NOT value of the CAS signal. The CAS signal value, the WE signal value, the Idle Signal value and the RAS signal value to apply the access address to the second word line decoder.

And a buffer control circuit for controlling the operation of the buffer including at least one of reading or writing the column data based on the control signal or reading or writing the column data.

The buffer control circuit generates a logical product of logical AND of the NOT value of the RAS signal and the Idle signal and the logical product of the CAS signal and the RAS signal value of the CAS signal and the Idle signal, Set column data or column data.

The buffer control circuit controls the writing operation or the reading operation of the buffer based on the WE (Write Enable) signal.

According to the present invention, the dynamic memory that provides the continuous row and column data provides an effect of increasing the efficiency of continuous column data access. That is, the dynamic memory that provides continuous row and column data activates a memory cell having the same column address by the RAS signal, and activates the memory cell having the same column address by the CAS signal. Thus, the bank activated in the RAS signal may be accessed by the CAS to generate data having the same column address, and the bank activated in the CAS signal may be accessed by the RAS to generate data having the same column address .

In addition, the dynamic memory providing continuous row and column data maintains all the functions of the existing DRAM, is compatible with the JEDEC interface, and has an effect of increasing the efficiency of continuous column data access.

In addition, the dynamic memory providing continuous row and column data requires about 2.6% larger area than the conventional DRAM, but it has a memory bandwidth improvement of about 5.8% and a response speed of about 14.8% And power consumption is improved by about 4.4%.

Figs. 1 to 3 are diagrams for explaining a method for accessing column data and column data in a conventional dynamic memory; Fig.
FIG. 4 is a diagram for explaining a dynamic memory for providing continuous row and column data in accordance with an embodiment of the present invention; FIG.
FIGS. 5 to 8 are views for explaining the memory array of FIG. 4;
Fig. 9 is a diagram for explaining the first access circuit of Fig. 4; Fig.
FIG. 10 is a diagram for explaining a second access circuit of FIG. 4; FIG.
11 is a diagram for explaining the buffer control circuit of Fig.
FIG. 12 is a diagram for explaining a function of a dynamic memory for providing continuous row and column data in accordance with an embodiment of the present invention; FIG.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings in order to facilitate a person skilled in the art to easily carry out the technical idea of the present invention. . In the drawings, the same reference numerals are used to designate the same or similar components throughout the drawings. In the following description of the present invention, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a dynamic memory providing continuous row and column data according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings. 4 is a view for explaining a dynamic memory for providing continuous row and column data according to an embodiment of the present invention. 5 to 8 are views for explaining the memory array of FIG. 4, FIG. 9 is a view for explaining the first access circuit of FIG. 4, FIG. 10 is a view for explaining the second access circuit of FIG. 4 And FIG. 11 is a diagram for explaining the buffer control circuit of FIG. 12 is a diagram for explaining a function of a dynamic memory for providing continuous row and column data according to an embodiment of the present invention.

4, a dynamic memory (hereinafter referred to as a dynamic memory) that provides continuous row and column data includes a memory array 100, a first access circuit 220, a first word line decoder 240, A first sense amplifier 260, a second access circuit 320, a second word line decoder 340, a second sense amplifier 360, a buffer control circuit 420 and a buffer 440.

The memory array 100 is formed by stacking a plurality of layers in which a plurality of memory cells 110 are arranged in a matrix. As shown in FIG. 5, the memory cell 110 includes a capacitor 112, a first transistor 114, and a second transistor 116.

The dynamic memory stores the data via the capacitor 112. That is, the capacitor 112 stores data having a column address or data having a column address.

The first transistor 114 detects data having a column address stored in the capacitor 112 when a control signal is applied through the first word line 520. The first transistor 114 outputs the data having the detected column address to the first bit line 620. To this end, the first transistor 114 is connected to the first word line 520 at the gate end, the source terminal is connected to the capacitor 112, and the drain terminal is connected to the first bit line 620. The first transistor 114 detects data having a column address from the capacitor 112 connected to the source terminal when a control signal is applied through the gate terminal. The first transistor 114 outputs the data having the column address detected through the source terminal to the first bit line 620 through the drain terminal.

The second transistor 116 detects data having a column address stored in the capacitor 112 when a control signal is applied through the second word line 540. The second transistor 116 outputs the data having the detected column address to the second bit line 640. To this end, the second transistor 116 is connected to the second word line 540 at the gate end, the source end is connected to the capacitor 112, and the drain end is connected to the second bit line 640. The second transistor 116 detects data having a column address from the capacitor 112 connected to the source terminal when a control signal is applied through the gate terminal. The second transistor 116 outputs the data having the column address detected through the source terminal to the second bit line 640 through the drain terminal.

As shown in FIGS. 7 and 8, since the memory cell 110 constituting the conventional dynamic memory is composed of one transistor, only one of the data having the column address or the data having the column address Access is possible.

However, since the memory cell 110 constituting the dynamic memory according to the embodiment of the present invention is composed of two transistors, all of data having a column address and data having a column address can be continuously accessed. That is, the first transistor 114 and the second transistor 116 are activated respectively by a control signal for data access having a column address and a control signal for data access having a column address to generate data having a column address And data having a column address can all be accessed consecutively.

The first access circuit 220 accesses the memory array 100 based on the column address based on a control signal input for data access. That is, when the row access control signal is input, the first access circuit 220 is activated and applies the control signal to the first word line decoder 240.

The first access circuit 220 is represented by a logic circuit as shown in FIG. That is, the first access circuit 220 is configured by a logical product circuit of a CAS (Column Access Strobe) signal value, a WE (Write Enable) signal value, and an Idle signal value and a NOT value of a RAS (Row Access Strobe) do. The first access circuit 220 is activated based on the CAS signal value, the WE signal value, the Idle signal value, and the RAS signal value included in the row access control signal to apply the access address to the first word line decoder 240 . For example, when a row access control signal of 0111 (RAS = 0, CAS = 1, WE = 1, Idle = 1) is input for data access having a column address, the first access circuit 220 is activated Address to the first word line decoder 240.

The first word line decoder 240 applies a control signal to the memory cell 110 of the row address based on the access address applied through the first access circuit 220. That is, the first word line decoder 240 applies a control signal to the first transistor 114 of the memory cell 110 corresponding to the access address applied from the first access circuit 220.

The first sense amplifier 260 receives the row data through the first bit line 620. That is, the memory cell 110 (i.e., the memory cell 110 corresponding to the access address) activated by the control signal applied by the first word line decoder 240. The first sense amplifier 260 outputs the received column data to the buffer 440.

The second access circuit 320 accesses the memory array 100 based on the column address based on a control signal input for data access having a column address. That is, the second access circuit 320 is activated when a column access control signal is input, and applies a control signal to the second word line decoder 340.

The second access circuit 320 is represented by a logic circuit as shown in FIG. That is, the second access circuit 320 comprises a logical product circuit of the RAS signal value, the WE signal value, and the Idle signal value and the NOT value of the CAS signal. And activates the access address based on the CAS signal value, the WE signal value, the Idle signal value, and the RAS signal value included in the column access control signal to apply the access address to the second word line decoder 340. For example, if a column access control signal of 1011 (RAS = 1, CAS = 0, WE = 1, Idle = 1) is input for data access with a column address, the second access circuit 320 is activated Address to the second word line decoder 340.

The second word line decoder 340 applies a control signal to the memory cell 110 of the column address based on the access address applied through the second access circuit 320. That is, the second word line decoder 340 applies a control signal to the second transistor 116 of the memory cell 110 corresponding to the access address applied from the second access circuit 320.

The second sense amplifier 360 receives the column data through the second bit line 640. That is, column column data is received from the memory cell 110 (i.e., the memory cell 110 corresponding to the access address) activated by the control signal applied by the second word line decoder 340. The second sense amplifier 360 outputs the received column data to the buffer 440.

The buffer control circuit 420 controls the operation of the buffer 440 in accordance with an applied control signal. That is, the buffer control circuit 420 controls the operation of the buffer 440 such as reading / writing of the row data in the buffer 440 and reading / writing of the column data in response to the applied control signal.

The buffer control circuit 420 is expressed by a logic circuit as shown in FIG. That is, the buffer control circuit 420 determines the logical product of the NOT value of the RAS signal and the Idle signal and the CAS signal value, and the logical product of the NOT value of the CAS signal and the Idle signal and the RAS signal value Set the column or column data based on the result. The buffer control circuit 420 controls the write operation or the read operation of the buffer 440 based on the WE (Write Enable) signal.

The buffer 440 performs a read operation on the column data output from the first sense amplifier 260 or a write operation on the column data input from the outside by the control of the buffer control circuit 420, And performs a read operation on the column data output from the amplifier 360 or a write operation on the column data input from the outside. At this time, when the buffer 440 is operated in the read mode under the control of the buffer control circuit 420, the buffer 440 outputs the column data outputted from the first sense amplifier 260 or the column data outputted from the second sense amplifier 360 . When the buffer 440 operates in the write mode under the control of the buffer control circuit 420, the buffer 440 receives the column data or column data to be temporarily stored.

On the other hand, in the description of the dynamic memory that provides data of the continuous row and column, the control signal used for the control of the operation of the buffer 440 and the activation of the memory cell 110, same. 12, the dynamic memory providing continuous row and column data includes all the functions of the existing dynamic memory (DRAM), and since the signals of the added functions are not overlapped with the existing signals, it is confirmed that the DRAM is compatible with the existing DRAM .

As described above, the dynamic memory that provides the continuous row and column data has the effect of increasing the efficiency of continuous column data access. That is, the dynamic memory that provides continuous row and column data activates a memory cell having the same column address by the RAS signal, and activates the memory cell having the same column address by the CAS signal. Thus, the bank activated in the RAS signal may be accessed by the CAS to generate data having the same column address, and the bank activated in the CAS signal may be accessed by the RAS to generate data having the same column address .

In addition, the dynamic memory providing continuous row and column data maintains all the functions of the existing DRAM, is compatible with the JEDEC interface, and has an effect of increasing the efficiency of continuous column data access.

In addition, the dynamic memory providing continuous row and column data requires about 2.6% larger area than the conventional DRAM, but it has a memory bandwidth improvement of about 5.8% and a response speed of about 14.8% And power consumption is improved by about 4.4%.

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but many variations and modifications may be made without departing from the scope of the present invention. It will be understood that the invention may be practiced.

100: memory array 110: memory cell
112: capacitor 114: first transistor
116: second transistor 220: first access circuit
240: first word line decoder 260: first sense amplifier
320: second access circuit 340: second word line decoder
360: second sense amplifier 420: buffer control circuit
440: buffer 520: first word line
540: second word line 620: first bit line
640: second bit line

Claims (9)

A memory array in which a plurality of layers in which a plurality of memory cells are arranged in a matrix are stacked;
A first access circuit that is activated when a row column access control signal is input and outputs an access address;
A first word line decoder for activating a memory cell corresponding to an access address output from the first access circuit among a plurality of memory cells included in the memory array;
A first sense amplifier receiving and outputting the row data from the memory cell activated by the first word line decoder;
A second access circuit activated when a column access control signal is input to output an access address;
A second word line decoder for activating a memory cell corresponding to an access address output from the second access circuit among a plurality of memory cells included in the memory array;
A second sense amplifier receiving and outputting column data from a memory cell activated by the second word line decoder; And
And a buffer for storing the row data or the column data output from the first sense amplifier or the second sense amplifier and outputting the stored data to the outside,
The first access circuit comprising:
A CAS signal value, a WE signal value, an Idle signal value, and a RAS signal, which are composed of an AND circuit of a CAS signal value, a WE signal value, and an Idle signal value and a NOT value of the RAS signal, Value to provide the access address to the first word line decoder. ≪ Desc / Clms Page number 20 > The method according to claim 1,
The memory cell includes:
A capacitor for storing data having a column address or data having a column address;
A first transistor for detecting data having a column address stored in the capacitor when a control signal is applied through a first word line and outputting the detected data to a first bit line; And
And a second transistor for detecting data having a column address stored in the capacitor when the control signal is applied through the second word line and outputting the detected data to the second bit line. Dynamic memory. The method of claim 2,
Wherein the first transistor comprises:
A gate terminal connected to the first word line, a source terminal connected to the capacitor, a drain terminal connected to the first bit line,
Wherein when a control signal is applied through the gate terminal, data having a column address is detected from a capacitor connected to the source terminal, and the data is output to the first bit line through the drain terminal. Dynamic memory provided. The method of claim 2,
Wherein the second transistor comprises:
A gate terminal connected to the second word line, a source terminal connected to the capacitor, a drain terminal connected to the second bit line,
Wherein when a control signal is applied through the gate terminal, data having a column address is detected from a capacitor connected to the source terminal, and the data is output to a second bit line through the drain terminal. Dynamic memory provided. delete The method according to claim 1,
The second access circuit comprising:
WE signal value, Idle signal value and RAS signal value included in the column address access control signal, and a logical sum product of the RAS signal value, the WE signal value and the Idle signal value and the NOT value of the CAS signal, Value to apply the access address to the second word line decoder. ≪ Desc / Clms Page number 21 > The method according to claim 1,
And a buffer control circuit for controlling the operation of the buffer including at least one of reading or writing the column data based on the control signal or reading or writing the column data. Dynamic memory that provides data. The method of claim 7,
The buffer control circuit includes:
Based on the result of the logical product of the NOT value of the RAS signal and the Idle signal and the CAS signal value and the logical product of the NOT value of the CAS signal and the Idle signal and the RAS signal value, And sets the column data. The dynamic memory provides continuous row and column data. The method of claim 8,
The buffer control circuit includes:
Wherein the write operation or the read operation of the buffer is controlled based on a WE (Write Enable) signal.
KR1020160023407A 2016-02-26 2016-02-26 Dram for providing successive row and column data KR101736884B1 (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11568920B2 (en) 2017-08-02 2023-01-31 Samsung Electronics Co., Ltd. Dual row-column major dram

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11568920B2 (en) 2017-08-02 2023-01-31 Samsung Electronics Co., Ltd. Dual row-column major dram

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