KR101735074B1 - Layout of line connection to sense amplifier - Google Patents

Abstract

The present invention relates to a wiring connection layout of a sense amplifier. The sense amplifier wiring layout of the present invention includes a first active region and a second active region disposed on a substrate; A plurality of bit lines extending across the first and second active regions and extending in a first direction; A gate connection bit line disposed so as not to overlap the first and second active areas; A pickup pad spaced apart from the gate connection bit line in a first direction and being in contact with the first active area; And a gate line disposed across the second active region and in contact with the gate connection bit line. According to the present invention, it is possible to provide a semiconductor device in which the pitch of the sense amplifiers is reduced without reducing the pitch of the bit lines by changing the arrangement of the pickup pads. Therefore, the semiconductor device can be integrated even by patterning without reducing the pitch of the bit lines.

Description

LAYOUT OF LINE CONNECTION TO SENSE AMPLIFIER < RTI ID = 0.0 >

The present invention relates to a semiconductor device, and more particularly to a wiring connection layout of a sense amplifier.

Among semiconductor devices, a DRAM device senses and amplifies data stored in a memory cell using a sense amplifier.

As the density of such DRAMs increases, the number and pitch of bit lines are being evaluated as a major factor in the sense amplifier pitch limit.

The sense amplifier operates in conjunction with the bit line of the memory cell to sense and amplify the data stored in the memory cell and is generally operated as a maintenance bit line (amplification bit line) and a sub bit line (reference bit line of the maintenance trace) A wiring structure is formed. For example, in the case of a two-stage sense amplifier, a plurality of memory cells arranged in a matrix form are connected to a first cell block by a maintenance trace, and are connected by a second cell block and a sub-bit line. Thus, the sense amplifier is accompanied by a maintenance trace and a sub-bit line connection, and the minimum pitch of the sense amplifier is related to the placement of the bit line.

This will be described with reference to the drawings.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic diagram for explaining a wiring design of a conventional semiconductor device, illustrating a bit line arrangement of a two-stage sense amplifier disposed between cell blocks. FIG. For convenience of explanation, the cell block and the sense amplifier are briefly shown, and reference numerals such as positive and negative bit lines refer to the operation of the first cell block.

Referring to FIG. 1, a first cell block, a first sense amplifier 101A, a second sense amplifier 101B, and a second cell block are disposed in a first direction.

The cell block is a simplified representation of a memory cell matrix, in which the cell block and the sense amplifier are connected by a bit line. In this figure, two bit lines for the first and second cell blocks are connected to the first sense amplifier 101A and the second sense amplifier 101B, respectively. For example, the first cell block is connected to the first sense amplifier 101A and the second sense amplifier 101B respectively by the first maintenance trains and the second maintenance trains, And connected to the first sense amplifier 101A and the second sense amplifier 101B by the bit line and the second sub bit line, respectively.

In the conventional bit line connection structure of the two-stage sense amplifier shown in the figure, three bit lines are arranged side by side in the second direction for each sense amplifier, and the pitch of the bit lines arranged side by side is determined This can be a major factor in determining the overall patch of the amplifier.

FIG. 2 is an enlarged view of a sense amplifier 101A as a layout for explaining the bit line arrangement between the conventional two-stage sense amplifier and the cell block shown in FIG.

Referring to FIG. 2 and FIG. 1, a plurality of bit lines are connected to a cell block. Illustratively, in FIG. 1 and FIG. 2, two bit lines are connected to each cell block. In particular, Three bit lines BL1, BL2, BL3 crossing the amplifier 101A are illustrated.

Referring to FIG. 2, a first active region 12 and a second active region 11 are formed on a substrate in a second direction. The active region is an area where a pickup pad or a MOS transistor can be formed, and the active region can be insulated with an insulating film.

Here, the second active region 11 is a region where a MOS transistor is formed, and a MOS transistor constituting a sense amplifier is formed in the second active region 11. For this purpose, a second active region 11 Drain junctions (not shown) and the gate lines 15 are disposed in the source / drain regions 11.

The bit lines BL1, BL2 and BL3 are arranged at regular intervals according to the related design rule in the first direction.

Here, the bit lines BL1 and BL2 are disposed across the first and second active regions 12 and 11, and the bit line BL3 is connected to the first active region 12, (12) and is connected to the gate line (15) through the contact (16). Further, bit lines corresponding to the bit lines BL1, BL2, and BL3 are symmetrically disposed in the second direction in the pickup pad 13, and in FIG. 2, only BLx is illustrated as an example.

According to the prior art, the pickup pads were disposed in the empty space between the bit lines for efficient space allocation, because there was no space available for the pickup pads needed to supply power to the sense amplifiers. In particular, as described above, the clearance formed by placing the contact 16 connecting the bit line BL3 in the first direction with the bit line BL3 in the first direction in the bit line, that is, the bit line BL3, The bit line BL3 is arranged in the second direction and the pickup pad 13 is arranged in the second direction. The pickup pad 13 is connected to the first active region 12 by the contact 14 and the other bit line BLx is arranged symmetrically with respect to the pickup pad 13. [

That is, in the conventional design, the pickup pad 13 is disposed in parallel with the bit line BL3 as shown in FIG.

However, according to this conventional technique, the minimum pitch of the sense amplifiers 101A and 101B is considered up to the pitch L4 of the pickup pad 13 to determine the total pitch L1 + L2 + L3 + L4. That is, the minimum pitches of the sense amplifiers 101A and 101B are determined considering not only the pitch L1 + L2 + L3 of the bit lines BL1, BL2 and BL3, but also the pitch L4 of the pickup pad 13, There is a problem in terms of space efficiency. This is an obstacle to the integration of the semiconductor device. In particular, considering the fact that it is difficult to minimize the linewidths of the individual bit lines BL1, BL2 and BL3 due to the increase in the patterning difficulty of the bit lines, a new bit line design is required to reduce the minimum pitch of the sense amplifiers do.

The present invention provides a semiconductor device with a sense amplifier wiring layout capable of reducing the minimum pitch of a sense amplifier while maintaining the pitch of a bit line at a current level for integration of semiconductor devices .

According to an aspect of the present invention, there is provided a semiconductor device of a sense amplifier wiring layout, comprising: a first active region spaced apart from a first direction and extending in a second direction substantially perpendicular to the first direction, A second active region; A plurality of bit lines extending in the first direction and crossing the first and second active regions, the bit lines being spaced apart from each other in the second direction; A gate connection bit line disposed so as not to overlap the first and second active areas; A pickup pad spaced apart from the gate connection bit line across the first active area and in the first direction, the pickup pad being in contact with the first active area; And a gate line disposed on the second active region and spaced apart from the gate connection bit line through the pick-up pad, the gate line bypassing the pick-up pad to be in contact with the gate connection bit line .

According to the present invention, it is possible to provide a semiconductor device in which the pitch of the sense amplifiers is reduced without reducing the pitch of the bit lines by changing the arrangement of the pickup pads. Therefore, the semiconductor device can be integrated even by patterning without reducing the pitch of the bit lines.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic view for explaining a bit line wiring arrangement between a conventional two-stage sense amplifier and a cell block; FIG.
2 is a layout for explaining bit line wiring arrangement between a conventional two-stage sense amplifier and a cell block
3 is a wiring layout of a sense amplifier according to an embodiment of the present invention;

Hereinafter, the most preferred embodiment of the present invention will be described. In the drawings, the thickness and the spacing are shown for convenience of explanation only, and may be exaggerated relative to the actual physical thickness. In describing the present invention, known configurations irrespective of the gist of the present invention may be omitted. It should be noted that, in the case of adding the reference numerals to the constituent elements of the drawings, the same constituent elements have the same number as possible even if they are displayed on different drawings.

3 is a wiring layout of a sense amplifier according to an embodiment of the present invention.

Generally, the wiring design of the sense amplifiers varies according to the associated design, but includes a bit line that is directly contacted and connected to the gate of a MOS transistor of the sense amplifier, and a pickup pad is disposed near the portion to be contacted with the gate The configuration is common. Therefore, for ease of understanding of the present invention, an embodiment of the present invention will be described by taking a two-stage sense amplifier as an example in FIG. 1 as an example. Three bit line wirings BL1, BL2 and BL3 are exemplified, of which the bit line BL3 is exemplified by a gate connection bit line BL3 which is in contact with the gate. Here, the bit lines BL1, BL2, and BL3 may be bit lines corresponding to any one of the bit lines illustrated in FIG. 1, depending on the related design. It should be noted, however, that the technical spirit of the present invention is not limited to those exemplified in this specification.

Referring to FIG. 3, a layout of a sense amplifier according to an embodiment of the present invention includes a first active region 22 and a second active region 21 disposed on a substrate; A plurality of bit lines (BL1, BL2) extending across the first and second active regions (22, 21) and extending in a first direction; A gate connection bit line BL3 disposed so as not to overlap with the first and second active regions 22 and 21; A pickup pad (23) spaced apart from the gate connection bit line (BL3) in a first direction and being in contact with the first active region; And a gate line (25) disposed across the second active region and in contact with the gate connection bit line (BL3).

On the other hand, the other bit lines are arranged symmetrically with respect to the pickup pad 23. That is, on the right side of the pickup pad 23, bit lines corresponding to the bit lines BL1, BL2, and BL3 are symmetrically disposed. In Fig. 3, for example, only the bit line BLx corresponding to the gate connection bit line BL3 is shown.

Here, the bit lines BL1 and BL2 and the gate connection bit line BL3 are arranged at regular intervals in the second direction. Here, the predetermined interval is determined according to the related design rule.

Here, the bit lines BL1 and BL2 are arranged across the first and second active regions 22 and 21, and the gate connection bit line BL3 is arranged so as not to cross the first active region 22. Then, the gate connection bit line BL3 is connected to the gate line 25 through the contact 26 instead of the short arrangement.

In addition, the pickup pads 23 are disposed apart from the gate connection bit line BL3 in the first direction. Accordingly, the pickup pad 23 is spaced apart from the contact 26 connecting the gate connection bit line BL3 and the gate line 25 in the first direction.

The layout according to the embodiment of the present invention described above and the layout of FIG. 2 according to the prior art are compared as follows.

As described above, the pickup pads must be disposed in the vicinity of the relatively short bit lines for effective spatial arrangement of the pickup pads for supplying the bias. That is, the pick-up pad 23 should be efficiently arranged so as not to affect the pitch increase of the sense amplifier. 2, the pickup pad 13 is disposed in parallel with the gate connection bit line BL3 in the second direction. Accordingly, the pitch L4 of the pickup pad 13 Space is wasted by being included in the pitch. That is, the minimum pitch of the sense amplifiers according to the prior art was "L1 + L2 + L3 + L4 ", and the pitch L4 due to the arrangement of the pickup pads 13 had to be included.

3, in order to remove the pitch L4 according to the prior art, the pickup pad 23 is moved from the gate connection bit line BL3 in the first direction Respectively. The gate connection bit line BL3 is arranged so as not to cross the first active region 22 for the arrangement of the pickup pads 23. [

As a result, considering the pitch L3 'to the bit line BLx corresponding to the gate connection bit line BL3, the minimum pitch of the sense amplifier according to an embodiment of the present invention is "L1 + L2 + Quot ;, the pitch of the pickup pads 23 is eliminated, and the efficiency of the space can be secured.

Therefore, according to the wiring layout of the sense amplifier according to the embodiment of the present invention, since the pitch of the pickup pads 23 does not affect the pitch of the sense amplifiers, the minimum pitch of the sense amplifiers can be reduced. Further, according to the embodiment of the present invention, it is possible to achieve the object of integrating the semiconductor device without reducing the line width of the bit line.

11: second active region 12: first active region
13: Pickup pad 14: Contact
15: gate line 16: contact

Claims (3)

A first active region and a second active region spaced from each other in a first direction and extending in a second direction substantially perpendicular to the first direction and disposed on the substrate;
A plurality of bit lines extending in the first direction and spaced apart from each other in the second direction across the first and second active regions;
A gate connection bit line disposed so as not to overlap the first and second active areas;
A pickup pad spaced apart from the gate connection bit line across the first active area and in the first direction, the pickup pad being in contact with the first active area; And
And a gate line disposed on the second active region and spaced apart from the gate connection bit line with the pickup pad therebetween, the gate line bypassing the pickup pad to be in contact with the gate connection bit line
A semiconductor device in a sense amplifier wiring layout.
delete Claim 3 has been abandoned due to the setting registration fee. The method according to claim 1,
Wherein the gate line is overlapped with the plurality of bit lines
A semiconductor device in a sense amplifier wiring layout.

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