KR101731048B1 - Liquid crystal display device and manufacturing method thereof - Google Patents

Abstract

A liquid crystal display device is provided. A liquid crystal display according to an embodiment of the present invention includes a substrate, a thin film transistor disposed on the substrate, a pixel electrode connected to one terminal of the thin film transistor, a liquid crystal layer disposed on the pixel electrode, And a capping layer disposed on the support member and covering the liquid crystal injection port, wherein the capping layer is disposed on the common electrode, the capping layer covering the liquid injection port, And an alignment material aggregation preventing portion is formed at the edge portion.

Description

TECHNICAL FIELD [0001] The present invention relates to a liquid crystal display (LCD)

The present invention relates to a liquid crystal display device and a manufacturing method thereof.

The liquid crystal display device is one of the most widely used flat panel display devices and is composed of two display panels having an electric field generating electrode such as a pixel electrode and a common electrode and a liquid crystal layer interposed therebetween.

A voltage is applied to the electric field generating electrode to generate an electric field in the liquid crystal layer, thereby determining the orientation of the liquid crystal molecules in the liquid crystal layer and controlling the polarization of the incident light to display an image.

An NCD (Nano Crystal Display) liquid crystal display device is a device for forming a display by forming a sacrificial layer with an organic material, forming a support member on an upper part, removing a sacrificial layer, and filling an empty space formed by sacrificial layer removal with liquid crystal.

A manufacturing method of an NCD (Nano Crystal Display) liquid crystal display device includes a step of injecting an orientation liquid and drying the liquid crystal before aligning and orienting the liquid crystal molecules. The solid component of the alignment liquid is aggregated during the drying of the alignment liquid, resulting in problems such as light leakage or reduced transmittance.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a liquid crystal display device and a method of manufacturing the same that can minimize the aggregation of solids in an alignment liquid.

A liquid crystal display according to an embodiment of the present invention includes a substrate, a thin film transistor disposed on the substrate, a pixel electrode connected to one terminal of the thin film transistor, and a supporting member facing the pixel electrode, A microcavity layer having a liquid crystal injection hole is formed between the electrode and the supporting member, and an alignment material aggregation preventing portion is formed at an edge portion of the micropneumatic layer.

The thin film transistor may further include a protection layer disposed between the micro-space layer and the protection layer at the edge of the micro-space layer, and the trench may be the alignment material aggregation prevention portion.

An open portion is formed between the micro space layers, the support member covers the open portion, and the trench may be formed at an edge portion of the micro space layer adjacent to the open portion.

An organic film disposed on the substrate, and a light shielding member positioned between the organic films, wherein the trench can be positioned to correspond to a portion where the organic film overlaps with the light shielding member.

The open portion extends in a direction parallel to a signal line connected to one terminal of the thin film transistor, and the trench can be extended in a direction in which the open portion extends.

A liquid crystal material may be injected into the micro-space layer to form a liquid crystal layer, and the width of the trench may be less than a cell gap of the liquid crystal layer.

And a capping layer located on the support member and covering the liquid crystal injection port. The capping layer may cover the groove. The capping layer may cover the groove.

The trench may be formed at both edge portions of the micro-space layer, and a storage trench connecting the trench may be formed in the protective film.

A groove may be formed between the micro-space layers, and the storage trench may be located along the groove.

The grooves may be filled with the capping film.

An open portion is formed between the micro space layers, and the support member covers the open portion to form a side wall portion of the micro space layer.

Wherein an edge portion of the micro-space layer contacting the side wall portion of the micro-space layer is elongated along a direction in which the open portion extends, an edge portion of the micro-space layer forms a non-linear portion, It may be an anti-agglomeration prevention part.

The non-linear portion of the micro-space layer may have a zigzag shape.

A liquid crystal material is injected into the micro-space layer to form a liquid crystal layer, and a pitch of the repetitive shape of the non-linear portion may be equal to or less than a cell gap of the liquid crystal layer.

And an alignment layer covering the pixel electrode in the micro space layer.

And a common electrode disposed on the micro-space layer.

A method of manufacturing a liquid crystal display according to an embodiment of the present invention includes forming a thin film transistor on a substrate, forming a pixel electrode on the thin film transistor, forming a sacrificial layer on the pixel electrode, Forming an alignment layer on the inner wall of the micro-space layer, injecting a liquid crystal material into the micro-space layer, and removing the sacrificial layer, And forming a capping film on the supporting member so as to cover the liquid crystal injection hole, wherein an alignment material aggregation preventing portion is formed at an edge portion of the micro space layer.

Forming a protective film on the thin film transistor, wherein the protective film forms a trench at an edge portion of the micro space layer, and the trench is formed to prevent the alignment material from being aggregated.

And forming an open portion by patterning the sacrificial layer, wherein the trench can be formed at an edge portion of the micro space layer adjacent to the open portion.

Forming an organic film on the substrate; and forming a light shielding member between the organic films. The trench may be formed to correspond to a portion where the organic film and the light shielding member overlap each other.

The open portion may extend in a direction parallel to a signal line connected to one terminal of the thin film transistor, and the trench may extend in the same direction as the open portion.

The micro-space layer into which the liquid crystal material is injected may include a liquid crystal layer, and the width of the trench may be less than a cell gap of the liquid crystal layer.

And forming a groove by patterning the support member, wherein the groove can be formed between the adjacent micro-space layers in the direction in which the open portion extends.

Forming the trenches at both edge portions of the micro-space layer, and forming a storage trench connecting the trenches in the protective film.

And forming a groove by patterning the support member, wherein the storage trench is formed to be positioned along the groove.

Forming an open portion between the micro-space layers by patterning the sacrificial layer, and patterning the sacrificial layer to form a concavo-convex portion at an edge portion of the sacrificial layer, wherein the concavo- .

The micro-space layer into which the liquid crystal material is injected may include a liquid crystal layer, and the pitch of the concave-convex portion may be less than a cell gap of the liquid crystal layer.

And forming the sidewall portion of the micro space layer while the support member covers the open portion.

The edge portion of the micro-space layer contacting the side wall portion of the micro-space layer may be formed to extend along the extending direction of the open portion, and the concave-convex portion may be formed at an edge portion of the micro-space layer.

And forming a common electrode on the sacrificial layer.

As described above, according to the embodiment of the present invention, the trench is formed at the edge portion of the micro space layer or the non-linear shape of the edge portion of the micro space layer is formed. Accordingly, the solid portion of the alignment liquid is collected in the trench or the non-linear pattern portion, so that the light leakage phenomenon or the transmittance drop phenomenon can be minimized.

1 is a plan view showing a liquid crystal display according to an embodiment of the present invention.
FIG. 2 is a plan view schematically illustrating the arrangement of trenches according to an embodiment of the present invention in FIG.
3 is a cross-sectional view taken along line III-III in FIG.
4 is a cross-sectional view taken along line IV-IV in Fig.
5 is a perspective view illustrating a micro-space layer according to one embodiment of the present invention.
6 to 12 are cross-sectional views illustrating a method of manufacturing a liquid crystal display device according to an embodiment of the present invention.
13 is a plan view showing a liquid crystal display device according to an embodiment of the present invention.
14 is a cross-sectional view taken along line XIV-XIV in Fig.
15 to 21 are cross-sectional views illustrating a method of manufacturing a liquid crystal display device according to an embodiment of the present invention.
22 is a plan view schematically illustrating the shape of the micro-space layer according to an embodiment of the present invention.
23 is a cross-sectional view taken along line XXIII-XXIII in FIG. 22. FIG.
24 is a schematic view showing a non-linear portion of a micro-space layer according to an embodiment of the present invention.
25 to 31 are a plan view and a cross-sectional view illustrating a method of manufacturing a liquid crystal display device according to an embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. However, the present invention is not limited to the embodiments described herein but may be embodied in other forms. Rather, the embodiments disclosed herein are provided so that the disclosure can be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.

In the drawings, the thicknesses of layers and regions are exaggerated for clarity. Also, when a layer is referred to as being "on" another layer or substrate, it may be formed directly on another layer or substrate, or a third layer may be interposed therebetween. Like numbers refer to like elements throughout the specification.

1 is a plan view showing a liquid crystal display according to an embodiment of the present invention. FIG. 2 is a plan view schematically illustrating the arrangement of trenches according to an embodiment of the present invention in FIG. 3 is a cross-sectional view taken along line III-III in FIG. 4 is a cross-sectional view taken along line IV-IV in Fig. 5 is a perspective view illustrating a micro-space layer according to one embodiment of the present invention.

Referring to FIGS. 1, 3 and 4, thin film transistors Qa, Qb, Qc are located on a substrate 110 made of transparent glass or plastic.

The organic film 230 may be disposed on the thin film transistors Qa, Qb, and Qc and the light shielding member 220 may be formed between the neighboring organic films 230. [ Here, the organic film 230 may be a color filter.

FIGS. 3 and 4 are cross-sectional views taken along the cutting line III-III and the cutting line IV-IV. In FIGS. 3 and 4, the structure between the substrate 110 and the organic film 230 shown in FIG. 1 is omitted. 3 and 4 include part of the thin film transistors Qa, Qb and Qc between the substrate 110 and the organic film 230. In this case,

The organic film 230 may extend along the column direction of the pixel electrode 191. The organic film 230 may be a color filter, and the color filter 230 may display one of primary colors such as red, green, and blue. However, it is not limited to the three primary colors of red, green, and blue, and one of cyan, magenta, yellow, and white colors may be displayed.

The neighboring organic films 230 may be spaced along the transverse direction D shown in FIG. 1 and the longitudinal direction intersecting with the transverse direction D shown in FIG. In FIG. 3, organic films 230 are shown separated from one another along the transverse direction D, and FIG. 4 shows organic films 230 spaced from each other along the longitudinal direction.

Referring to FIG. 3, a longitudinal light shielding member 220b is disposed between the organic films 230 spaced along the lateral direction D. The vertical shielding member 220b overlaps the edge of each of the neighboring organic films 230 and the width at which the vertical shielding member 220b overlaps with both edges of the organic film 230 is substantially the same.

Referring to FIG. 4, the transverse light shielding member 220a is positioned between the organic films 230 spaced along the longitudinal direction. The transverse light shielding member 220a overlaps the edge of each of the neighboring organic films 230 and the width of the transverse light shielding member 220a overlapping both edges of the organic film 230 is substantially the same.

The lower protective film 170 and the upper protective film 180 are located on the organic film 230 and the light shielding member 220. The lower protective film 170 may be formed of an organic material and may serve to planarize the films formed thereunder. The upper protective film 180 may be formed of an inorganic material such as silicon oxide or silicon nitride. The upper protective film 180 may be omitted.

The pixel electrode 191 is positioned on the upper protective layer 180 and the pixel electrode 191 is electrically connected to one terminal of the thin film transistors Qa and Qb through the contact holes 185a and 185b.

A lower alignment layer 11 may be formed on the pixel electrode 191 and a lower alignment layer 11 may be a vertical alignment layer. The lower alignment layer 11 may include at least one material commonly used as a liquid crystal alignment layer such as polyamic acid, polysiloxane, or polyimide.

On the lower alignment layer 11, a micro-space layer 400 is positioned. A liquid crystal material containing liquid crystal molecules 310 is injected into the micro space layer 400 and the liquid space injection port A is formed in the micro space layer 400. The fine space layer 400 may be formed along the column direction, that is, along the longitudinal direction of the pixel electrode 191. In this embodiment, the liquid crystal material including the alignment material forming the alignment films 11 and 21 and the liquid crystal molecules 310 may be injected into the micro-space layer 400 using a capillary force.

In this embodiment, as shown in FIGS. 2 and 3, an open portion OPN is formed between the adjacent micro space layers 400 in the transverse direction, and the micro space layer 400 adjacent to the open portion OPN The trenches SP may be formed at both edge portions of the trenches SP. The trench SP may be formed on a portion where the organic film 230 and the vertical shielding member 220b overlap with each other. The first width w1 of the trench SP formed at the edge of the micro space layer 400 is preferably less than or equal to the cell gap of the liquid crystal layer in which the liquid crystal material including the liquid crystal molecules 310 is formed. The space between adjacent short sides of the rectangular pixel electrodes 191a and 191b may be referred to as an inlet portion EP so as to include a region where the liquid crystal injection hole A of the micro space layer 400 is formed. The entrance portion EP may be substantially the same width as the lateral light shielding member 220a.

The trench SP is elongated along the longitudinal direction of the micro space layer 400 and the first length L1 corresponding to the length of the trench SP protruding from the inlet EP is parallel to the length of the inlet EP. Width can be adjusted.

Although the trenches SP are separated in the entrance part EP in FIG. 2, they can be formed continuously in the vertical direction without being separated in one pixel PX.

The cell gap of the liquid crystal layer may be 2um or more and 10um or less.

In the course of manufacturing a liquid crystal display device, not only a liquid crystal material is injected through the liquid crystal injection hole (A) but also an alignment material in which solid and solvent are mixed before liquid crystal injection can be injected. After the orientation material is injected, the drying process is carried out. At this time, the solid content remaining as the solvent contained in the alignment liquid is volatilized is accumulated in the microporous layer 400. In particular, when drying is started simultaneously at both the liquid crystal injection ports A and the drying is progressed to the central portion of the micropipolar layer 400, a huddle defect in which the solid components are accumulated may occur in the central portion of the micropipolar layer 400 have. Or when the drying is started at one of the liquid crystal injection ports (A), the solid content may be aggregated at the other liquid crystal injection port (A) of the fine space layer (400). When the solid content is aggregated in the fine space layer 400, defective display such as light leakage phenomenon or reduced transmittance occurs.

If the trench SP is formed at the edge portion of the micro space layer 400 as in the present embodiment, the alignment liquid is injected along the liquid crystal inlet A of the micro space layer 400 and dried, The phenomenon of aggregation in the liquid crystal inlet (A) is reduced, and light leakage phenomenon is minimized. When the width w1 of the trench SP is less than the cell gap of the liquid crystal layer, the capillary force of the trench SP structure is higher than the capillary force of the micro space layer 400, so that the remaining solid portion can be led to the trench SP have. As a result, the solid component remaining after drying spreads over the trench (SP), so that the solid components can be prevented from being aggregated.

In this embodiment, one liquid crystal injection port is formed on each of both edges of one micro-space layer 400, but in another embodiment, only one liquid crystal injection port may be formed on one edge of one micro-space layer 400 have.

The upper alignment layer 21 is located on the micro space layer 400 and the common electrode 270 and the first cover layer 250 are positioned on the upper alignment layer 21. The common electrode 270 receives a common voltage and generates an electric field together with the pixel electrode 191 to which the data voltage is applied so that the liquid crystal molecules 310 located in the fine space layer 400 between the two electrodes are tilted . The common electrode 270 and the pixel electrode 191 form a capacitor to maintain the applied voltage even after the TFT is turned off. The first cover film 250 may be formed of silicon nitride (SiNx) or silicon oxide (SiO2).

A supporting member 260 is placed on the first cover film 250. The support member 260 may comprise silicon oxycarbide (SiOC) or photoresist or other organic material. When the support member 260 includes silicon oxycarbide (SiOC), the support member 260 may be formed by a chemical vapor deposition method. When the support member 260 includes a photoresist, a coating method may be used. Silicon oxycarbide (SiOC) has a high transmittance in a film which can be formed by a chemical vapor deposition method, and has a merit in that the film stress is small and the film is not deformed. Therefore, in this embodiment, the support member 260 is made of silicon oxycarbide (SiOC), so that light can be transmitted well and a stable film can be formed.

A groove GRV penetrating the fine space layer 400, the upper alignment layer 21, the common electrode 270, the first cover layer 250, and the support member 260 is formed on the horizontal shielding member 220a .

Hereinafter, the fine space layer 400 will be described in detail with reference to FIGS. 1, 3 to 5.

1, 3 to 5, the fine space layer 400 is divided by a plurality of grooves (GRV) located at portions overlapping the gate lines 121a, and the gate lines 121a extend Are formed along the direction (D). Each of the plurality of micro-space layers 400 may correspond to a pixel region, and a plurality of groups of the plurality of micro-space layers 400 are formed in a column direction. Here, the pixel region may correspond to an area for displaying a screen.

In this embodiment, the two sub-pixel electrodes 191a and 191b have a thin film transistor and a pixel electrode structure in which the gate line 121 is interposed therebetween. Accordingly, in the micro-spatial layer 400, the first sub-pixel electrode 191a and the second sub-pixel electrode 191b, each having a pixel PX adjacent thereto in the longitudinal direction, correspond to one micro-spatial layer 400 do. However, since such a structure can change the structure of the thin film transistor and the pixel electrode, it is also possible for the fine space layer 400 to be deformed into a corresponding shape in one pixel PX.

In this case, the groove GRV formed between the micro space layers 400 may be positioned along the direction D in which the gate line 121a extends, and the liquid crystal injection hole A of the micro space layer 400 may be formed in the groove (GRV) and the micro-spatial layer 400 are formed. The liquid crystal injection hole A is formed along the direction in which the groove GRV extends. The open portion OPN formed between the neighboring fine space layers 400 in the direction D in which the gate line 121a extends may be covered with the support member 260 as shown in FIG.

The liquid crystal injection hole A included in the micro space layer 400 may be positioned between the upper alignment film 21 and the horizontal light shielding member 220a or between the upper alignment film 21 and the lower alignment film 11. [

The grooves GRV are formed along the direction D in which the gate lines 121a extend in the present embodiment, but in another embodiment, the grooves GRV are formed in a plurality of directions along the extending direction of the data lines 171 And a plurality of groups of the plurality of micro-space layers 400 formed in the row direction can be formed. The liquid crystal injection hole A may be formed along the direction in which the groove GRV formed along the extending direction of the data line 171 extends.

The second cover film 240 is placed on the support member 260. The second cover membrane 240 may contact the top surface and the side wall of the support member 260. The second cover film 240 may be formed of silicon nitride (SiNx) or silicon oxide (SiO2). The capping layer 280 is located on the second cover layer 240. The capping layer 280 contacts the upper surface and sidewalls of the second cover layer 240 and the capping layer 280 covers the liquid crystal injection port A of the micro space layer 400 exposed by the groove GRV . The capping layer 280 may be formed of a thermosetting resin, silicon oxycarbide (SiOC), or graphene.

When the capping layer 280 is formed of graphene, the graphene has a strong resistance to gas including helium and the like, and thus can serve as a capping layer for blocking the liquid crystal injection port A, The liquid crystal material is not contaminated even when it is in contact with the liquid crystal material. In addition, Graphene can also protect the liquid crystal material against external oxygen and moisture.

In this embodiment, since the liquid crystal material is injected through the liquid crystal injection hole A of the micro space layer 400, the liquid crystal display device can be formed without forming an additional upper substrate.

An overcoat film (not shown) formed of an inorganic film or an organic film may be placed on the capping film 280. The overcoat film protects the liquid crystal molecules 310 injected into the fine space layer 400 from external impact and smoothes the film.

Hereinafter, the liquid crystal display according to the present embodiment will be described in detail with reference to FIGS. 1 to 4 again.

1 to 4, a plurality of gate lines 121a, a plurality of depression gate lines 121b, and a plurality of sustain electrode lines 131 are formed on a substrate 110 made of transparent glass or plastic, A gate conductor is formed.

The gate line 121a and the decompression gate line 121b extend mainly in the lateral direction and transmit gate signals. The gate line 121a includes a first gate electrode 124a and a second gate electrode 124b protruding upward and downward and the decompression gate line 121b includes a third gate electrode 124c protruding upward. The first gate electrode 124a and the second gate electrode 124b are connected to each other to form one protrusion.

The sustain electrode line 131 also extends in the lateral direction mainly and delivers a predetermined voltage such as the common voltage Vcom. The sustain electrode line 131 includes a sustain electrode 129 protruding upward and downward, a pair of vertical portions 134 extending downward substantially perpendicular to the gate line 121a, and a pair of vertical portions 134 And includes transverse portions 127 that connect to each other. The lateral portion 127 includes a downwardly extending capacitance electrode 137.

A gate insulating film (not shown) is formed on the gate conductors 121a, 121b, and 131.

A plurality of linear semiconductors (not shown), which can be made of amorphous or crystalline silicon, are formed on the gate insulating film. The linear semiconductor mainly includes first and second semiconductors 154a and 154b extending in the longitudinal direction and extending toward the first and second gate electrodes 124a and 124b and connected to each other and a third gate electrode 124c, And a third semiconductor 154c positioned on the second semiconductor layer 154c.

A plurality of pairs of resistive contact members (not shown) may be formed on the semiconductors 154a, 154b, and 154c. The resistive contact member may be made of a silicide or a material such as n + hydrogenated amorphous silicon which is heavily doped with n-type impurities.

A data conductor including a plurality of data lines 171, a plurality of first drain electrodes 175a, a plurality of second drain electrodes 175b, and a plurality of third drain electrodes 175c is formed on the resistive contact member have.

The data line 171 transmits the data signal and extends mainly in the vertical direction and crosses the gate line 121a and the decompression gate line 121b. Each data line 171 includes a first source electrode 173a and a second source electrode 173b extending toward the first gate electrode 124a and the second gate electrode 124b and connected to each other.

The first drain electrode 175a, the second drain electrode 175b, and the third drain electrode 175c include a wide one end portion and a rod-shaped other end portion. The rod-shaped end portions of the first drain electrode 175a and the second drain electrode 175b are partially surrounded by the first source electrode 173a and the second source electrode 173b. The wide one end of the first drain electrode 175a extends again to form a U-shaped third drain electrode 175c. The wide end portion 177c of the third source electrode 173c overlaps with the capacitor electrode 137 to form a reduced-pressure storage capacitor Cstd and the rod-end portion is partially surrounded by the third drain electrode 175c.

The first gate electrode 124a, the first source electrode 173a and the first drain electrode 175a together with the first semiconductor 154a form the first thin film transistor Qa and the second gate electrode 124b The second source electrode 173b and the second drain electrode 175b together with the second semiconductor 154b form the second thin film transistor Qb and the third gate electrode 124c, The second drain electrode 173c and the third drain electrode 175c together with the third semiconductor 154c form a third thin film transistor Qc.

The linear semiconductor including the first semiconductor 154a, the second semiconductor 154b and the third semiconductor 154c has a channel region between the source electrodes 173a, 173b and 173c and the drain electrodes 175a, 175b and 175c, 173a, 173b, 173c, 175a, 175b, and 175c, and the resistive contact member therebelow, with the exception of the data conductors 171, 173a, 173b, 173c, 175a, 175b, and 175c.

The first semiconductor 154a has a portion exposed between the first source electrode 173a and the first drain electrode 175a without being blocked by the first source electrode 173a and the first drain electrode 175a, The second semiconductor electrode 154b is exposed between the second source electrode 173b and the second drain electrode 175b without being blocked by the second source electrode 173b and the second drain electrode 175b, The semiconductor 154c is exposed between the third source electrode 173c and the third drain electrode 175c without being blocked by the third source electrode 173c and the third drain electrode 175c.

A lower protective film (not shown) which can be made of an inorganic insulating material such as silicon nitride or silicon oxide is formed on the data conductors 171, 173a, 173b, 173c, 175a, 175b, and 175c and exposed semiconductors 154a, 154b, Is formed.

An organic film 230 may be disposed on the lower protective film. The organic film 230 is located in most of the regions except where the first thin film transistor Qa, the second thin film transistor Qb, and the third thin film transistor Qc are located. However, it may also be elongated in the longitudinal direction along the interval between the neighboring data lines 171. The organic film 230 may be a color filter and the color filter 230 may be formed on the lower side of the pixel electrode 191 but may be formed on the common electrode 270.

The light shielding member 220 is located on a region where the organic film 230 is not located and on a part of the organic film 230. [ The light shielding member 220 extends up and down along the gate line 121a and the decompression gate line 121b and includes a first thin film transistor Qa, a second thin film transistor Qb and a third thin film transistor Qc And a vertical shielding member 220b extending along the data line 171. The horizontal shielding member 220a covers the area where the data line 171 is located.

The light shielding member 220 is also called a black matrix and blocks light leakage.

The lower protective film and the light shielding member 220 are formed with a plurality of contact holes 185a and 185b for exposing the first drain electrode 175a and the second drain electrode 175b.

A lower protective film 170 and an upper protective film 180 are formed on the organic film 230 and the light shielding member 220. A pixel electrode 191 including a first sub-pixel electrode 191a and a second sub-pixel electrode 191b is formed on the upper protective layer 180. [ The first sub-pixel electrode 191a and the second sub-pixel electrode 191b are separated from each other with the gate line 121a and the decompression gate line 121b interposed therebetween, and are arranged above and below each other and are adjacent to each other in the column direction. The size of the second sub-pixel electrode 191b may be greater than the size of the first sub-pixel electrode 191a and may be approximately 1 to 3 times.

The first sub-pixel electrode 191a and the second sub-pixel electrode 191b are entirely rectangular in shape and each of the first sub-pixel electrode 191a and the second sub-pixel electrode 191b includes a lateral stripe portion 193a, 193b And vertical stem portions 192a and 192b intersecting the horizontal stem portions 193a and 193b. The first sub-pixel electrode 191a and the second sub-pixel electrode 191b are protruded upward or downward from the side edges of the plurality of fine branch portions 194a and 194b and the sub-pixel electrodes 191a and 191b, respectively. (197a, 197b).

The pixel electrode 191 is divided into four sub-regions by the horizontal line bases 193a and 193b and the vertical line bases 192a and 192b. The fine branch portions 194a and 194b extend obliquely from the transverse trunk portions 193a and 193b and the trunk base portions 192a and 192b and extend in the direction of the gate lines 121a and 121b or the transverse trunk portions 193a and 193b ) And an angle of about 45 degrees or 135 degrees. Further, directions in which the fine branch portions 194a and 194b of the neighboring two sub-regions extend may be orthogonal to each other.

The first sub-pixel electrode 191a further includes an outline trunk portion surrounding the outer sub-pixel electrode 191a. The second sub-pixel electrode 191b includes a transverse portion and a first sub-pixel electrode 191a located at the upper and lower ends, And left and right vertical portions 198 positioned on the left and right sides of the left and right vertical portions 198, respectively. The left and right vertical portions 198 can prevent capacitive coupling, i.e., coupling, between the data line 171 and the first sub-pixel electrode 191a.

The lower alignment layer 11, the micro space layer 400, the upper alignment layer 21, the common electrode 270, the first lid 250 and the capping layer 280 are formed on the pixel electrode 191, The description of these components will be omitted hereinbefore.

The description of the liquid crystal display device described so far is an example of a visible structure for improving lateral visibility. The structure of the thin film transistor and the pixel electrode design are not limited to the structure described in this embodiment, The contents according to the example can be applied.

Hereinafter, an embodiment of manufacturing the above-described liquid crystal display device will be described with reference to FIGS. 6 to 12. FIG. FIGS. 6 to 12 are sectional views taken along line III-III of FIG. 1 and FIG. 2 in order to illustrate a method of manufacturing a liquid crystal display device according to an embodiment of the present invention.

Referring to FIG. 6, thin film transistors Qa, Qb, Qc (shown in FIG. 1) are formed on a substrate 110 made of transparent glass or plastic. The organic film 230 is formed on the thin film transistors Qa, Qb and Qc so as to correspond to the pixel region and the light blocking member 220a and the vertical light blocking member 220b, Member 220 is formed. As shown in FIG. 6, the longitudinal light shielding member 220b overlaps the edge of the neighboring organic film 230. As the vertical shielding member 220b overlaps the organic film 230 a lot, a level difference may occur due to the leveling effect. When forming the vertical shading member 220b, the gap between the organic film 230 and the organic film 230 may be adjusted to control the level difference and prevent the level difference from being generated.

Here, the organic film 230 may be a color filter.

Referring to FIG. 7, a lower protective film 170 is formed on the organic film 230 and the light shielding member 220. The lower protective film 170 may be formed of an organic material. The lower protection film 170 is patterned to form a trench SP having a first width w1 which is elongated in the longitudinal direction. As shown in FIG. 2, the trench SP is located between neighboring pixels in the transverse direction, and the trench SP may be located at a portion where the organic film 230 and the vertical shielding member 220b overlap.

Referring to FIG. 8, an upper protective layer 180 is formed on the lower protective layer 170. The upper protective film 180 may be formed of an inorganic material such as silicon oxide or silicon nitride, and is not necessarily required, and thus may be omitted. After the pixel electrode material is formed on the lower protective layer 180, the pixel electrode material is patterned such that the pixel electrode 191 is located at a portion corresponding to the pixel region. At this time, the pixel electrode 191 is in contact with the contact holes 185a, 185b (shown in FIG. 1) to one terminal of the thin film transistor Qa, Qb. The pixel electrode 191 formed by patterning the pixel electrode material may have a shape as shown in FIG. 2. However, the shape of the pixel electrode 191 is not limited thereto.

Referring to FIG. 9, a sacrificial layer 300 including silicon oxycarbide (SiOC) or a photoresist is formed on the pixel electrode 191. The sacrificial layer 300 may be formed of an organic material other than silicon oxycarbide (SiOC) or photoresist.

The sacrificial layer 300 is patterned to form an open portion OPN on the vertical shielding member 200b. The open portion OPN can distinguish the neighboring fine space layers 400 in the transverse direction.

A common electrode 270 and a first cover film 250 are sequentially formed on the sacrificial layer 300. The common electrode 270 may be formed of a transparent conductor such as ITO or IZO and the first cover film 250 may be formed of silicon nitride (SiNx) or silicon oxide (SiO2). The common electrode 260 and the first cover layer 250 may cover the open portion OPN between the fine space layers 400.

Referring to FIG. 10, a support member 260 and a second lid 240 are formed on the first lid 250 in this order. The support member 260 according to the present embodiment may be formed of a different material from the sacrificial layer 300 formed before. The second cover film 240 may be formed of silicon nitride (SiNx) or silicon oxide (SiO2).

Fig. 11 is a cross-sectional view taken along the line IV-IV in Fig. 1, and shows the structure in the step of Fig. 11, the support member 260 is patterned to form a groove GRV exposing the first cover film 250 corresponding to the lateral light shielding member 220a before the second cover film 240 is formed, Can be formed. The sacrificial film 300 is exposed by sequentially patterning the protective film 240, the first cover film 250 and the common electrode 270 located at the portions corresponding to the grooves GRV, (300) is removed by an oxygen (O2) ashing process or a wet etching process. At this time, the micro space layer 400 having the liquid crystal injection hole A is formed. The micro-space layer 400 is in an empty state after the sacrificial layer 300 is removed. The liquid crystal injection hole A may be formed along a direction parallel to a signal line connected to one terminal of the thin film transistor. When the sacrificial layer 300 is removed, the common electrode 270, the first cover layer 250, and the support member 260 cover the open portion OPN as shown in FIG. 10, To form the edge sidewall portion of the layer (400).

12, an alignment material is injected through the liquid crystal injection hole A shown in FIG. 11 to form alignment films 11 and 21 on the pixel electrode 191 and the common electrode 270. FIG. After the alignment material including the solid content and the solvent is injected through the liquid crystal injection port (A), the baking process is performed. At this time, as the solvent of the alignment material is volatilized, the solid content remaining after forming the alignment film is guided to the trench SP while drying proceeds toward the liquid crystal injection port (A). The solid part derived by the trench SP is drawn into the entrance part EP shown in Fig. 2, or remains in the trench SP, the trench SP becomes an area not visible by the vertical light shielding member 220b It can prevent light leakage phenomenon. The width w1 of the trench SP is formed to be less than the cell gap, and a strong traction force acts on this portion, so that the remaining solid portion can be led to the trench SP.

Next, a liquid crystal material including the liquid crystal molecules 310 is injected into the fine space layer 400 through the liquid crystal injection port A by using an inkjet method or the like.

A capping layer 280 is formed to cover the upper surface and the side wall of the support member 260. The capping layer 280 is formed on the surface of the liquid crystal injection hole A and the liquid crystal display device shown in Figs. 3 and 4 can be formed.

13 is a plan view showing a liquid crystal display device according to an embodiment of the present invention. 14 is a cross-sectional view taken along line XIV-XIV in Fig.

13 and 14, most of the configuration is the same as the embodiment described with reference to Figs. 1, 3, and 4. Fig. However, as shown in FIG. 13, the trenches SP extending in the longitudinal direction extend in the lateral direction at both edge portions of the micro-space layer 400 to form the storage trench SP1. The storage trench SP1 is formed in the inlet EP and the remaining solids in the microporous layer 400 can be drawn along the trench SP to the inlet EP and collected in the storage trench SP1. The width w2 of the storage trench SP1 can be adjusted within an interval of the inlet portion EP.

In the present embodiment, the entrance part EP is a part where the light shielding member 220 is formed, and when the remaining solid part is gathered in the storage trench SP1, an alignment film oriented vertically to the entrance part EP may be formed. Since the vertically aligned alignment film makes a black state, there is an advantage that the material of the light shielding member formed at the entrance part (EP) can be reduced.

The embodiment described in Figures 13 and 14, except for the difference in the addition of the storage trench SP1 in the embodiment described in Figures 1, 3 and 4, It is applicable to this embodiment.

Hereinafter, one embodiment of manufacturing the above-described liquid crystal display device will be described with reference to FIGS. 15 to 21. FIG. FIGS. 15 to 21 are sectional views taken along line XIV-XIV of FIG. 13 in order to illustrate a method of manufacturing a liquid crystal display device according to an embodiment of the present invention.

Referring to FIG. 15, thin film transistors Qa, Qb, Qc (shown in FIG. 1) are formed on a substrate 110 made of transparent glass or plastic. The organic film 230 is formed on the thin film transistors Qa, Qb and Qc so as to correspond to the pixel region and the light blocking member 220a and the vertical light blocking member 220b, Member 220 is formed. As shown in FIG. 15, the transverse light shielding member 220a overlaps the edge of the neighboring organic film 230. As shown in FIG. As the lateral light shielding member 220a overlaps the organic film 230 a lot, a level difference may occur due to the leveling effect. When forming the lateral light shielding member 220a, the gap between the organic light shielding layer 230 and the organic layer 230 may be adjusted so that the level difference can be adjusted.

Here, the organic film 230 may be a color filter.

A lower protective film 170 is formed on the organic film 230 and the light shielding member 220. The lower protective film 170 may be formed of an organic material. The lower protective film 170 is patterned to form a storage trench SP1 extending in the lateral direction and having a second width L2. As shown in Fig. 13, the storage trench SP1 overlaps the lateral light shielding member 220a because it is formed in the entrance portion EP. The storage trench SP1 can be formed simultaneously with the trench SP extending in the longitudinal direction and having the first width w1.

Referring to FIG. 16, an upper protective layer 180 is formed on the lower protective layer 170. The upper protective film 180 may be formed of an inorganic material such as silicon oxide or silicon nitride, and is not necessarily required, and thus may be omitted. After the pixel electrode material is formed on the upper protective layer 180, the pixel electrode material is patterned such that the pixel electrode 191 is positioned at a portion corresponding to the pixel region. At this time, the pixel electrode 191 is in contact with the contact holes 185a, 185b (shown in FIG. 1) to one terminal of the thin film transistor Qa, Qb. The pixel electrode 191 formed by patterning the pixel electrode material may have the shape shown in FIG. 13, but the present invention is not limited thereto, and the design of the pixel electrode 191 may be modified.

A sacrificial layer 300 including silicon oxycarbide (SiOC) or a photoresist is formed on the pixel electrode 191. [ The sacrificial layer 300 may be formed of an organic material other than silicon oxycarbide (SiOC) or photoresist.

Referring to FIG. 17, a common electrode 270, a first cover film 250, and a support member 260 are sequentially formed on a sacrificial layer 300. The common electrode 270 may be formed of a transparent conductor such as ITO or IZO and the first cover film 250 may be formed of silicon nitride (SiNx) or silicon oxide (SiO2). The support member 260 according to the present embodiment may be formed of a different material from the sacrificial layer 300 formed before.

The support member 260 is patterned to form a groove GRV exposing the first cover film 250 of the portion corresponding to the light shielding member 220a.

Referring to FIG. 18, a second cover film 240 is formed to cover the exposed first cover film 250 and the support member 260. The second cover film 240 may be formed of silicon nitride (SiNx) or silicon oxide (SiO2).

19, the sacrificial layer 300 is exposed by sequentially patterning the second cover layer 240, the first cover layer 250, and the common electrode 270, which are located at a portion corresponding to the groove GRV . At this time, a part of the sacrifice film 300 corresponding to the groove GRV can be removed.

Referring to FIG. 20, the sacrificial layer 300 is removed through an oxide (O ₂ ) ashing process or a wet etching process through a groove GRV. At this time, the micro space layer 400 having the liquid crystal injection hole A is formed. In this case, the sacrificial layer 300 is removed from the micro-space layer 400 to form an empty space. The liquid crystal injection hole A may be formed along a direction parallel to a signal line connected to one terminal of the thin film transistor.

Referring to FIG. 21, alignment materials 11 and 21 are formed on the pixel electrode 191 and the common electrode 270 by injecting an alignment material through the liquid crystal injection hole A shown in FIG. After the alignment material including the solid content and the solvent is injected through the liquid crystal injection port (A), the baking process is performed. At this time, as the solvent of the alignment material is volatilized, the solid content remaining after forming the alignment film is guided to the trench SP shown in Fig. 12 while drying proceeds toward the liquid crystal injection port (A). Solids derived from the trench SP are attracted to the inlet portion EP shown in Fig. 13 and gathered in the storage trench SP1. The width w2 of the storage trench SP1 can be formed to be within the interval of the inlet portion EP.

22 is a plan view schematically illustrating the shape of the micro-space layer according to an embodiment of the present invention. 23 is a cross-sectional view taken along line XXIII-XXIII in FIG. 22. FIG.

The embodiment described in Figs. 22 and 23 is almost the same as the embodiment described in Figs. 1 to 5, but the trench SP structure shown in Figs. 2 and 3 is not formed. Instead, a non-linear portion (NSLP), which functions similarly to the trench (SP) structure, is formed in the edge portion of the micro-space layer 400. The contents described in Figs. 1 to 5 are applicable to the present embodiment, except for such differences.

22, a plurality of micro-space layers 400 are formed in the form of a matrix, and the micro-space layer 400 is adjacent to the longitudinal direction with grooves GRV interposed therebetween. 23, the neighboring fine space layer 400 in the transverse direction is divided by the open portion OPN and includes a common electrode 270 covering the open portion OPN, a first cover film 250, The support member 260 forms a sidewall portion 400w of a kind of micro-space layer 400. [

The nonlinear portion NSLP of the fine space layer 400 does not appear well because the sectional shape is shown in FIG. 23, but a nonlinear portion NSLP is formed on the side wall portion 400w of the fine space layer 400 And that the nonlinear portion NSLP is formed in a linear zigzag shape, by referring to FIG. The pitch d of the repetitive shape of the nonlinear portion NSLP is preferably equal to or smaller than the cell gap of the liquid crystal layer.

The nonlinear portion NSLP is formed at the edge portion of the microspace layer 400 as in the present embodiment and the alignment solution is injected along the liquid crystal injection port A of the microspace layer 400 and dried, The phenomenon of light leakage and the like are minimized. If the pitch d of the nonlinear portion NSLP is less than the cell gap of the liquid crystal layer, the capillary force of the nonlinear portion NSLP structure becomes higher than the capillary force of the fine space layer 400, NSLP). The solid part remaining after drying spreads on the nonlinear part (NSLP), thereby preventing the solid part from aggregating. The nonlinear portion NSLP of the fine space layer 400 is located at a portion overlapping the light shielding member 220, so that the light can be blocked. In addition, there is an effect that the sidewall of the edge portion of the fine space layer 400 is flattened by appropriately filling solid portions in the irregular portion of the non-linear portion NSLP.

Referring to FIG. 24, the nonlinear portion NSLP of the micro space layer 400 according to the present embodiment is not limited to the zigzag shape, and may be formed in a zigzag shape of a circle, trapezoid, rectangle, or triangle.

25 to 31 are a plan view and a cross-sectional view illustrating a method of manufacturing a liquid crystal display device according to an embodiment of the present invention.

25 and 26, thin film transistors Qa, Qb, Qc (shown in FIG. 1) are formed on a substrate 110 made of transparent glass or plastic. The organic film 230 is formed on the thin film transistors Qa, Qb and Qc so as to correspond to the pixel region and the light blocking member 220a and the vertical light blocking member 220b, Member 220 is formed. As shown in FIG. 26, the longitudinal light shielding member 220b overlaps the edge of the neighboring organic film 230. FIG.

After the pixel electrode material is formed on the organic layer 230, the pixel electrode material is patterned such that the pixel electrode 191 is located at a portion corresponding to the pixel region.

Referring to FIGS. 27 and 28, a sacrificial layer 300 including silicon oxycarbide (SiOC) or a photoresist is formed on the pixel electrode 191. The sacrificial layer 300 may be formed of an organic material other than silicon oxycarbide (SiOC) or photoresist.

The sacrificial layer 300 is patterned to form an open portion OPN on the vertical shielding member 200b. The open portion OPN can distinguish the neighboring fine space layers 400 in the transverse direction. At this time, according to this embodiment, a non-linear portion NSLP is formed at the edge portion of the sacrificial film 300 so as to include the concavo-convex portion PTP as shown in Fig. As described above, it is preferable that the pitch of the projections and depressions PTP is formed to be equal to or smaller than the cell gap of the liquid crystal layer.

Referring to FIG. 29, a common electrode 270 and a first lid 250 are sequentially formed on a sacrificial layer 300. The common electrode 270 may be formed of a transparent conductor such as ITO or IZO and the first cover film 250 may be formed of silicon nitride (SiNx) or silicon oxide (SiO2). The common electrode 260 and the first cover layer 250 may cover the open portion OPN between the fine space layers 400.

30 and 31, a second cover film 240 is formed on the support member 260 after the support member 260 having the groove GRV formed on the first cover film 250 is formed. Thereafter, the process proceeds similar to the previously described embodiment to sequentially pattern the second cover film 240, the first cover film 250, and the common electrode 270 located at the portion corresponding to the groove GRV, The sacrificial layer 300 is exposed, and the sacrificial layer 300 is removed by an ashing process or a wet etching process. When the sacrifice layer 300 is removed, a micro-space layer 400 having a liquid crystal injection hole A is formed.

When the sacrificial layer 300 is removed, the common electrode 270, the first cover layer 250, and the support member 260 cover the open portion OPN as shown in FIG. 31, To form the edge sidewall portion of the layer (400). The portions corresponding to the edge sidewall portions of the micropipolar layer 400 are formed such that the shapes of the nonlinear portions NSLP of the sacrificial layer 300 remain unchanged, A straight line portion NSLP is formed.

31, an alignment material is injected through the liquid crystal injection hole A shown in FIG. 30 to form alignment films 11 and 21 on the pixel electrode 191 and the common electrode 270. FIG. After the alignment material including the solid content and the solvent is injected through the liquid crystal injection port (A), the baking process is performed. At this time, the solvent of the alignment material is volatilized, and the solid content remaining after forming the alignment film is guided to the nonlinear portion NSLP of the fine space layer 400 while drying proceeds toward the liquid crystal injection port (A). Even if the solid portion induced by the non-straight line portion NSLP remains, if the concave / convex portion PTP is formed on the vertical light shielding member 220b, the light leakage phenomenon can be blocked because the portion is not visually recognized.

A liquid crystal material including the liquid crystal molecules 310 is injected through the liquid crystal injection hole A and a capping film (not shown) is formed to cover the upper surface and the side walls of the support member 260, .

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, Of the right.

220 Light blocking member 230 Organic film
191 pixel electrode 300 sacrificial film
250 cover membrane 260 support member
270 common electrode 400 fine space layer
SP trench NSLP non-linear portion

Claims (19)

Board,
A first pixel electrode and a second pixel electrode disposed on the substrate,
A supporting member spaced apart from the first pixel electrode and the second pixel electrode,
A first micro-spatial layer positioned between the first pixel electrode and the support member, a second micro-spatial layer positioned between the second pixel electrode and the support member,
A protective film located between the substrate and the first micro-space layer and between the substrate and the second micro-space layer,
Wherein a plurality of trenches are formed on an upper surface of the protective film and the plurality of trenches are formed in at least one of both edge portions of the first micropace layer and both edge portions of the second micropace layer, A storage trench is formed on the top surface of the protective film,
Wherein a groove is formed adjacent to the first liquid crystal injection port of the first micro-space layer and the second liquid crystal injection port of the second micro-space layer, and the storage trench overlaps with the groove. The method of claim 1,
Further comprising a thin film transistor located between the substrate and the protective film,
Wherein each of the plurality of trenches is formed along a signal line connected to the thin film transistor. The method of claim 1,
An open portion is formed between the first micro-space layer and the second micro-space layer, and the support member is formed in the open portion to partition the first micro-space layer and the second micro-space layer,
Wherein the trench is formed in at least one of an edge portion of the first micro-space layer and an edge portion of the second micro-space layer adjacent to the open portion. 4. The method of claim 3,
Further comprising a thin film transistor located between the substrate and the protective film,
Wherein the open portion extends along a direction parallel to a signal line connected to the thin film transistor. 5. The method of claim 4,
Further comprising a capping film located on the support member and covering the first liquid crystal injection port and the second liquid crystal injection port,
Wherein the grooves are located between adjacent micro-space layers in a direction in which the open portions extend,
And the capping film covers the groove. The method of claim 1,
An organic film disposed on the substrate,
Further comprising a light shielding member positioned between the organic films,
Wherein the trench is positioned so as to correspond to a portion where the organic film and the light shielding member overlap. The method of claim 1,
A liquid crystal material is injected into the first micro-space layer and the second micro-space layer to form a liquid crystal layer,
Wherein a width of the trench is equal to or less than a cell gap of the liquid crystal layer. delete delete The method of claim 1,
Further comprising a capping film located on the support member and covering the first liquid crystal injection port and the second liquid crystal injection port,
And the groove is filled with the capping film. Forming a protective film having a plurality of trenches on the substrate,
Forming a first pixel electrode and a second pixel electrode on the protective film,
Forming a sacrificial layer on the first pixel electrode and the second pixel electrode,
Forming a support member on the sacrificial layer,
Removing the sacrificial layer to form a first micro-space layer and a second micro-space layer, each having a liquid crystal injection port,
Forming an alignment layer on the inner walls of the first micro-space layer and the second micro-space layer,
Forming a liquid crystal layer including a liquid crystal material on the first micro-space layer and the second micro-space layer, and
And forming a capping film on the support member so as to cover the liquid crystal injection port,
Wherein the plurality of trenches are formed on an upper surface of the protective film and the plurality of trenches are formed in at least one of the both edge portions of the first micropace layer and the both edge portions of the second micropace layer, A storage trench connecting the trenches is formed on the top surface of the protective film,
Wherein a groove is formed adjacent to the first liquid crystal injection port of the first micro-space layer and the second liquid crystal injection port of the second micro-space layer, and the storage trench overlaps with the groove. 12. The method of claim 11,
Further comprising forming a thin film transistor between the substrate and the protective film,
Wherein each of the plurality of trenches is formed along a signal line connected to the thin film transistor. 12. The method of claim 11,
Further comprising patterning the sacrificial layer to form an open portion, at least one of the plurality of trenches having at least one of an edge portion of the first micro-space layer adjacent to the open portion and an edge portion of the second micro- In the liquid crystal display device. The method of claim 13,
Further comprising forming a thin film transistor between the substrate and the protective film,
Wherein the open portion extends along a direction parallel to a signal line connected to the thin film transistor. The method of claim 14,
Wherein the groove is formed by patterning the support member,
Wherein the grooves are formed between the adjacent fine space layers in a direction in which the open portions extend. 12. The method of claim 11,
Forming an organic film on the substrate,
Further comprising the step of forming a light shielding member between the organic films,
And the plurality of trenches are formed so as to correspond to a portion where the organic film and the light shielding member overlap each other. 12. The method of claim 11,
Wherein a width of the trench is less than a cell gap of the liquid crystal layer. delete delete

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